From 586b15bce82a2161dbe71991c14c8c36f5683033 Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Sun, 29 Mar 2020 20:57:39 +0300 Subject: common/board_f: Move arm-specific reserve_mmu to arch/arm/lib/cache.c Move the ARM-specific reserve_mmu definition from common/board_f.c to arch/arm/lib/cache.c. Signed-off-by: Ovidiu Panait Reviewed-by: Simon Glass --- arch/arm/lib/cache.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm/lib/cache.c') diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 007d4ebc49..b8e1e340a1 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -10,6 +10,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + /* * Flush range from all levels of d-cache/unified-cache. * Affects the range [start, start + size - 1]. @@ -118,3 +120,29 @@ void invalidate_l2_cache(void) isb(); } #endif + +__weak int reserve_mmu(void) +{ +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + /* reserve TLB table */ + gd->arch.tlb_size = PGTABLE_SIZE; + gd->relocaddr -= gd->arch.tlb_size; + + /* round down to next 64 kB limit */ + gd->relocaddr &= ~(0x10000 - 1); + + gd->arch.tlb_addr = gd->relocaddr; + debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + /* + * Record allocated tlb_addr in case gd->tlb_addr to be overwritten + * with location within secure ram. + */ + gd->arch.tlb_allocated = gd->arch.tlb_addr; +#endif +#endif + + return 0; +} -- cgit From 6184858b859f6fcea4b23f76cfb7988882a3c8a7 Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Sun, 29 Mar 2020 20:57:40 +0300 Subject: arm: asm/cache.c: Introduce arm_reserve_mmu As a preparation for turning reserve_mmu into an arch-specific variant, introduce arm_reserve_mmu on ARM. It implements the default routine for reserving memory for MMU TLB and needs to be weakly defined in order to allow for machines to override it. Without this decoupling, after introducing arch_reserve_mmu, there would be two weak definitions for it, one in common/board_f.c and one in arch/arm/lib/cache.c. Signed-off-by: Ovidiu Panait Reviewed-by: Simon Glass --- arch/arm/lib/cache.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/lib/cache.c') diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index b8e1e340a1..3cbed602eb 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -122,6 +122,11 @@ void invalidate_l2_cache(void) #endif __weak int reserve_mmu(void) +{ + return arm_reserve_mmu(); +} + +__weak int arm_reserve_mmu(void) { #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) /* reserve TLB table */ -- cgit From 79926e4f2f3cf84c65188c59ea1e93d6b221d36b Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Sun, 29 Mar 2020 20:57:41 +0300 Subject: common/board_f: Make reserve_mmu generic Introduce arch_reserve_mmu to allow for architecture-specific reserve_mmu routines. Also, define a weak nop stub for it. Signed-off-by: Ovidiu Panait Reviewed-by: Simon Glass --- arch/arm/lib/cache.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/lib/cache.c') diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 3cbed602eb..44dde26065 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -121,7 +121,7 @@ void invalidate_l2_cache(void) } #endif -__weak int reserve_mmu(void) +int arch_reserve_mmu(void) { return arm_reserve_mmu(); } -- cgit