From ef70a42f0ffc6b43f719810c4e3861c55c2eefbc Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Tue, 10 Oct 2017 16:21:01 +0200 Subject: arm: boot0 hook: move boot0 hook before '_start' The boot0 hook on ARM does not insert its payload before the vector table. This is both a mismatch with thec comment above it and contradict usage of the boot0 hook on ARM64. To fix this (and unify the semantics for ARM and ARM64), we change the boot0-hook semantics on ARM to match those on ARM64: (1) if a boot0-hook is present it is inserted at the start of the image (2) if a boot0-hook is present, emitting the ARM vector table (and the _start) symbol are suppressed in vectors.S and the boot0-hook has full control over where and when it wants to emit these Signed-off-by: Philipp Tomsich --- arch/arm/lib/vectors.S | 54 ++++++++++++++++++++++++++++++++------------------ 1 file changed, 35 insertions(+), 19 deletions(-) (limited to 'arch/arm/lib') diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index 101909103e..9cb0d2ef36 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -15,6 +15,22 @@ #include +/* + * A macro to allow insertion of an ARM exception vector either + * for the non-boot0 case or by a boot0-header. + */ + .macro ARM_VECTORS + b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + .endm + + /* ************************************************************************* * @@ -35,6 +51,23 @@ .section ".vectors", "ax" +#if defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK) +/* + * Various SoCs need something special and SoC-specific up front in + * order to boot, allow them to set that in their boot0.h file and then + * use it here. + * + * To allow a boot0 hook to insert a 'special' sequence after the vector + * table (e.g. for the socfpga), the presence of a boot0 hook supresses + * the below vector table and assumes that the vector table is filled in + * by the boot0 hook. The requirements for a boot0 hook thus are: + * (1) defines '_start:' as appropriate + * (2) inserts the vector table using ARM_VECTORS as appropriate + */ +#include + +#else + /* ************************************************************************* * @@ -46,28 +79,11 @@ */ _start: - #ifdef CONFIG_SYS_DV_NOR_BOOT_CFG .word CONFIG_SYS_DV_NOR_BOOT_CFG #endif - - b reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -#ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK -/* - * Various SoCs need something special and SoC-specific up front in - * order to boot, allow them to set that in their boot0.h file and then - * use it here. - */ -#include -#endif + ARM_VECTORS +#endif /* !defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK) */ /* ************************************************************************* -- cgit From b4806d6f1f82f0a2d76b7206bdc5e4ba7d567b6f Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Tue, 10 Oct 2017 16:21:13 +0200 Subject: arm: provide a PCS-compliant setjmp implementation The previous setjmp-implementation (as a static inline function that contained an 'asm volatile' sequence) was extremely fragile: (some versions of) GCC optimised the set of registers. One critical example was the removal of 'r9' from the clobber list, if -ffixed-reg9 was supplied. To increase robustness and ensure PCS-compliant behaviour, the setjmp and longjmp implementation are now in assembly and closely match what one would expect to find in a libc implementation. Signed-off-by: Philipp Tomsich Tested-by: Andy Yan --- arch/arm/lib/Makefile | 6 ++++++ arch/arm/lib/setjmp.S | 37 +++++++++++++++++++++++++++++++++++++ arch/arm/lib/setjmp_aarch64.S | 42 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 85 insertions(+) create mode 100644 arch/arm/lib/setjmp.S create mode 100644 arch/arm/lib/setjmp_aarch64.S (limited to 'arch/arm/lib') diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 6e1c436933..abffa10c85 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -17,6 +17,12 @@ else obj-y += vectors.o crt0.o endif +ifdef CONFIG_ARM64 +obj-y += setjmp_aarch64.o +else +obj-y += setjmp.o +endif + ifndef CONFIG_SPL_BUILD ifdef CONFIG_ARM64 obj-y += relocate_64.o diff --git a/arch/arm/lib/setjmp.S b/arch/arm/lib/setjmp.S new file mode 100644 index 0000000000..6746e5e2cc --- /dev/null +++ b/arch/arm/lib/setjmp.S @@ -0,0 +1,37 @@ +/* + * (C) 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +.pushsection .text.setjmp, "ax" +ENTRY(setjmp) + /* + * A subroutine must preserve the contents of the registers + * r4-r8, r10, r11 (v1-v5, v7 and v8) and SP (and r9 in PCS + * variants that designate r9 as v6). + */ + mov ip, sp + stm a1, {v1-v8, ip, lr} + mov a1, #0 + bx lr +ENDPROC(setjmp) +.popsection + +.pushsection .text.longjmp, "ax" +ENTRY(longjmp) + ldm a1, {v1-v8, ip, lr} + mov sp, ip + mov a1, a2 + /* If we were passed a return value of zero, return one instead */ + cmp a1, #0 + bne 1f + mov a1, #1 +1: + bx lr +ENDPROC(longjmp) +.popsection diff --git a/arch/arm/lib/setjmp_aarch64.S b/arch/arm/lib/setjmp_aarch64.S new file mode 100644 index 0000000000..b68edb86d6 --- /dev/null +++ b/arch/arm/lib/setjmp_aarch64.S @@ -0,0 +1,42 @@ +/* + * (C) 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +.pushsection .text.setjmp, "ax" +ENTRY(setjmp) + /* Preserve all callee-saved registers and the SP */ + stp x19, x20, [x0,#0] + stp x21, x22, [x0,#16] + stp x23, x24, [x0,#32] + stp x25, x26, [x0,#48] + stp x27, x28, [x0,#64] + stp x29, x30, [x0,#80] + mov x2, sp + str x2, [x0, #96] + mov x0, #0 + ret +ENDPROC(setjmp) +.popsection + +.pushsection .text.longjmp, "ax" +ENTRY(longjmp) + ldp x19, x20, [x0,#0] + ldp x21, x22, [x0,#16] + ldp x23, x24, [x0,#32] + ldp x25, x26, [x0,#48] + ldp x27, x28, [x0,#64] + ldp x29, x30, [x0,#80] + ldr x2, [x0,#96] + mov sp, x2 + /* Move the return value in place, but return 1 if passed 0. */ + adds x0, xzr, x1 + csinc x0, x0, xzr, ne + ret +ENDPROC(longjmp) +.popsection -- cgit