From f7cf291aa788eb5b64c0d16de529b1a378f509bb Mon Sep 17 00:00:00 2001 From: Samuel Mescoff Date: Tue, 16 Feb 2016 09:45:06 +0100 Subject: ARM: at91: sama5d2: configure the L2 cache memory MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SAMA5D2 has a second internal SRAM that can be reassigned as a L2 cache memory. Make sure it is configured as a L2 cache memory when booting from a SPL image. Based on the commit b5ea95ef2b5b from the at91bootstrap repository. Signed-off-by: Samuel Mescoff Reviewed-by: Wenyou Yang Reviewed-by: Andreas Bießmann --- arch/arm/mach-at91/atmel_sfr.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/mach-at91/atmel_sfr.c') diff --git a/arch/arm/mach-at91/atmel_sfr.c b/arch/arm/mach-at91/atmel_sfr.c index 2bccb840c1..adf44c6a94 100644 --- a/arch/arm/mach-at91/atmel_sfr.c +++ b/arch/arm/mach-at91/atmel_sfr.c @@ -19,3 +19,10 @@ void redirect_int_from_saic_to_aic(void) writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir); } } + +void configure_2nd_sram_as_l2_cache(void) +{ + struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; + + writel(1, &sfr->l2cc_hramc); +} -- cgit