From 2444dae587815e5ba14cb27c32f57bc3b3bbed1d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 30 Aug 2015 16:55:38 -0600 Subject: rockchip: Add core SoC start-up code Add code for starting up U-Boot SPL and U-Boot proper. This is generic and makes use of devices provided by the board- or SoC-specific code. Signed-off-by: Simon Glass --- arch/arm/mach-rockchip/board.c | 46 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 arch/arm/mach-rockchip/board.c (limited to 'arch/arm/mach-rockchip/board.c') diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c new file mode 100644 index 0000000000..688bc0ffde --- /dev/null +++ b/arch/arm/mach-rockchip/board.c @@ -0,0 +1,46 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + struct ram_info ram; + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return ret; + } + ret = ram_get_info(dev, &ram); + if (ret) { + debug("Cannot get DRAM size: %d\n", ret); + return ret; + } + debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size); + gd->ram_size = ram.size; + + return 0; +} + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif -- cgit