From 975e4abad2fabfb8aa3f0391e0ef07cc3aede905 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Fri, 23 Jun 2017 16:11:11 +0800 Subject: rockchip: correct the bank0 ram size The bank0 ram size should be the DRAM size minus reserved size, the DRAM size may be 1GB, 2GB, 4GB, we can not hard code it. Signed-off-by: Kever Yang Reviewed-by: Philipp Tomsich Added DECLARE_GLOBAL_DATA_PTR for RK3328, RK3368 and RK3399: Signed-off-by: Philipp Tomsich --- arch/arm/mach-rockchip/rk3328/rk3328.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm/mach-rockchip/rk3328') diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c index cec6f905f6..6764494d3b 100644 --- a/arch/arm/mach-rockchip/rk3328/rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -9,6 +9,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + static struct mm_region rk3328_mem_map[] = { { .virt = 0x0UL, @@ -31,6 +33,17 @@ static struct mm_region rk3328_mem_map[] = { struct mm_region *mem_map = rk3328_mem_map; +int dram_init_banksize(void) +{ + size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top); + + /* Reserve 0x200000 for ATF bl31 */ + gd->bd->bi_dram[0].start = 0x200000; + gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start; + + return 0; +} + int arch_cpu_init(void) { /* We do some SoC one time setting here. */ -- cgit