From 21143ce127b953356bd6174fb4e4892af3a92d0f Mon Sep 17 00:00:00 2001 From: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Date: Thu, 28 Dec 2017 15:09:02 +0300 Subject: SOCFPGA: clock manager: implement dw_spi_get_clk function Implement dw_spi_get_clk function to override its weak implementation in designware_spi.c driver. We need this change to get rid of cm_get_spi_controller_clk_hz function and clock_manager.h include in designware_spi.c driver. Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@openedev.com> --- arch/arm/mach-socfpga/clock_manager_arria10.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/mach-socfpga/clock_manager_arria10.c') diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c index 482b8543f4..623a266f80 100644 --- a/arch/arm/mach-socfpga/clock_manager_arria10.c +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c @@ -7,6 +7,7 @@ #include <common.h> #include <fdtdec.h> #include <asm/io.h> +#include <dm.h> #include <asm/arch/clock_manager.h> DECLARE_GLOBAL_DATA_PTR; @@ -1076,6 +1077,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void) return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB); } +/* Override weak dw_spi_get_clk implementation in designware_spi.c driver */ +int dw_spi_get_clk(struct udevice *bus, ulong *rate) +{ + *rate = cm_get_spi_controller_clk_hz(); + + return 0; +} + void cm_print_clock_quick_summary(void) { printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000); -- cgit