From a6e5b06bea5f6bd98c184f1049e49ebd123538c7 Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Wed, 27 Nov 2019 15:55:25 +0800 Subject: arm: agilex: Add clock handoff offset for Agilex Add clock handoff offset for Agilex. Remove S10 prefix to avoid confusion. Signed-off-by: Ley Foon Tan Reviewed-by: Simon Goldschmidt --- arch/arm/mach-socfpga/wrap_pll_config_s10.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-socfpga/wrap_pll_config_s10.c') diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c index b266a5817b..3da85791a1 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c +++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c @@ -33,7 +33,8 @@ const struct cm_config * const cm_get_default_config(void) const unsigned int cm_get_osc_clk_hz(void) { #ifdef CONFIG_SPL_BUILD - u32 clock = readl(S10_HANDOFF_CLOCK_OSC); + + u32 clock = readl(HANDOFF_CLOCK_OSC); writel(clock, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD1); @@ -50,7 +51,7 @@ const unsigned int cm_get_intosc_clk_hz(void) const unsigned int cm_get_fpga_clk_hz(void) { #ifdef CONFIG_SPL_BUILD - u32 clock = readl(S10_HANDOFF_CLOCK_FPGA); + u32 clock = readl(HANDOFF_CLOCK_FPGA); writel(clock, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD2); -- cgit