From 7656d3982a39127f38d5be4ab4e3f61500739ba7 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 15 Jul 2019 02:27:08 +0100 Subject: sunxi: H6: Add DDR3-1333 timings Add a routine to program the timing parameters for DDR3-1333 DRAM chips connected to the H6 DRAM controller. The values were gathered from doing back-calculations from a register dump, trying to match them up with the official JEDEC DDDR3 spec. If in doubt, the register dump values were taken for now, but the JEDEC recommendation were added as a comment. Many thanks to Jernej for contributing fixes! Signed-off-by: Andre Przywara Tested-by: Jernej Skrabec Reviewed-by: Jernej Skrabec Reviewed-by: Jagan Teki --- arch/arm/mach-sunxi/dram_timings/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/mach-sunxi/dram_timings/Makefile') diff --git a/arch/arm/mach-sunxi/dram_timings/Makefile b/arch/arm/mach-sunxi/dram_timings/Makefile index 0886a95968..0deb9911fd 100644 --- a/arch/arm/mach-sunxi/dram_timings/Makefile +++ b/arch/arm/mach-sunxi/dram_timings/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_SUNXI_DRAM_DDR3_1333) += ddr3_1333.o obj-$(CONFIG_SUNXI_DRAM_LPDDR3_STOCK) += lpddr3_stock.o obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S) += ddr2_v3s.o obj-$(CONFIG_SUNXI_DRAM_H6_LPDDR3) += h6_lpddr3.o +obj-$(CONFIG_SUNXI_DRAM_H6_DDR3_1333) += h6_ddr3_1333.o -- cgit