From 6dd34ae4c4cce6a4b9f62c9be55b343a6f0a35f8 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 27 Oct 2016 23:47:07 +0900 Subject: ARM: uniphier: rework existing DDR PHY code to reuse for LD11 SoC The DDR PHY register view of LD11 is slightly different from that of LD4/Pro4/sLD8, but it will be possible to share the register macros (and I want to re-use as much code as possible). Change the code in the more flexible form. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/dram/ddrphy-init.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 arch/arm/mach-uniphier/dram/ddrphy-init.h (limited to 'arch/arm/mach-uniphier/dram/ddrphy-init.h') diff --git a/arch/arm/mach-uniphier/dram/ddrphy-init.h b/arch/arm/mach-uniphier/dram/ddrphy-init.h new file mode 100644 index 0000000000..3fc610baea --- /dev/null +++ b/arch/arm/mach-uniphier/dram/ddrphy-init.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_DDRPHY_INIT_H +#define ARCH_DDRPHY_INTT_H + +#include +#include + +/* for LD4, Pro4, sLD8 */ +#define NR_DATX8_PER_DDRPHY 2 + +int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus); +void ddrphy_prepare_training(void __iomem *phy_base, int rank); +int ddrphy_training(void __iomem *phy_base); + +#endif /* ARCH_DDRPHY_INT_H */ -- cgit