From b04ed73a50fc03c7887f0b1887e11101e3b50a49 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 16 Dec 2015 10:42:29 +0900 Subject: ARM: uniphier: rename DTCR_RNKEN_* register bit to DTCR_RANKEN_* The bit 27-24 of the DTCR register is described as RANKEN in the DDR PHY databook. Follow this abbreviation. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/include/mach/ddrphy-regs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-uniphier/include') diff --git a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h index adcc972877..0c3b508821 100644 --- a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h +++ b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h @@ -147,8 +147,8 @@ struct ddrphy { #define DTCR_DTRANK_SHIFT 4 /* Data Training Rank */ #define DTCR_DTRANK_MASK (0x3 << (DTCR_DTRANK_SHIFT)) #define DTCR_DTMPR (1 << 6) /* Data Training using MPR */ -#define DTCR_RNKEN_SHIFT 24 /* Rank Enable */ -#define DTCR_RNKEN_MASK (0xf << (DTCR_RNKEN_SHIFT)) +#define DTCR_RANKEN_SHIFT 24 /* Rank Enable */ +#define DTCR_RANKEN_MASK (0xf << (DTCR_RANKEN_SHIFT)) #define DXGCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */ #define DXGCR_WLRKEN_MASK (0xf << (DXGCR_WLRKEN_SHIFT)) -- cgit