From ec48b6c991f400c8583ac2f875d65a8539f0b437 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 22 Aug 2018 14:55:27 +0200 Subject: arm64: versal: Add support for new Xilinx Versal ACAPs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex™-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. The patch is adding necessary infrastructure in place without enabling platform which is done in separate patch. Signed-off-by: Michal Simek --- arch/arm/mach-versal/include/mach/sys_proto.h | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 arch/arm/mach-versal/include/mach/sys_proto.h (limited to 'arch/arm/mach-versal/include/mach/sys_proto.h') diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h new file mode 100644 index 0000000000..677facba5e --- /dev/null +++ b/arch/arm/mach-versal/include/mach/sys_proto.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 - 2018 Xilinx, Inc. + */ + +/* Empty file - for compilation */ -- cgit