From ac76dd0836468445e1ba4d756617d677ed58f59b Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Thu, 19 Dec 2019 18:59:28 +0800 Subject: Add global variable sdhc_per_clk for arm/powerpc The QorIQ eSDHC controller supports two reference clocks. They are platform clock and periperhal clock. The global variable sdhc_clk has already been used for platform clock. This patch is to add another global variable sdhc_per_clk for periperhal clock, which provides higher frequency and is required to be used for SD UHS and eMMC HS200/HS400 speed modes. Signed-off-by: Yangbo Lu --- arch/arm/include/asm/global_data.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 17740147ea..f23b6bfb75 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -13,6 +13,10 @@ struct arch_global_data { u32 sdhc_clk; #endif +#if defined(CONFIG_FSL_ESDHC) + u32 sdhc_per_clk; +#endif + #if defined(CONFIG_U_QE) u32 qe_clk; u32 brg_clk; -- cgit From f1bce084264f52caca80ca56815d6c4b4c5d5935 Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Thu, 19 Dec 2019 18:59:30 +0800 Subject: Drop CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK usage The eSDHC reference clocks should be provided by speed.c in arch/. And we do not need CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK option to select which clock to use. Because we can make the driver to select the periperhal clock which is better (provides higher frequency) automatically if its value is provided by speed.c. This patch is to drop this option and make driver to select clock automatically. Also fix peripheral clock calculation issue in fsl_lsch2_speed.c/fsl_lsch3_speed.c. Signed-off-by: Yangbo Lu --- .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 29 ++++++++-------------- .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 22 ++++++++-------- 2 files changed, 20 insertions(+), 31 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 25e9a495f7..fec231857b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -125,7 +125,6 @@ void get_sys_info(struct sys_info *sys_info) } #endif -#ifdef CONFIG_FSL_ESDHC #define HWA_CGA_M2_CLK_SEL 0x00000007 #define HWA_CGA_M2_CLK_SHIFT 0 #if defined(CONFIG_TARGET_LS1046ARDB) || defined(CONFIG_TARGET_LS1043ARDB) @@ -148,11 +147,10 @@ void get_sys_info(struct sys_info *sys_info) break; #endif default: - printf("Error: Unknown peripheral clock select!\n"); + printf("Error: Unknown cluster group A mux 2 clock select!\n"); break; } #endif -#endif #if defined(CONFIG_FSL_IFC) sys_info->freq_localbus = sys_info->freq_systembus / @@ -179,28 +177,21 @@ unsigned long get_qman_freq(void) int get_clocks(void) { struct sys_info sys_info; - +#ifdef CONFIG_FSL_ESDHC + u32 clock = 0; +#endif get_sys_info(&sys_info); gd->cpu_clk = sys_info.freq_processor[0]; gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV; gd->mem_clk = sys_info.freq_ddrbus; - #ifdef CONFIG_FSL_ESDHC -#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK) -#if defined(CONFIG_TARGET_LS1046ARDB) - gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2; -#endif -#if defined(CONFIG_TARGET_LS1043ARDB) - gd->arch.sdhc_clk = sys_info.freq_cga_m2; -#endif -#if defined(CONFIG_TARGET_LS1012ARDB) - gd->arch.sdhc_clk = sys_info.freq_systembus; -#endif -#else - gd->arch.sdhc_clk = (sys_info.freq_systembus / - CONFIG_SYS_FSL_PCLK_DIV) / - CONFIG_SYS_FSL_SDHC_CLK_DIV; +#if defined(CONFIG_ARCH_LS1012A) + clock = sys_info.freq_systembus; +#elif defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) + clock = sys_info.freq_cga_m2; #endif + gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV; + gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV; #endif if (gd->cpu_clk != 0) return 0; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index 4b047a39c0..bd8b9cbdad 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -160,14 +160,14 @@ void get_sys_info(struct sys_info *sys_info) break; } #endif -#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A) - sys_info->freq_cga_m2 = sys_info->freq_systembus; -#endif } int get_clocks(void) { struct sys_info sys_info; +#ifdef CONFIG_FSL_ESDHC + u32 clock = 0; +#endif get_sys_info(&sys_info); gd->cpu_clk = sys_info.freq_processor[0]; gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV; @@ -175,18 +175,16 @@ int get_clocks(void) #ifdef CONFIG_SYS_FSL_HAS_DP_DDR gd->arch.mem2_clk = sys_info.freq_ddrbus2; #endif -#if defined(CONFIG_FSL_ESDHC) -#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK) -#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A) - gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2; -#endif -#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) - gd->arch.sdhc_clk = sys_info.freq_cga_m2; + +#ifdef CONFIG_FSL_ESDHC +#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A) + clock = sys_info.freq_cga_m2; +#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A) + clock = sys_info.freq_systembus; #endif -#else + gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV; gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV; #endif -#endif /* defined(CONFIG_FSL_ESDHC) */ if (gd->cpu_clk != 0) return 0; -- cgit From 8302d1708aef720d52942ea47bcebf9c1b8d5de0 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Mon, 6 Jan 2020 15:22:35 +0100 Subject: aes: add support of aes192 and aes256 Until now, we only support aes128. This commit add the support of aes192 and aes256. Signed-off-by: Philippe Reynes Reviewed-by: Simon Glass --- arch/arm/mach-tegra/tegra20/crypto.c | 41 +++++++++++++++++++----------------- 1 file changed, 22 insertions(+), 19 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-tegra/tegra20/crypto.c b/arch/arm/mach-tegra/tegra20/crypto.c index 66fbc3b458..b91191eba3 100644 --- a/arch/arm/mach-tegra/tegra20/crypto.c +++ b/arch/arm/mach-tegra/tegra20/crypto.c @@ -39,34 +39,35 @@ static void left_shift_vector(u8 *in, u8 *out, int size) /** * Sign a block of data, putting the result into dst. * - * \param key Input AES key, length AES_KEY_LENGTH + * \param key Input AES key, length AES128_KEY_LENGTH * \param key_schedule Expanded key to use * \param src Source data of length 'num_aes_blocks' blocks - * \param dst Destination buffer, length AES_KEY_LENGTH + * \param dst Destination buffer, length AES128_KEY_LENGTH * \param num_aes_blocks Number of AES blocks to encrypt */ static void sign_object(u8 *key, u8 *key_schedule, u8 *src, u8 *dst, u32 num_aes_blocks) { - u8 tmp_data[AES_KEY_LENGTH]; - u8 iv[AES_KEY_LENGTH] = {0}; - u8 left[AES_KEY_LENGTH]; - u8 k1[AES_KEY_LENGTH]; + u8 tmp_data[AES128_KEY_LENGTH]; + u8 iv[AES128_KEY_LENGTH] = {0}; + u8 left[AES128_KEY_LENGTH]; + u8 k1[AES128_KEY_LENGTH]; u8 *cbc_chain_data; unsigned i; cbc_chain_data = zero_key; /* Convenient array of 0's for IV */ /* compute K1 constant needed by AES-CMAC calculation */ - for (i = 0; i < AES_KEY_LENGTH; i++) + for (i = 0; i < AES128_KEY_LENGTH; i++) tmp_data[i] = 0; - aes_cbc_encrypt_blocks(key_schedule, iv, tmp_data, left, 1); + aes_cbc_encrypt_blocks(AES128_KEY_LENGTH, key_schedule, iv, + tmp_data, left, 1); left_shift_vector(left, k1, sizeof(left)); if ((left[0] >> 7) != 0) /* get MSB of L */ - k1[AES_KEY_LENGTH-1] ^= AES_CMAC_CONST_RB; + k1[AES128_KEY_LENGTH - 1] ^= AES_CMAC_CONST_RB; /* compute the AES-CMAC value */ for (i = 0; i < num_aes_blocks; i++) { @@ -78,31 +79,32 @@ static void sign_object(u8 *key, u8 *key_schedule, u8 *src, u8 *dst, aes_apply_cbc_chain_data(tmp_data, k1, tmp_data); /* encrypt the AES block */ - aes_encrypt(tmp_data, key_schedule, dst); + aes_encrypt(AES128_KEY_LENGTH, tmp_data, + key_schedule, dst); debug("sign_obj: block %d of %d\n", i, num_aes_blocks); /* Update pointers for next loop. */ cbc_chain_data = dst; - src += AES_KEY_LENGTH; + src += AES128_KEY_LENGTH; } } /** * Encrypt and sign a block of data (depending on security mode). * - * \param key Input AES key, length AES_KEY_LENGTH + * \param key Input AES key, length AES128_KEY_LENGTH * \param oper Security operations mask to perform (enum security_op) * \param src Source data * \param length Size of source data - * \param sig_dst Destination address for signature, AES_KEY_LENGTH bytes + * \param sig_dst Destination address for signature, AES128_KEY_LENGTH bytes */ static int encrypt_and_sign(u8 *key, enum security_op oper, u8 *src, u32 length, u8 *sig_dst) { u32 num_aes_blocks; - u8 key_schedule[AES_EXPAND_KEY_LENGTH]; - u8 iv[AES_KEY_LENGTH] = {0}; + u8 key_schedule[AES128_EXPAND_KEY_LENGTH]; + u8 iv[AES128_KEY_LENGTH] = {0}; debug("encrypt_and_sign: length = %d\n", length); @@ -110,15 +112,16 @@ static int encrypt_and_sign(u8 *key, enum security_op oper, u8 *src, * The only need for a key is for signing/checksum purposes, so * if not encrypting, expand a key of 0s. */ - aes_expand_key(oper & SECURITY_ENCRYPT ? key : zero_key, key_schedule); + aes_expand_key(oper & SECURITY_ENCRYPT ? key : zero_key, + AES128_KEY_LENGTH, key_schedule); - num_aes_blocks = (length + AES_KEY_LENGTH - 1) / AES_KEY_LENGTH; + num_aes_blocks = (length + AES128_KEY_LENGTH - 1) / AES128_KEY_LENGTH; if (oper & SECURITY_ENCRYPT) { /* Perform this in place, resulting in src being encrypted. */ debug("encrypt_and_sign: begin encryption\n"); - aes_cbc_encrypt_blocks(key_schedule, iv, src, src, - num_aes_blocks); + aes_cbc_encrypt_blocks(AES128_KEY_LENGTH, key_schedule, iv, src, + src, num_aes_blocks); debug("encrypt_and_sign: end encryption\n"); } -- cgit