From 6fb7b756732054dc3972ced06dac2bddc11dfeb9 Mon Sep 17 00:00:00 2001 From: Anton Gerasimov Date: Sat, 24 Mar 2018 18:31:59 +0100 Subject: ARM: dts: zynq: Update dts for Z-turn board Delete devices implemented in PL, stylistic changes. Signed-off-by: Anton Gerasimov Signed-off-by: Michal Simek --- arch/arm/dts/zynq-zturn-myir.dts | 61 ++++++++-------------------------------- 1 file changed, 12 insertions(+), 49 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynq-zturn-myir.dts b/arch/arm/dts/zynq-zturn-myir.dts index a5ecfcc1d7..8aa384b59b 100644 --- a/arch/arm/dts/zynq-zturn-myir.dts +++ b/arch/arm/dts/zynq-zturn-myir.dts @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2015 Andrea Merello * Copyright (C) 2017 Alexander Graf @@ -6,31 +7,23 @@ * Copyright (C) 2011 - 2014 Xilinx * Copyright (C) 2012 National Instruments Corp. * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ + /dts-v1/; /include/ "zynq-7000.dtsi" / { model = "Zynq Z-Turn MYIR Board"; - compatible = "xlnx,zynq-7000"; + compatible = "myir,zynq-zturn", "xlnx,zynq-7000"; aliases { ethernet0 = &gem0; serial0 = &uart1; serial1 = &uart0; - spi0 = &qspi; mmc0 = &sdhci0; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x40000000>; }; @@ -41,52 +34,23 @@ gpio-leds { compatible = "gpio-leds"; - led_r { - label = "led_r"; - gpios = <&gpio0 0x72 0x1>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led_g { - label = "led_g"; - gpios = <&gpio0 0x73 0x1>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - led_b { - label = "led_b"; - gpios = <&gpio0 0x74 0x1>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - }; - - usr_led1 { - label = "usr_led1"; + usr-led1 { + label = "usr-led1"; gpios = <&gpio0 0x0 0x1>; default-state = "off"; - linux,default-trigger = "none"; }; - usr_led2 { - label = "usr_led2"; + usr-led2 { + label = "usr-led2"; gpios = <&gpio0 0x9 0x1>; default-state = "off"; - linux,default-trigger = "none"; }; }; - gpio-beep { - compatible = "gpio-beeper"; - label = "pl-beep"; - gpios = <&gpio0 0x75 0x0>; - }; - gpio-keys { compatible = "gpio-keys"; - #address-cells = <0x1>; - #size-cells = <0x0>; + #address-cells = <1>; + #size-cells = <0>; autorepeat; K1 { label = "K1"; @@ -100,7 +64,6 @@ &clkc { ps-clk-frequency = <33333333>; - fclk-enable = <0xf>; }; &qspi { @@ -152,8 +115,8 @@ reg = <0x49>; }; - adxl345@53 { - compatible = "adi,adxl34x", "adxl34x"; + accelerometer@53 { + compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x"; reg = <0x53>; interrupt-parent = <&intc>; interrupts = <0x0 0x1e 0x4>; -- cgit From 1d4fc9ef1fb1e5030e201e79d743a0eec888dbeb Mon Sep 17 00:00:00 2001 From: Anton Gerasimov Date: Sat, 24 Mar 2018 18:32:00 +0100 Subject: ARM: dts: zynq: Rename dts for Z-turn board Makes naming in line with other Zynq boards. Signed-off-by: Anton Gerasimov Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 2 +- arch/arm/dts/zynq-zturn-myir.dts | 124 --------------------------------------- arch/arm/dts/zynq-zturn.dts | 124 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 125 insertions(+), 125 deletions(-) delete mode 100644 arch/arm/dts/zynq-zturn-myir.dts create mode 100644 arch/arm/dts/zynq-zturn.dts (limited to 'arch/arm') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3f10762b7d..207fbda307 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -143,7 +143,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zc770-xm012.dtb \ zynq-zc770-xm013.dtb \ zynq-zed.dtb \ - zynq-zturn-myir.dtb \ + zynq-zturn.dtb \ zynq-zybo.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-mini-emmc.dtb \ diff --git a/arch/arm/dts/zynq-zturn-myir.dts b/arch/arm/dts/zynq-zturn-myir.dts deleted file mode 100644 index 8aa384b59b..0000000000 --- a/arch/arm/dts/zynq-zturn-myir.dts +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2015 Andrea Merello - * Copyright (C) 2017 Alexander Graf - * - * Based on zynq-zed.dts which is: - * Copyright (C) 2011 - 2014 Xilinx - * Copyright (C) 2012 National Instruments Corp. - * - */ - -/dts-v1/; -/include/ "zynq-7000.dtsi" - -/ { - model = "Zynq Z-Turn MYIR Board"; - compatible = "myir,zynq-zturn", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - serial0 = &uart1; - serial1 = &uart0; - mmc0 = &sdhci0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-leds { - compatible = "gpio-leds"; - usr-led1 { - label = "usr-led1"; - gpios = <&gpio0 0x0 0x1>; - default-state = "off"; - }; - - usr-led2 { - label = "usr-led2"; - gpios = <&gpio0 0x9 0x1>; - default-state = "off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - K1 { - label = "K1"; - gpios = <&gpio0 0x32 0x1>; - linux,code = <0x66>; - gpio-key,wakeup; - autorepeat; - }; - }; -}; - -&clkc { - ps-clk-frequency = <33333333>; -}; - -&qspi { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - - ethernet_phy: ethernet-phy@0 { - reg = <0x0>; - }; -}; - -&sdhci0 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&uart0 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&uart1 { - u-boot,dm-pre-reloc; - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&can0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - stlm75@49 { - status = "okay"; - compatible = "lm75"; - reg = <0x49>; - }; - - accelerometer@53 { - compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x"; - reg = <0x53>; - interrupt-parent = <&intc>; - interrupts = <0x0 0x1e 0x4>; - }; -}; diff --git a/arch/arm/dts/zynq-zturn.dts b/arch/arm/dts/zynq-zturn.dts new file mode 100644 index 0000000000..8aa384b59b --- /dev/null +++ b/arch/arm/dts/zynq-zturn.dts @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2015 Andrea Merello + * Copyright (C) 2017 Alexander Graf + * + * Based on zynq-zed.dts which is: + * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2012 National Instruments Corp. + * + */ + +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + model = "Zynq Z-Turn MYIR Board"; + compatible = "myir,zynq-zturn", "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + serial1 = &uart0; + mmc0 = &sdhci0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + usr-led1 { + label = "usr-led1"; + gpios = <&gpio0 0x0 0x1>; + default-state = "off"; + }; + + usr-led2 { + label = "usr-led2"; + gpios = <&gpio0 0x9 0x1>; + default-state = "off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + K1 { + label = "K1"; + gpios = <&gpio0 0x32 0x1>; + linux,code = <0x66>; + gpio-key,wakeup; + autorepeat; + }; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&qspi { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0x0>; + }; +}; + +&sdhci0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&uart1 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&can0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + stlm75@49 { + status = "okay"; + compatible = "lm75"; + reg = <0x49>; + }; + + accelerometer@53 { + compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x"; + reg = <0x53>; + interrupt-parent = <&intc>; + interrupts = <0x0 0x1e 0x4>; + }; +}; -- cgit From 7ad6d9a4ad8a9cbe116647b7613aaec7c263fcf5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 23 Feb 2018 13:39:37 +0100 Subject: arm: zynq: Handle ENXIO error return value properly zynq_clk_get_rate() is also returning ENXIO which is not handled now. Signed-off-by: Michal Simek --- arch/arm/mach-zynq/clk.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-zynq/clk.c b/arch/arm/mach-zynq/clk.c index 1369cd095b..3c27038630 100644 --- a/arch/arm/mach-zynq/clk.c +++ b/arch/arm/mach-zynq/clk.c @@ -94,7 +94,8 @@ int soc_clk_dump(void) clk_free(&clk); - if (rate == (unsigned long)-ENOSYS) + if ((rate == (unsigned long)-ENOSYS) || + (rate == (unsigned long)-ENXIO)) printf("%10s%20s\n", name, "unknown"); else printf("%10s%20lu\n", name, rate); -- cgit From 680e9976c92714a88611cacc8df9ce136d9d6b16 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 17 Jan 2018 16:32:33 +0100 Subject: arm64: zynqmp: Sync alignment with mainline Sync pcie and lpd_dma nodes with mainline version. Incorrect locations are causing diff in statistics that's why synchronizations are needed. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp.dtsi | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 5bdab61164..e71399f83d 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -547,10 +547,10 @@ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; + clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x868>; @@ -560,10 +560,10 @@ lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; + clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x869>; @@ -573,10 +573,10 @@ lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; + clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86a>; @@ -586,10 +586,10 @@ lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; + clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86b>; @@ -599,10 +599,10 @@ lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; + clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86c>; @@ -612,10 +612,10 @@ lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; + clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86d>; @@ -625,10 +625,10 @@ lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; + clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86e>; @@ -638,10 +638,10 @@ lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; + clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86f>; @@ -781,7 +781,8 @@ <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ - interrupt-names = "misc","dummy","intx", "msi1", "msi0"; + interrupt-names = "misc", "dummy", "intx", + "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, -- cgit From a16e57863960fe5a7d847aa3735fc6295f65d644 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 27 Mar 2018 10:52:40 +0200 Subject: arm64: zynqmp: Use maxim prefix for all maxim chips Use vendor prefix for Maxim chips. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu102-revA.dts | 28 ++++++++++++++-------------- arch/arm/dts/zynqmp-zcu102-revB.dts | 2 +- 2 files changed, 15 insertions(+), 15 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 2be6eb0eb5..1c9e4b1bd3 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -333,51 +333,51 @@ reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ - compatible = "max15301"; + compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ - compatible = "max15303"; + compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ - compatible = "max15303"; + compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ - compatible = "max15301"; + compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ - compatible = "max15303"; + compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ - compatible = "max15303"; + compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ - compatible = "max15303"; + compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ - compatible = "max15303"; + compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ - compatible = "max15301"; + compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ - compatible = "max15303"; + compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ - compatible = "max15303"; + compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ - compatible = "max15303"; + compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; @@ -386,11 +386,11 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ - compatible = "max20751"; + compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ - compatible = "max20751"; + compatible = "maxim,max20751"; reg = <0x73>; }; }; diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts index c771a946b2..d0acb29b64 100644 --- a/arch/arm/dts/zynqmp-zcu102-revB.dts +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -34,7 +34,7 @@ i2cswitch@75 { i2c@2 { max15303@1b { /* u8 */ - compatible = "max15303"; + compatible = "maxim,max15303"; reg = <0x1b>; }; /delete-node/ max15303@20; -- cgit From ba7b6dfae110eb2accc3fa3b25379cee9a7f43f0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 27 Mar 2018 10:38:08 +0200 Subject: arm64: zynqmp: Use i2c-mux instead of i2cswitch instead Based on review from mainline i2c-mux is standard name for i2c switches. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu102-revA.dts | 6 +++--- arch/arm/dts/zynqmp-zcu102-revB.dts | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 1c9e4b1bd3..5f4ac22e1d 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -220,7 +220,7 @@ */ }; - i2cswitch@75 { /* u60 */ + i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; @@ -412,7 +412,7 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ - i2cswitch@74 { /* u34 */ + i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -487,7 +487,7 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o /* 5 - 7 unconnected */ }; - i2cswitch@75 { + i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts index d0acb29b64..46517ba0b4 100644 --- a/arch/arm/dts/zynqmp-zcu102-revB.dts +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -31,7 +31,7 @@ /* Fix collision with u61 */ &i2c0 { - i2cswitch@75 { + i2c-mux@75 { i2c@2 { max15303@1b { /* u8 */ compatible = "maxim,max15303"; -- cgit From 18a952ce7f7d1059fb11bd1b479ad663a4abb6db Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 27 Mar 2018 10:36:39 +0200 Subject: arm64: zynqmp: Sync up license with mainline kernel Mainline Linux kernel has adopted SPDX header license in a different format then was used before. This patch is syncing it up. Also update years in License text and remove Nathalie's email because it is no longer valid. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-clk-ccf.dtsi | 3 +-- arch/arm/dts/zynqmp-clk.dtsi | 5 ++--- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 5 ++--- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 5 ++--- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 5 ++--- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 5 ++--- arch/arm/dts/zynqmp-zcu102-rev1.0.dts | 5 ++--- arch/arm/dts/zynqmp-zcu102-revA.dts | 5 ++--- arch/arm/dts/zynqmp-zcu102-revB.dts | 5 ++--- arch/arm/dts/zynqmp.dtsi | 6 +++++- 10 files changed, 22 insertions(+), 27 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 4449d5b93d..b18d8d19c3 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -1,11 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2017, Xilinx, Inc. * * Michal Simek - * - * SPDX-License-Identifier: GPL-2.0+ */ / { diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi index f6e83e1513..45d84a6b7d 100644 --- a/arch/arm/dts/zynqmp-clk.dtsi +++ b/arch/arm/dts/zynqmp-clk.dtsi @@ -1,11 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * - * (C) Copyright 2015, Xilinx, Inc. + * (C) Copyright 2015 - 2018, Xilinx, Inc. * * Michal Simek - * - * SPDX-License-Identifier: GPL-2.0+ */ / { diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 9062ffe919..0ddb43df6d 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -1,11 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * - * (C) Copyright 2015, Xilinx, Inc. + * (C) Copyright 2015 - 2018, Xilinx, Inc. * * Michal Simek - * - * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index bf43bf8748..670cc44755 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -1,11 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * - * (C) Copyright 2015, Xilinx, Inc. + * (C) Copyright 2015 - 2018, Xilinx, Inc. * * Michal Simek - * - * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index 39c82c592f..41012fa61d 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -1,11 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * - * (C) Copyright 2015 - 2016, Xilinx, Inc. + * (C) Copyright 2015 - 2018, Xilinx, Inc. * * Michal Simek - * - * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index c774b866fb..99aa74e54e 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -1,12 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * - * (C) Copyright 2015, Xilinx, Inc. + * (C) Copyright 2015 - 2018, Xilinx, Inc. * * Siva Durga Prasad * Michal Simek - * - * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts index 323a674e3a..3fc3e74991 100644 --- a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts +++ b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts @@ -1,11 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * - * (C) Copyright 2016, Xilinx, Inc. + * (C) Copyright 2016 - 2018, Xilinx, Inc. * * Michal Simek - * - * SPDX-License-Identifier: GPL-2.0+ */ #include "zynqmp-zcu102-revB.dts" diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 5f4ac22e1d..c9cffc125b 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -1,11 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * - * (C) Copyright 2015, Xilinx, Inc. + * (C) Copyright 2015 - 2018, Xilinx, Inc. * * Michal Simek - * - * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts index 46517ba0b4..384d0a2a0c 100644 --- a/arch/arm/dts/zynqmp-zcu102-revB.dts +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -1,11 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * - * (C) Copyright 2016, Xilinx, Inc. + * (C) Copyright 2016 - 2018, Xilinx, Inc. * * Michal Simek - * - * SPDX-License-Identifier: GPL-2.0+ */ #include "zynqmp-zcu102-revA.dts" diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index e71399f83d..ad4bbbf667 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP * @@ -5,7 +6,10 @@ * * Michal Simek * - * SPDX-License-Identifier: GPL-2.0+ + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. */ / { -- cgit From 52af7e3e81b92911906e19294df16c77f17fdab6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 27 Mar 2018 12:01:24 +0200 Subject: arm64: zynqmp: Remove additional comments from dts files Remove additional comments which were removed as the part of upstreaming. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 1 - arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 1 - arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 1 - arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 3 --- arch/arm/dts/zynqmp-zcu102-revA.dts | 29 ++++++++--------------------- arch/arm/dts/zynqmp-zcu102-revB.dts | 2 -- 6 files changed, 8 insertions(+), 29 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 0ddb43df6d..3c2054734c 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -39,7 +39,6 @@ }; }; -/* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { status = "okay"; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index 670cc44755..22a3c1ebec 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -49,7 +49,6 @@ status = "okay"; }; -/* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { status = "okay"; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index 41012fa61d..fb49b4fcb4 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -51,7 +51,6 @@ status = "okay"; }; -/* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { status = "okay"; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index 99aa74e54e..fe737be038 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -37,7 +37,6 @@ }; }; -/* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { status = "okay"; }; @@ -83,12 +82,10 @@ status = "okay"; }; -/* FIXME: Add device */ &i2c0 { status = "okay"; }; -/* FIXME: Add device */ &i2c1 { status = "okay"; }; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index c9cffc125b..efa94a1419 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -77,7 +77,6 @@ status = "okay"; }; -/* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { status = "okay"; }; @@ -381,23 +380,17 @@ reg = <0x20>; }; -/* drivers/hwmon/pmbus/Kconfig:86: be called max20751. -drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o -*/ - max20751@72 { /* u95 FIXME - not detected */ + max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; - max20751@73 { /* u96 FIXME - not detected */ + max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; - - /* FIXME PMOD - j160 */ - /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { @@ -409,8 +402,7 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; - /* FIXME PL i2c via PCA9306 - u45 */ - /* FIXME MSP430 - u41 - not detected */ + /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; @@ -515,24 +507,19 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ - dev@19 { /* u-boot detection */ - compatible = "xxx"; + dev@19 { reg = <0x19>; }; - dev@30 { /* u-boot detection */ - compatible = "xxx"; + dev@30 { reg = <0x30>; }; - dev@35 { /* u-boot detection */ - compatible = "xxx"; + dev@35 { reg = <0x35>; }; - dev@36 { /* u-boot detection */ - compatible = "xxx"; + dev@36 { reg = <0x36>; }; - dev@51 { /* u-boot detection - maybe SPD */ - compatible = "xxx"; + dev@51 { reg = <0x51>; }; }; diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts index 384d0a2a0c..af4d86882a 100644 --- a/arch/arm/dts/zynqmp-zcu102-revB.dts +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -26,8 +26,6 @@ /delete-node/ phy@21; }; -/* Different qspi 512Mbit version */ - /* Fix collision with u61 */ &i2c0 { i2c-mux@75 { -- cgit From 9d928f0418b55a6796f737e5b166634e493a3413 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 27 Mar 2018 12:13:13 +0200 Subject: arm64: zynqmp: Use keycode from input/input.h Instead of hardcoding numbers. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu102-revA.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index efa94a1419..c04e37dc65 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -11,6 +11,7 @@ #include "zynqmp.dtsi" #include "zynqmp-clk-ccf.dtsi" +#include #include #include #include @@ -51,7 +52,7 @@ sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; - linux,code = <108>; /* down */ + linux,code = ; gpio-key,wakeup; autorepeat; }; -- cgit From d13d97bb95d8fa92be8e9d22ad7693b08d50f37b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 27 Mar 2018 12:50:04 +0200 Subject: arm64: zynqmp: Use s/_/-/g in node name for zcu102 rev1.0 Follow spec for node names. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu102-rev1.0.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts index 3fc3e74991..b1a95a91d1 100644 --- a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts +++ b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts @@ -18,19 +18,19 @@ #address-cells = <1>; #size-cells = <1>; - board_sn: board_sn@0 { + board_sn: board-sn@0 { reg = <0x0 0x14>; }; - eth_mac: eth_mac@20 { + eth_mac: eth-mac@20 { reg = <0x20 0x6>; }; - board_name: board_name@d0 { + board_name: board-name@d0 { reg = <0xd0 0x6>; }; - board_revision: board_revision@e0 { + board_revision: board-revision@e0 { reg = <0xe0 0x3>; }; }; -- cgit From ba9da60c4be9c9718304db7834ed08a8609f41e8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 27 Mar 2018 13:09:15 +0200 Subject: arm64: zynqmp: Fix spi flash partition definition for zc1751 dc2 Using different node name and label partitions as data. Also use latest compatible strings based on mainline review. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index 22a3c1ebec..afa90a8a5b 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -178,15 +178,15 @@ &spi0 { status = "okay"; num-cs = <1>; - spi0_flash0: spi0_flash0@0 { - compatible = "m25p80"; + spi0_flash0: flash@0 { #address-cells = <1>; #size-cells = <1>; + compatible = "sst,sst25wf080", "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; - spi0_flash0@0 { - label = "spi0_flash0"; + partition@0 { + label = "data"; reg = <0x0 0x100000>; }; }; @@ -195,15 +195,15 @@ &spi1 { status = "okay"; num-cs = <1>; - spi1_flash0: spi1_flash0@0 { - compatible = "mtd_dataflash"; + spi1_flash0: flash@0 { #address-cells = <1>; #size-cells = <1>; + compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; spi-max-frequency = <20000000>; reg = <0>; - spi1_flash0@0 { - label = "spi1_flash0"; + partition@0 { + label = "data"; reg = <0x0 0x84000>; }; }; -- cgit From 098505f50028dc2e2de63a519d87036486977190 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 27 Mar 2018 10:54:25 +0200 Subject: arm64: zynqmp: Use atmel prefix instead of at This changes was done in mainline and this patch is just following it. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 2 +- arch/arm/dts/zynqmp-zcu102-revA.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 3c2054734c..7968aa7bec 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -92,7 +92,7 @@ status = "okay"; clock-frequency = <400000>; eeprom@55 { - compatible = "at,24c64"; /* 24AA64 */ + compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; }; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index c04e37dc65..60d3f71031 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -422,7 +422,7 @@ * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ - compatible = "at,24c08"; + compatible = "atmel,24c08"; reg = <0x54>; }; }; -- cgit From 43bf439472f0f47988ca642b293d2b7efe636f17 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 27 Mar 2018 13:15:17 +0200 Subject: arm64: zynqmp: Add eeprom reference to eeprom nodes eeprom can contain information which can be used by nvmem drivers. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 7968aa7bec..c794c91de1 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -91,7 +91,8 @@ &i2c1 { status = "okay"; clock-frequency = <400000>; - eeprom@55 { + + eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; -- cgit From 470f09c9129bbe38f366f77f3868938c174c5bf0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 27 Mar 2018 16:10:25 +0200 Subject: arm64: zynqmp: Enable ttcs for zc1751 dc5 Enable TTCs for this target as is done in Linux kernel. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index fe737be038..16a14eacd8 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -94,6 +94,22 @@ status = "okay"; }; +&ttc0 { + status = "okay"; +}; + +&ttc1 { + status = "okay"; +}; + +&ttc2 { + status = "okay"; +}; + +&ttc3 { + status = "okay"; +}; + &uart0 { status = "okay"; }; -- cgit From 1077dc2889accae69b4aef149abfab2c7f9a3ca2 Mon Sep 17 00:00:00 2001 From: Srinivas Goud Date: Tue, 22 Aug 2017 14:38:46 +0530 Subject: arm64: zynqmp: Update sd properties for dc5 This patch adds no-1-8-v below properties to sd node for dc5 board dts. Signed-off-by: Srinivas Goud Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index 16a14eacd8..0632b18ccf 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -92,6 +92,7 @@ &sdhci0 { status = "okay"; + no-1-8-v; }; &ttc0 { -- cgit From 95f7d6419d5effdd4379b6c5f0b1b831aedcc4a4 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 27 Mar 2018 10:47:26 +0200 Subject: arm64: zynqmp: Remove u-boot commands from dts files U-Boot commands shouldn't be the part of kernel DTS files. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu102-revA.dts | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 60d3f71031..9f2b46cf76 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -144,12 +144,6 @@ sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { - /* - * Enable all GTs to out from U-Boot - * i2c mw 20 6 0 - setup IO to output - * i2c mw 20 2 ef - setup output values on pins 0-7 - * i2c mw 20 3 ff - setup output values on pins 10-17 - */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; @@ -193,7 +187,7 @@ }; }; - tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ + tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; @@ -224,7 +218,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; - i2c@0 { /* i2c mw 75 0 1 */ + i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; @@ -280,7 +274,7 @@ shunt-resistor = <5000>; }; }; - i2c@1 { /* i2c mw 75 0 1 */ + i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; @@ -326,7 +320,7 @@ shunt-resistor = <5000>; }; }; - i2c@2 { /* i2c mw 75 0 1 */ + i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; @@ -409,7 +403,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; - i2c@0 { /* i2c mw 74 0 1 */ + i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; @@ -426,7 +420,7 @@ reg = <0x54>; }; }; - i2c@1 { /* i2c mw 74 0 2 */ + i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; @@ -436,7 +430,7 @@ }; }; - i2c@2 { /* i2c mw 74 0 4 */ + i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; @@ -449,7 +443,7 @@ clock-frequency = <300000000>; }; }; - i2c@3 { /* i2c mw 74 0 8 */ + i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; @@ -462,7 +456,7 @@ clock-frequency = <148500000>; }; }; - i2c@4 { /* i2c mw 74 0 10 */ + i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; @@ -503,7 +497,7 @@ reg = <2>; /* SYSMON */ }; - i2c@3 { /* i2c mw 75 0 8 */ + i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; -- cgit From 147ae1f210f63aacb59a063797e26d0780f13a85 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 27 Mar 2018 10:39:53 +0200 Subject: arm64: zynqmp: Remove number from clock-generator node name There shouldn't be a number appended based on spec. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu102-revA.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 9f2b46cf76..93f1d85d05 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -424,7 +424,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <1>; - si5341: clock-generator1@36 { /* SI5341 - u69 */ + si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; @@ -434,7 +434,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; - si570_1: clock-generator2@5d { /* USER SI570 - u42 */ + si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; @@ -447,7 +447,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <3>; - si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ + si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; @@ -460,7 +460,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - si5328: clock-generator4@69 {/* SI5328 - u20 */ + si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* -- cgit From bbe5c7252d12efc3e4fc49de6fb705c48c3f6bf8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 27 Mar 2018 12:48:30 +0200 Subject: arm64: zynqmp: Add silabs prefix to u69 for zcu102 Add vendor prefix to si5341. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu102-revA.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 93f1d85d05..059d1ffe86 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -425,7 +425,7 @@ #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ - compatible = "si5341"; + compatible = "silabs,si5341"; reg = <0x36>; }; -- cgit From 5208a3a46a5efd43e944b3fd8e46074cfb85f883 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 27 Mar 2018 16:21:42 +0200 Subject: arm64: zynqmp: Remove double spaces from dts file There is no reason to have double spaces for indentation. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zcu102-rev1.0.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts index b1a95a91d1..6647e97edb 100644 --- a/arch/arm/dts/zynqmp-zcu102-rev1.0.dts +++ b/arch/arm/dts/zynqmp-zcu102-rev1.0.dts @@ -14,7 +14,7 @@ compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; }; -&eeprom { +&eeprom { #address-cells = <1>; #size-cells = <1>; -- cgit From 03bc69dec93551b80681fe51b0637fcb4fb6a5f1 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 27 Mar 2018 14:31:42 +0200 Subject: arm: zynq: Remove 0x prefixes from cc108 The patch fixing issues reported by DTC: zynq-cc108.dtb: Warning (unit_address_format): Node /amba/spi@e000d000/flash@0/partition@0x400000 unit name should not have leading "0x" zynq-cc108.dtb: Warning (unit_address_format): Node /amba/spi@e000d000/flash@0/partition@0x800000 unit name should not have leading "0x" zynq-cc108.dtb: Warning (unit_address_format): Node /amba/spi@e000d000/flash@0/partition@0xc00000 unit name should not have leading "0x" zynq-cc108.dtb: Warning (unit_address_format): Node /amba/spi@e000d000/flash@0/partition@0xd00000 unit name should not have leading "0x" zynq-cc108.dtb: Warning (unit_address_format): Node /amba/spi@e000d000/flash@0/partition@0xf00000 unit name should not have leading "0x" Signed-off-by: Michal Simek --- arch/arm/dts/zynq-cc108.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynq-cc108.dts b/arch/arm/dts/zynq-cc108.dts index 4804da5235..b9cc000a33 100644 --- a/arch/arm/dts/zynq-cc108.dts +++ b/arch/arm/dts/zynq-cc108.dts @@ -70,23 +70,23 @@ label = "qspi-fsbl-uboot-bs"; reg = <0x0 0x400000>; /* 4MB */ }; - partition@0x400000 { + partition@400000 { label = "qspi-linux"; reg = <0x400000 0x400000>; /* 4MB */ }; - partition@0x800000 { + partition@800000 { label = "qspi-rootfs"; reg = <0x800000 0x400000>; /* 4MB */ }; - partition@0xc00000 { + partition@c00000 { label = "qspi-devicetree"; reg = <0xc00000 0x100000>; /* 1MB */ }; - partition@0xd00000 { + partition@d00000 { label = "qspi-scratch"; reg = <0xd00000 0x200000>; /* 2MB */ }; - partition@0xf00000 { + partition@f00000 { label = "qspi-uboot-env"; reg = <0xf00000 0x100000>; /* 1MB */ }; -- cgit From 051a8ad7bb9fa05c4b2ae74d9059d4f7157d5fd1 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 27 Mar 2018 13:43:05 +0200 Subject: arm: zynq: Sync up licenses with mainline kernel Use different location for SPDX line. Also update dates for new mainline DTS files. Signed-off-by: Michal Simek --- arch/arm/dts/zynq-cc108.dts | 5 ++--- arch/arm/dts/zynq-zc702.dts | 5 +---- arch/arm/dts/zynq-zc706.dts | 5 +---- arch/arm/dts/zynq-zc770-xm010.dts | 5 ++--- arch/arm/dts/zynq-zc770-xm011.dts | 5 ++--- arch/arm/dts/zynq-zc770-xm012.dts | 5 ++--- arch/arm/dts/zynq-zc770-xm013.dts | 3 +-- arch/arm/dts/zynq-zed.dts | 5 +---- arch/arm/dts/zynq-zybo.dts | 5 +---- 9 files changed, 13 insertions(+), 30 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynq-cc108.dts b/arch/arm/dts/zynq-cc108.dts index b9cc000a33..5f8a0d2555 100644 --- a/arch/arm/dts/zynq-cc108.dts +++ b/arch/arm/dts/zynq-cc108.dts @@ -1,13 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Xilinx CC108 board DTS * - * (C) Copyright 2007-2013 Xilinx, Inc. + * (C) Copyright 2007-2018 Xilinx, Inc. * (C) Copyright 2007-2013 Michal Simek * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd * * Michal SIMEK - * - * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; /include/ "zynq-7000.dtsi" diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index da698a19cc..b95c1608d2 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -1,10 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Xilinx ZC702 board DTS - * * Copyright (C) 2011 - 2015 Xilinx * Copyright (C) 2012 National Instruments Corp. - * - * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; #include "zynq-7000.dtsi" diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index a88a83c166..dbb57445ca 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -1,10 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Xilinx ZC706 board DTS - * * Copyright (C) 2011 - 2015 Xilinx * Copyright (C) 2012 National Instruments Corp. - * - * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; #include "zynq-7000.dtsi" diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index cc5ba98d6b..0c364dfcc1 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -1,9 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Xilinx ZC770 XM010 board DTS * - * Copyright (C) 2013 - 2015 Xilinx, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ + * Copyright (C) 2013-2018 Xilinx, Inc. */ /dts-v1/; #include "zynq-7000.dtsi" diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts index 7f08961491..f711675dd8 100644 --- a/arch/arm/dts/zynq-zc770-xm011.dts +++ b/arch/arm/dts/zynq-zc770-xm011.dts @@ -1,9 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Xilinx ZC770 XM013 board DTS * - * Copyright (C) 2013 Xilinx, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ + * Copyright (C) 2013-2018 Xilinx, Inc. */ /dts-v1/; #include "zynq-7000.dtsi" diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts index 699cd2c0fb..ee6809d51b 100644 --- a/arch/arm/dts/zynq-zc770-xm012.dts +++ b/arch/arm/dts/zynq-zc770-xm012.dts @@ -1,9 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Xilinx ZC770 XM012 board DTS * - * Copyright (C) 2013 - 2015 Xilinx, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ + * Copyright (C) 2013-2018 Xilinx, Inc. */ /dts-v1/; #include "zynq-7000.dtsi" diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index 81a6aa562a..88a7ef0682 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -1,9 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Xilinx ZC770 XM013 board DTS * * Copyright (C) 2013 Xilinx, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; #include "zynq-7000.dtsi" diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index a9ff0e6fa8..24eccf1633 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -1,10 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Xilinx ZED board DTS - * * Copyright (C) 2011 - 2015 Xilinx * Copyright (C) 2012 National Instruments Corp. - * - * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; #include "zynq-7000.dtsi" diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts index 52ec5a4566..3844822305 100644 --- a/arch/arm/dts/zynq-zybo.dts +++ b/arch/arm/dts/zynq-zybo.dts @@ -1,10 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Digilent ZYBO board DTS - * * Copyright (C) 2011 - 2015 Xilinx * Copyright (C) 2012 National Instruments Corp. - * - * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; #include "zynq-7000.dtsi" -- cgit From c78a80ad1301fc1cfa0cf52819ef69f21d45ba2a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 6 Feb 2018 14:00:30 +0100 Subject: arm: zynq: Use i2c-mux instead of i2cswitch for pca9548 i2c muxes should described like this. Signed-off-by: Michal Simek --- arch/arm/dts/zynq-zc702.dts | 2 +- arch/arm/dts/zynq-zc706.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index b95c1608d2..1410c4d7b6 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -111,7 +111,7 @@ scl-gpios = <&gpio0 50 0>; sda-gpios = <&gpio0 51 0>; - i2cswitch@74 { + i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index dbb57445ca..c782064a80 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -62,7 +62,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_default>; - i2cswitch@74 { + i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; -- cgit From a3e10642dab723480992b7232e95c0cfabf0f5d3 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 15 Jun 2017 20:54:12 +0200 Subject: ARM: dts: zynq: Add generic compatible string for I2C EEPROM The at24 driver allows to register I2C EEPROM chips using different vendor and devices, but the I2C subsystem does not take the vendor into account when matching using the I2C table since it only has device entries. But when matching using an OF table, both the vendor and device has to be taken into account so the driver defines only a set of compatible strings using the "atmel" vendor as a generic fallback for compatible I2C devices. So add this generic fallback to the device node compatible string to make the device to match the driver using the OF device ID table. Signed-off-by: Javier Martinez Canillas Signed-off-by: Michal Simek --- arch/arm/dts/zynq-zc702.dts | 2 +- arch/arm/dts/zynq-zc706.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index 1410c4d7b6..bb224662bb 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -151,7 +151,7 @@ #size-cells = <0>; reg = <2>; eeprom@54 { - compatible = "at,24c08"; + compatible = "atmel,24c08"; reg = <0x54>; }; }; diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index c782064a80..f24364b385 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -102,7 +102,7 @@ #size-cells = <0>; reg = <2>; eeprom@54 { - compatible = "at,24c08"; + compatible = "atmel,24c08"; reg = <0x54>; }; }; -- cgit From 99a2e34d770bfcb1373211b2d629457c31a55a60 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 27 Mar 2018 13:48:51 +0200 Subject: arm: zynq: Fix eeprom dt nodes - Use eeprom for node name - Use atmel compatible string instead of at. - Add missing labels Signed-off-by: Michal Simek --- arch/arm/dts/zynq-zc770-xm010.dts | 4 ++-- arch/arm/dts/zynq-zc770-xm011.dts | 4 ++-- arch/arm/dts/zynq-zc770-xm012.dts | 8 ++++---- arch/arm/dts/zynq-zc770-xm013.dts | 2 +- 4 files changed, 9 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index 0c364dfcc1..2c594b7ecc 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -54,8 +54,8 @@ status = "okay"; clock-frequency = <400000>; - m24c02_eeprom@52 { - compatible = "at,24c02"; + eeprom: eeprom@52 { + compatible = "atmel,24c02"; reg = <0x52>; }; diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts index f711675dd8..3fe6eb559e 100644 --- a/arch/arm/dts/zynq-zc770-xm011.dts +++ b/arch/arm/dts/zynq-zc770-xm011.dts @@ -41,8 +41,8 @@ status = "okay"; clock-frequency = <400000>; - m24c02_eeprom@52 { - compatible = "at,24c02"; + eeprom: eeprom@52 { + compatible = "atmel,24c02"; reg = <0x52>; }; }; diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts index ee6809d51b..19d5b275ae 100644 --- a/arch/arm/dts/zynq-zc770-xm012.dts +++ b/arch/arm/dts/zynq-zc770-xm012.dts @@ -37,8 +37,8 @@ status = "okay"; clock-frequency = <400000>; - m24c02_eeprom@52 { - compatible = "at,24c02"; + eeprom0: eeprom@52 { + compatible = "atmel,24c02"; reg = <0x52>; }; }; @@ -47,8 +47,8 @@ status = "okay"; clock-frequency = <400000>; - m24c02_eeprom@52 { - compatible = "at,24c02"; + eeprom1: eeprom@52 { + compatible = "atmel,24c02"; reg = <0x52>; }; }; diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index 88a7ef0682..efd0833eab 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -67,7 +67,7 @@ status = "okay"; num-cs = <4>; is-decoded-cs = <0>; - eeprom: at25@0 { + eeprom: eeprom@0 { at25,byte-len = <8192>; at25,addr-mode = <2>; at25,page-size = <32>; -- cgit From 5510d637863d9f39e2446c7f1d40308e4d5ff8ea Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 27 Mar 2018 13:49:05 +0200 Subject: arm: zynq: Use fixed partitions for spi flash for zc770 xm010 Sync with mainline. Signed-off-by: Michal Simek --- arch/arm/dts/zynq-zc770-xm010.dts | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index 2c594b7ecc..a779672f3a 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -74,14 +74,17 @@ num-cs = <4>; is-decoded-cs = <0>; flash@0 { - compatible = "sst25wf080"; + compatible = "sst25wf080", "jedec,spi-nor"; reg = <1>; spi-max-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <1>; - partition@test { - label = "spi-flash"; - reg = <0x0 0x100000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "data"; + reg = <0x0 0x100000>; + }; }; }; }; -- cgit From 19ed4b697b9732e0a5097bd233fba7e24dfe9146 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 1 Mar 2018 17:44:47 +0530 Subject: fpga: zynqmp: Update zynqmp_load() as per latest xilfpga Latest xilfpga expects to set BIT5 of flags for nonsecure bitsream and also expects length in bytes instead of words This patch does the same. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek Reviewed-by: Joe Hershberger --- arch/arm/include/asm/arch-zynqmp/sys_proto.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index ad3dc9aba5..3daf0e81d8 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -14,6 +14,8 @@ #define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD 0xC200002D #define KEY_PTR_LEN 32 +#define ZYNQMP_FPGA_BIT_NS 5 + enum { IDCODE, VERSION, -- cgit From aedd54739fde8c3524dbed99c9deb38b0675b6fb Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 4 Apr 2018 10:43:04 +0200 Subject: arm64: zynqmp: Remove power domain description This part hasn't been pushed to mainline yet that's why remove it. The patch can be reverted in future when this is pushed there. Reported-by: Alexander Graf Signed-off-by: Michal Simek Reviewed-by: Alexander Graf --- arch/arm/dts/zynqmp.dtsi | 194 ----------------------------------------------- 1 file changed, 194 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index ad4bbbf667..80ac9a6ac7 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -102,155 +102,6 @@ u-boot,dm-pre-reloc; }; - power-domains { - compatible = "xlnx,zynqmp-genpd"; - - pd_usb0: pd-usb0 { - #power-domain-cells = <0x0>; - pd-id = <0x16>; - }; - - pd_usb1: pd-usb1 { - #power-domain-cells = <0x0>; - pd-id = <0x17>; - }; - - pd_sata: pd-sata { - #power-domain-cells = <0x0>; - pd-id = <0x1c>; - }; - - pd_spi0: pd-spi0 { - #power-domain-cells = <0x0>; - pd-id = <0x23>; - }; - - pd_spi1: pd-spi1 { - #power-domain-cells = <0x0>; - pd-id = <0x24>; - }; - - pd_uart0: pd-uart0 { - #power-domain-cells = <0x0>; - pd-id = <0x21>; - }; - - pd_uart1: pd-uart1 { - #power-domain-cells = <0x0>; - pd-id = <0x22>; - }; - - pd_eth0: pd-eth0 { - #power-domain-cells = <0x0>; - pd-id = <0x1d>; - }; - - pd_eth1: pd-eth1 { - #power-domain-cells = <0x0>; - pd-id = <0x1e>; - }; - - pd_eth2: pd-eth2 { - #power-domain-cells = <0x0>; - pd-id = <0x1f>; - }; - - pd_eth3: pd-eth3 { - #power-domain-cells = <0x0>; - pd-id = <0x20>; - }; - - pd_i2c0: pd-i2c0 { - #power-domain-cells = <0x0>; - pd-id = <0x25>; - }; - - pd_i2c1: pd-i2c1 { - #power-domain-cells = <0x0>; - pd-id = <0x26>; - }; - - pd_dp: pd-dp { - #power-domain-cells = <0x0>; - pd-id = <0x29>; - }; - - pd_gdma: pd-gdma { - #power-domain-cells = <0x0>; - pd-id = <0x2a>; - }; - - pd_adma: pd-adma { - #power-domain-cells = <0x0>; - pd-id = <0x2b>; - }; - - pd_ttc0: pd-ttc0 { - #power-domain-cells = <0x0>; - pd-id = <0x18>; - }; - - pd_ttc1: pd-ttc1 { - #power-domain-cells = <0x0>; - pd-id = <0x19>; - }; - - pd_ttc2: pd-ttc2 { - #power-domain-cells = <0x0>; - pd-id = <0x1a>; - }; - - pd_ttc3: pd-ttc3 { - #power-domain-cells = <0x0>; - pd-id = <0x1b>; - }; - - pd_sd0: pd-sd0 { - #power-domain-cells = <0x0>; - pd-id = <0x27>; - }; - - pd_sd1: pd-sd1 { - #power-domain-cells = <0x0>; - pd-id = <0x28>; - }; - - pd_nand: pd-nand { - #power-domain-cells = <0x0>; - pd-id = <0x2c>; - }; - - pd_qspi: pd-qspi { - #power-domain-cells = <0x0>; - pd-id = <0x2d>; - }; - - pd_gpio: pd-gpio { - #power-domain-cells = <0x0>; - pd-id = <0x2e>; - }; - - pd_can0: pd-can0 { - #power-domain-cells = <0x0>; - pd-id = <0x2f>; - }; - - pd_can1: pd-can1 { - #power-domain-cells = <0x0>; - pd-id = <0x30>; - }; - - pd_pcie: pd-pcie { - #power-domain-cells = <0x0>; - pd-id = <0x3b>; - }; - - pd_gpu: pd-gpu { - #power-domain-cells = <0x0>; - pd-id = <0x3a 0x14 0x15>; - }; - }; - pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; @@ -394,7 +245,6 @@ interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; - power-domains = <&pd_can0>; }; can1: can@ff070000 { @@ -406,7 +256,6 @@ interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; - power-domains = <&pd_can1>; }; cci: cci@fd6e0000 { @@ -439,7 +288,6 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; - power-domains = <&pd_gdma>; }; fpd_dma_chan2: dma@fd510000 { @@ -452,7 +300,6 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; - power-domains = <&pd_gdma>; }; fpd_dma_chan3: dma@fd520000 { @@ -465,7 +312,6 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; - power-domains = <&pd_gdma>; }; fpd_dma_chan4: dma@fd530000 { @@ -478,7 +324,6 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; - power-domains = <&pd_gdma>; }; fpd_dma_chan5: dma@fd540000 { @@ -491,7 +336,6 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; - power-domains = <&pd_gdma>; }; fpd_dma_chan6: dma@fd550000 { @@ -504,7 +348,6 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; - power-domains = <&pd_gdma>; }; fpd_dma_chan7: dma@fd560000 { @@ -517,7 +360,6 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; - power-domains = <&pd_gdma>; }; fpd_dma_chan8: dma@fd570000 { @@ -530,7 +372,6 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; - power-domains = <&pd_gdma>; }; gpu: gpu@fd4b0000 { @@ -541,7 +382,6 @@ interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; clock-names = "gpu", "gpu_pp0", "gpu_pp1"; - power-domains = <&pd_gpu>; }; /* LPDDMA default allows only secured access. inorder to enable @@ -558,7 +398,6 @@ xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x868>; - power-domains = <&pd_adma>; }; lpd_dma_chan2: dma@ffa90000 { @@ -571,7 +410,6 @@ xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x869>; - power-domains = <&pd_adma>; }; lpd_dma_chan3: dma@ffaa0000 { @@ -584,7 +422,6 @@ xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86a>; - power-domains = <&pd_adma>; }; lpd_dma_chan4: dma@ffab0000 { @@ -597,7 +434,6 @@ xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86b>; - power-domains = <&pd_adma>; }; lpd_dma_chan5: dma@ffac0000 { @@ -610,7 +446,6 @@ xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86c>; - power-domains = <&pd_adma>; }; lpd_dma_chan6: dma@ffad0000 { @@ -623,7 +458,6 @@ xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86d>; - power-domains = <&pd_adma>; }; lpd_dma_chan7: dma@ffae0000 { @@ -636,7 +470,6 @@ xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86e>; - power-domains = <&pd_adma>; }; lpd_dma_chan8: dma@ffaf0000 { @@ -649,7 +482,6 @@ xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86f>; - power-domains = <&pd_adma>; }; mc: memory-controller@fd070000 { @@ -670,7 +502,6 @@ #size-cells = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x872>; - power-domains = <&pd_nand>; }; gem0: ethernet@ff0b0000 { @@ -684,7 +515,6 @@ #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x874>; - power-domains = <&pd_eth0>; }; gem1: ethernet@ff0c0000 { @@ -698,7 +528,6 @@ #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x875>; - power-domains = <&pd_eth1>; }; gem2: ethernet@ff0d0000 { @@ -712,7 +541,6 @@ #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x876>; - power-domains = <&pd_eth2>; }; gem3: ethernet@ff0e0000 { @@ -726,7 +554,6 @@ #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x877>; - power-domains = <&pd_eth3>; }; gpio: gpio@ff0a0000 { @@ -739,7 +566,6 @@ #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; gpio-controller; - power-domains = <&pd_gpio>; }; i2c0: i2c@ff020000 { @@ -750,7 +576,6 @@ reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; - power-domains = <&pd_i2c0>; }; i2c1: i2c@ff030000 { @@ -761,7 +586,6 @@ reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; - power-domains = <&pd_i2c1>; }; ocm: memory-controller@ff960000 { @@ -800,7 +624,6 @@ <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; - power-domains = <&pd_pcie>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; @@ -822,7 +645,6 @@ #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x873>; - power-domains = <&pd_qspi>; }; rtc: rtc@ffa60000 { @@ -872,7 +694,6 @@ reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; - power-domains = <&pd_sata>; #stream-id-cells = <4>; iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; @@ -890,7 +711,6 @@ xlnx,device_id = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x870>; - power-domains = <&pd_sd0>; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; }; @@ -906,7 +726,6 @@ xlnx,device_id = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x871>; - power-domains = <&pd_sd1>; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; }; @@ -940,7 +759,6 @@ clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; - power-domains = <&pd_spi0>; }; spi1: spi@ff050000 { @@ -952,7 +770,6 @@ clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; - power-domains = <&pd_spi1>; }; ttc0: timer@ff110000 { @@ -962,7 +779,6 @@ interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; - power-domains = <&pd_ttc0>; }; ttc1: timer@ff120000 { @@ -972,7 +788,6 @@ interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; - power-domains = <&pd_ttc1>; }; ttc2: timer@ff130000 { @@ -982,7 +797,6 @@ interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; - power-domains = <&pd_ttc2>; }; ttc3: timer@ff140000 { @@ -992,7 +806,6 @@ interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; - power-domains = <&pd_ttc3>; }; uart0: serial@ff000000 { @@ -1003,7 +816,6 @@ interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; - power-domains = <&pd_uart0>; }; uart1: serial@ff010000 { @@ -1014,7 +826,6 @@ interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; - power-domains = <&pd_uart1>; }; usb0: usb0@ff9d0000 { @@ -1024,7 +835,6 @@ compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; - power-domains = <&pd_usb0>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; @@ -1050,7 +860,6 @@ compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; - power-domains = <&pd_usb1>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; @@ -1111,7 +920,6 @@ interrupts = <0 119 4>; interrupt-parent = <&gic>; clock-names = "aclk", "aud_clk"; - power-domains = <&pd_dp>; xlnx,dp-version = "v1.2"; xlnx,max-lanes = <2>; xlnx,max-link-rate = <540000>; @@ -1134,7 +942,6 @@ xlnx,output-fmt = "rgb"; xlnx,vid-fmt = "yuyv"; xlnx,gfx-fmt = "rgb565"; - power-domains = <&pd_dp>; }; xlnx_dpdma: dma@fd4c0000 { @@ -1144,7 +951,6 @@ interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; - power-domains = <&pd_dp>; dma-channels = <6>; #dma-cells = <1>; dma-video0channel { -- cgit From 704744f81bd478e9b1ef4fae9b14201f17bd8fe3 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 4 Apr 2018 10:46:49 +0200 Subject: arm64: zynqmp: Remove pinctrl settings This part hasn't been pushed to mainline yet that's why remove it. The patch can be reverted in future when this is pushed there. Reported-by: Alexander Graf Signed-off-by: Michal Simek Reviewed-by: Alexander Graf --- arch/arm/dts/zynqmp-zcu102-revA.dts | 288 ------------------------------------ 1 file changed, 288 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 059d1ffe86..b7c638bc9e 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -13,7 +13,6 @@ #include "zynqmp-clk-ccf.dtsi" #include #include -#include #include / { @@ -70,8 +69,6 @@ &can1 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1_default>; }; &dcc { @@ -114,8 +111,6 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; @@ -126,8 +121,6 @@ &gpio { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_default>; }; &gpu { @@ -137,11 +130,6 @@ &i2c0 { status = "okay"; clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c0_default>; - pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; @@ -391,11 +379,6 @@ &i2c1 { status = "okay"; clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1_default>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ @@ -545,269 +528,6 @@ }; }; -&pinctrl0 { - status = "okay"; - pinctrl_i2c0_default: i2c0-default { - mux { - groups = "i2c0_3_grp"; - function = "i2c0"; - }; - - conf { - groups = "i2c0_3_grp"; - bias-pull-up; - slew-rate = ; - io-standard = ; - }; - }; - - pinctrl_i2c0_gpio: i2c0-gpio { - mux { - groups = "gpio0_14_grp", "gpio0_15_grp"; - function = "gpio0"; - }; - - conf { - groups = "gpio0_14_grp", "gpio0_15_grp"; - slew-rate = ; - io-standard = ; - }; - }; - - pinctrl_i2c1_default: i2c1-default { - mux { - groups = "i2c1_4_grp"; - function = "i2c1"; - }; - - conf { - groups = "i2c1_4_grp"; - bias-pull-up; - slew-rate = ; - io-standard = ; - }; - }; - - pinctrl_i2c1_gpio: i2c1-gpio { - mux { - groups = "gpio0_16_grp", "gpio0_17_grp"; - function = "gpio0"; - }; - - conf { - groups = "gpio0_16_grp", "gpio0_17_grp"; - slew-rate = ; - io-standard = ; - }; - }; - - pinctrl_uart0_default: uart0-default { - mux { - groups = "uart0_4_grp"; - function = "uart0"; - }; - - conf { - groups = "uart0_4_grp"; - slew-rate = ; - io-standard = ; - }; - - conf-rx { - pins = "MIO18"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO19"; - bias-disable; - }; - }; - - pinctrl_uart1_default: uart1-default { - mux { - groups = "uart1_5_grp"; - function = "uart1"; - }; - - conf { - groups = "uart1_5_grp"; - slew-rate = ; - io-standard = ; - }; - - conf-rx { - pins = "MIO21"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO20"; - bias-disable; - }; - }; - - pinctrl_usb0_default: usb0-default { - mux { - groups = "usb0_0_grp"; - function = "usb0"; - }; - - conf { - groups = "usb0_0_grp"; - slew-rate = ; - io-standard = ; - }; - - conf-rx { - pins = "MIO52", "MIO53", "MIO55"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", - "MIO60", "MIO61", "MIO62", "MIO63"; - bias-disable; - }; - }; - - pinctrl_gem3_default: gem3-default { - mux { - function = "ethernet3"; - groups = "ethernet3_0_grp"; - }; - - conf { - groups = "ethernet3_0_grp"; - slew-rate = ; - io-standard = ; - }; - - conf-rx { - pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", - "MIO75"; - bias-high-impedance; - low-power-disable; - }; - - conf-tx { - pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", - "MIO69"; - bias-disable; - low-power-enable; - }; - - mux-mdio { - function = "mdio3"; - groups = "mdio3_0_grp"; - }; - - conf-mdio { - groups = "mdio3_0_grp"; - slew-rate = ; - io-standard = ; - bias-disable; - }; - }; - - pinctrl_can1_default: can1-default { - mux { - function = "can1"; - groups = "can1_6_grp"; - }; - - conf { - groups = "can1_6_grp"; - slew-rate = ; - io-standard = ; - }; - - conf-rx { - pins = "MIO25"; - bias-high-impedance; - }; - - conf-tx { - pins = "MIO24"; - bias-disable; - }; - }; - - pinctrl_sdhci1_default: sdhci1-default { - mux { - groups = "sdio1_0_grp"; - function = "sdio1"; - }; - - conf { - groups = "sdio1_0_grp"; - slew-rate = ; - io-standard = ; - bias-disable; - }; - - mux-cd { - groups = "sdio1_0_cd_grp"; - function = "sdio1_cd"; - }; - - conf-cd { - groups = "sdio1_0_cd_grp"; - bias-high-impedance; - bias-pull-up; - slew-rate = ; - io-standard = ; - }; - - mux-wp { - groups = "sdio1_0_wp_grp"; - function = "sdio1_wp"; - }; - - conf-wp { - groups = "sdio1_0_wp_grp"; - bias-high-impedance; - bias-pull-up; - slew-rate = ; - io-standard = ; - }; - }; - - pinctrl_gpio_default: gpio-default { - mux-sw { - function = "gpio0"; - groups = "gpio0_22_grp", "gpio0_23_grp"; - }; - - conf-sw { - groups = "gpio0_22_grp", "gpio0_23_grp"; - slew-rate = ; - io-standard = ; - }; - - mux-msp { - function = "gpio0"; - groups = "gpio0_13_grp", "gpio0_38_grp"; - }; - - conf-msp { - groups = "gpio0_13_grp", "gpio0_38_grp"; - slew-rate = ; - io-standard = ; - }; - - conf-pull-up { - pins = "MIO22", "MIO23"; - bias-pull-up; - }; - - conf-pull-none { - pins = "MIO13", "MIO38"; - bias-disable; - }; - }; -}; - &pcie { status = "okay"; }; @@ -864,8 +584,6 @@ /* SD1 with level shifter */ &sdhci1 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; /* for 1.0 silicon */ xlnx,mio_bank = <1>; }; @@ -876,21 +594,15 @@ &uart0 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { -- cgit From 949ec53c34995b39cd228893c29190f61b4cd680 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 4 Apr 2018 10:41:35 +0200 Subject: arm64: zynqmp: Get 200MHz clock early for MMC SPL MMC boot requires to have clock early. Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-clk.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi index 45d84a6b7d..a8664e8187 100644 --- a/arch/arm/dts/zynqmp-clk.dtsi +++ b/arch/arm/dts/zynqmp-clk.dtsi @@ -25,6 +25,7 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; + u-boot,dm-pre-reloc; }; clk250: clk250 { -- cgit From 6d0340931ec3d833a3c9525014d78424fba644a4 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 28 Mar 2018 14:37:47 +0200 Subject: arm64: zynqmp: Add support for zcu100 aka Ultra96 board Add support for Xilinx zcu100. Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 1 + arch/arm/dts/zynqmp-zcu100-revC.dts | 343 ++++++++++++++++++++++++++++++++++++ 2 files changed, 344 insertions(+) create mode 100644 arch/arm/dts/zynqmp-zcu100-revC.dts (limited to 'arch/arm') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 207fbda307..b4eb0c5894 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -148,6 +148,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-mini-emmc.dtb \ zynqmp-mini-nand.dtb \ + zynqmp-zcu100-revC.dtb \ zynqmp-zcu102-revA.dtb \ zynqmp-zcu102-revB.dtb \ zynqmp-zcu102-rev1.0.dtb \ diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts new file mode 100644 index 0000000000..9114f98140 --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -0,0 +1,343 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZCU100 revC + * + * (C) Copyright 2016 - 2018, Xilinx, Inc. + * + * Michal Simek + * Nathalie Chan King Choy + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" +#include +#include +#include +#include + +/ { + model = "ZynqMP ZCU100 RevC"; + compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; + + aliases { + gpio0 = &gpio; + i2c0 = &i2c1; + rtc0 = &rtc; + serial0 = &uart1; + serial1 = &uart0; + serial2 = &dcc; + spi0 = &spi0; + spi1 = &spi1; + usb0 = &usb0; + usb1 = &usb1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + sw4 { + label = "sw4"; + gpios = <&gpio 23 GPIO_ACTIVE_LOW>; + linux,code = ; + gpio-key,wakeup; + autorepeat; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, + <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, + <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, + <&xilinx_ams 9>, <&xilinx_ams 10>, + <&xilinx_ams 11>, <&xilinx_ams 12>; + }; + + leds { + compatible = "gpio-leds"; + ds2 { + label = "ds2"; + gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + ds3 { + label = "ds3"; + gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; /* WLAN tx */ + default-state = "off"; + }; + + ds4 { + label = "ds4"; + gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0rx"; /* WLAN rx */ + default-state = "off"; + }; + + ds5 { + label = "ds5"; + gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + }; + + vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ + label = "vbus_det"; + gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + ltc2954: ltc2954 { /* U7 */ + compatible = "lltc,ltc2954", "lltc,ltc2952"; + trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */ + /* If there is HW watchdog on mezzanine this signal should be connected there */ + watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */ + kill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */ + }; + + wmmcsdio_fixed: fixedregulator-mmcsdio { + compatible = "regulator-fixed"; + regulator-name = "wmmcsdio_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + sdio_pwrseq: sdio_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ + }; +}; + +&dcc { + status = "okay"; +}; + +&gpio { + status = "okay"; + gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", + "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", + "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", + "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", + "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", + "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", + "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", + "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", + "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", + "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", + "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", + "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", + "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", + "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", + "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", + "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ + "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", ""; +}; + +&gpu { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <100000>; + i2c-mux@75 { /* u11 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2csw_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + label = "LS-I2C0"; + }; + i2csw_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + label = "LS-I2C1"; + }; + i2csw_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + label = "HS-I2C2"; + }; + i2csw_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + label = "HS-I2C3"; + }; + i2csw_4: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + + pmic: pmic@5e { /* Custom TI PMIC u33 */ + compatible = "ti,tps65086"; + reg = <0x5e>; + interrupt-parent = <&gpio>; + interrupts = <77 GPIO_ACTIVE_LOW>; + #gpio-cells = <2>; + gpio-controller; + }; + }; + i2csw_5: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* PS_PMBUS */ + ina226@40 { /* u35 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <10000>; + /* MIO31 is alert which should be routed to PMUFW */ + }; + }; + i2csw_6: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* + * Not Connected + */ + }; + i2csw_7: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* + * usb5744 (DNP) - U5 + * 100kHz - this is default freq for us + */ + }; + }; +}; + +&rtc { + status = "okay"; +}; + +/* SD0 only supports 3.3V, no level shifter */ +&sdhci0 { + status = "okay"; + no-1-8-v; + broken-cd; /* CD has to be enabled by default */ + disable-wp; + xlnx,mio_bank = <0>; +}; + +&sdhci1 { + status = "okay"; + bus-width = <0x4>; + xlnx,mio_bank = <0>; + non-removable; + disable-wp; + cap-power-off-card; + mmc-pwrseq = <&sdio_pwrseq>; + vqmmc-supply = <&wmmcsdio_fixed>; + #address-cells = <1>; + #size-cells = <0>; + wlcore: wifi@2 { + compatible = "ti,wl1831"; + reg = <2>; + interrupt-parent = <&gpio>; + interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ + }; +}; + +&serdes { + status = "okay"; +}; + +&spi0 { /* Low Speed connector */ + status = "okay"; + label = "LS-SPI0"; +}; + +&spi1 { /* High Speed connector */ + status = "okay"; + label = "HS-SPI1"; +}; + +&uart0 { + status = "okay"; + bluetooth { + compatible = "ti,wl1831-st"; + enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; + }; + +}; + +&uart1 { + status = "okay"; + +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "peripheral"; + phy-names = "usb3-phy"; + phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; + maximum-speed = "super-speed"; +}; + +/* ULPI SMSC USB3320 */ +&usb1 { + status = "okay"; +}; + +&dwc3_1 { + status = "okay"; + dr_mode = "host"; + phy-names = "usb3-phy"; + phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; + maximum-speed = "super-speed"; +}; + +&watchdog0 { + status = "okay"; +}; + +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; -- cgit From 10aaa3584bc4381f86253acc136d641c7dce64eb Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 28 Mar 2018 15:00:25 +0200 Subject: arm64: zynqmp: Add support for zc1751 dc3 zc1751 is based board with dc3 extenstion card which is used for silicon validation. Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 1 + arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 210 +++++++++++++++++++++++++++++++ 2 files changed, 211 insertions(+) create mode 100644 arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts (limited to 'arch/arm') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b4eb0c5894..37f6563802 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -154,6 +154,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zcu102-rev1.0.dtb \ zynqmp-zc1751-xm015-dc1.dtb \ zynqmp-zc1751-xm016-dc2.dtb \ + zynqmp-zc1751-xm017-dc3.dtb \ zynqmp-zc1751-xm018-dc4.dtb \ zynqmp-zc1751-xm019-dc5.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \ diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts new file mode 100644 index 0000000000..d6a010355b --- /dev/null +++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP zc1751-xm017-dc3 + * + * (C) Copyright 2016 - 2018, Xilinx, Inc. + * + * Michal Simek + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" + +/ { + model = "ZynqMP zc1751-xm017-dc3 RevA"; + compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem0; + gpio0 = &gpio; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + usb0 = &usb0; + usb1 = &usb1; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + +&gem0 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@0 { /* VSC8211 */ + reg = <0>; + }; +}; + +&gpio { + status = "okay"; +}; + +/* just eeprom here */ +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + tca6416_u26: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + /* IRQ not connected */ + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +/* eeprom24c02 and SE98A temp chip pca9306 */ +&i2c1 { + status = "okay"; + clock-frequency = <400000>; +}; + +/* MT29F64G08AECDBJ4-6 */ +&nand0 { + status = "okay"; + arasan,has-mdma; + num-cs = <2>; + + partition@0 { /* for testing purpose */ + label = "nand-fsbl-uboot"; + reg = <0x0 0x0 0x400000>; + }; + partition@1 { /* for testing purpose */ + label = "nand-linux"; + reg = <0x0 0x400000 0x1400000>; + }; + partition@2 { /* for testing purpose */ + label = "nand-device-tree"; + reg = <0x0 0x1800000 0x400000>; + }; + partition@3 { /* for testing purpose */ + label = "nand-rootfs"; + reg = <0x0 0x1C00000 0x1400000>; + }; + partition@4 { /* for testing purpose */ + label = "nand-bitstream"; + reg = <0x0 0x3000000 0x400000>; + }; + partition@5 { /* for testing purpose */ + label = "nand-misc"; + reg = <0x0 0x3400000 0xFCC00000>; + }; + + partition@6 { /* for testing purpose */ + label = "nand1-fsbl-uboot"; + reg = <0x1 0x0 0x400000>; + }; + partition@7 { /* for testing purpose */ + label = "nand1-linux"; + reg = <0x1 0x400000 0x1400000>; + }; + partition@8 { /* for testing purpose */ + label = "nand1-device-tree"; + reg = <0x1 0x1800000 0x400000>; + }; + partition@9 { /* for testing purpose */ + label = "nand1-rootfs"; + reg = <0x1 0x1C00000 0x1400000>; + }; + partition@10 { /* for testing purpose */ + label = "nand1-bitstream"; + reg = <0x1 0x3000000 0x400000>; + }; + partition@11 { /* for testing purpose */ + label = "nand1-misc"; + reg = <0x1 0x3400000 0xFCC00000>; + }; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; + /* SATA phy OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +}; + +&sdhci1 { /* emmc with some settings */ + status = "okay"; +}; + +/* main */ +&uart0 { + status = "okay"; +}; + +/* DB9 */ +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +/* ULPI SMSC USB3320 */ +&usb1 { + status = "okay"; + dr_mode = "host"; +}; -- cgit From 85231c087eff5968e37966d6cc751f954301c43d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 28 Mar 2018 15:09:32 +0200 Subject: arm64: zynqmp: Add support for zc12xx boards Add support for zc12xx boards. All of them are internal boards for silicon validation and share very similar base platforms. Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 3 ++ arch/arm/dts/zynqmp-zc1232-revA.dts | 87 +++++++++++++++++++++++++++++++++++++ arch/arm/dts/zynqmp-zc1254-revA.dts | 72 ++++++++++++++++++++++++++++++ arch/arm/dts/zynqmp-zc1275-revA.dts | 72 ++++++++++++++++++++++++++++++ 4 files changed, 234 insertions(+) create mode 100644 arch/arm/dts/zynqmp-zc1232-revA.dts create mode 100644 arch/arm/dts/zynqmp-zc1254-revA.dts create mode 100644 arch/arm/dts/zynqmp-zc1275-revA.dts (limited to 'arch/arm') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 37f6563802..fd871617a8 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -152,6 +152,9 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zcu102-revA.dtb \ zynqmp-zcu102-revB.dtb \ zynqmp-zcu102-rev1.0.dtb \ + zynqmp-zc1232-revA.dtb \ + zynqmp-zc1254-revA.dtb \ + zynqmp-zc1275-revA.dtb \ zynqmp-zc1751-xm015-dc1.dtb \ zynqmp-zc1751-xm016-dc2.dtb \ zynqmp-zc1751-xm017-dc3.dtb \ diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts new file mode 100644 index 0000000000..ea1ca561a1 --- /dev/null +++ b/arch/arm/dts/zynqmp-zc1232-revA.dts @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZC1232 + * + * (C) Copyright 2017 - 2018, Xilinx, Inc. + * + * Michal Simek + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include + +/ { + model = "ZynqMP ZC1232 RevA"; + compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; + + aliases { + serial0 = &uart0; + serial1 = &dcc; + spi0 = &qspi; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&dcc { + status = "okay"; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80"; /* 32MB FIXME */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + partition@qspi-fsbl-uboot { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + }; +}; + +&sata { + status = "okay"; + /* SATA OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + phy-names = "sata-phy"; + phys = <&lane0 PHY_TYPE_SATA 0 0 125000000>, <&lane1 PHY_TYPE_SATA 1 1 125000000>; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts new file mode 100644 index 0000000000..2493883e6f --- /dev/null +++ b/arch/arm/dts/zynqmp-zc1254-revA.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZC1254 + * + * (C) Copyright 2015 - 2018, Xilinx, Inc. + * + * Michal Simek + * Siva Durga Prasad Paladugu + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" + +/ { + model = "ZynqMP ZC1254 RevA"; + compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; + + aliases { + serial0 = &uart0; + serial1 = &dcc; + spi0 = &qspi; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&dcc { + status = "okay"; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + partition@qspi-fsbl-uboot { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/zynqmp-zc1275-revA.dts b/arch/arm/dts/zynqmp-zc1275-revA.dts new file mode 100644 index 0000000000..2543a674ca --- /dev/null +++ b/arch/arm/dts/zynqmp-zc1275-revA.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZC1275 + * + * (C) Copyright 2017 - 2018, Xilinx, Inc. + * + * Michal Simek + * Siva Durga Prasad Paladugu + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" + +/ { + model = "ZynqMP ZC1275 RevA"; + compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; + + aliases { + serial0 = &uart0; + serial1 = &dcc; + spi0 = &qspi; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&dcc { + status = "okay"; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + partition@qspi-fsbl-uboot { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; -- cgit From f7c8e491e9a493239471cb4eb77fc940c526bcf3 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 28 Mar 2018 15:36:36 +0200 Subject: arm64: zynqmp: Add support for zcu104 customer board Xilinx zcu104 is another customer board. It is sort of zcu102 clone with some differences. Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 2 + arch/arm/dts/zynqmp-zcu104-revA.dts | 265 +++++++++++++++++++++++++++++++++++ arch/arm/dts/zynqmp-zcu104-revC.dts | 266 ++++++++++++++++++++++++++++++++++++ 3 files changed, 533 insertions(+) create mode 100644 arch/arm/dts/zynqmp-zcu104-revA.dts create mode 100644 arch/arm/dts/zynqmp-zcu104-revC.dts (limited to 'arch/arm') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index fd871617a8..201661cb2c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -152,6 +152,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zcu102-revA.dtb \ zynqmp-zcu102-revB.dtb \ zynqmp-zcu102-rev1.0.dtb \ + zynqmp-zcu104-revA.dtb \ + zynqmp-zcu104-revC.dtb \ zynqmp-zc1232-revA.dtb \ zynqmp-zc1254-revA.dtb \ zynqmp-zc1275-revA.dtb \ diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts new file mode 100644 index 0000000000..a0e13d8dc5 --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -0,0 +1,265 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZCU104 + * + * (C) Copyright 2017 - 2018, Xilinx, Inc. + * + * Michal Simek + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include +#include + +/ { + model = "ZynqMP ZCU104 RevA"; + compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + gpio0 = &gpio; + i2c0 = &i2c1; + mmc0 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &dcc; + spi0 = &qspi; + usb0 = &usb0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&can1 { + status = "okay"; +}; + +&dcc { + status = "okay"; +}; + +&gem3 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@c { + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + }; +}; + +&gpio { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + /* Another connection to this bus via PL i2c via PCA9306 - u45 */ + i2c-mux@74 { /* u34 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* + * IIC_EEPROM 1kB memory which uses 256B blocks + * where every block has different address. + * 0 - 256B address 0x54 + * 256B - 512B address 0x55 + * 512B - 768B address 0x56 + * 768B - 1024B address 0x57 + */ + eeprom: eeprom@54 { /* u23 */ + compatible = "atmel,24c08"; + reg = <0x54>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ + compatible = "idt,8t49n287"; + reg = <0x6c>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ + #clock-cells = <0>; + compatible = "infineon,irps5401"; + reg = <0x43>; + }; + irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ + #clock-cells = <0>; + compatible = "infineon,irps5401"; + reg = <0x4d>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + tca6416_u97: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + /* + * IRQ not connected + * Lines: + * 0 - IRPS5401_ALERT_B + * 1 - HDMI_8T49N241_INT_ALM + * 2 - MAX6643_OT_B + * 3 - MAX6643_FANFAIL_B + * 5 - IIC_MUX_RESET_B + * 6 - GEM3_EXP_RESET_B + * 7 - FMC_LPC_PRSNT_M2C_B + * 4, 10 - 17 - not connected + */ + }; + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + + /* 3, 6 not connected */ + }; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80"; /* n25q512a 128MiB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + partition@qspi-fsbl-uboot { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + }; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; + /* SATA OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + phy-names = "sata-phy"; + phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + no-1-8-v; + xlnx,mio_bank = <1>; + disable-wp; +}; + +&serdes { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + phy-names = "usb3-phy"; + phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; + maximum-speed = "super-speed"; +}; + +&watchdog0 { + status = "okay"; +}; + +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + +&ams_pl { + status = "okay"; +}; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts new file mode 100644 index 0000000000..6e3cf5a97f --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZCU104 + * + * (C) Copyright 2017 - 2018, Xilinx, Inc. + * + * Michal Simek + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include +#include + +/ { + model = "ZynqMP ZCU104 RevC"; + compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + gpio0 = &gpio; + i2c0 = &i2c1; + mmc0 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &dcc; + spi0 = &qspi; + usb0 = &usb0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; + +&can1 { + status = "okay"; +}; + +&dcc { + status = "okay"; +}; + +&gem3 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@c { + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + }; +}; + +&gpio { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + tca6416_u97: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + /* + * IRQ not connected + * Lines: + * 0 - IRPS5401_ALERT_B + * 1 - HDMI_8T49N241_INT_ALM + * 2 - MAX6643_OT_B + * 3 - MAX6643_FANFAIL_B + * 5 - IIC_MUX_RESET_B + * 6 - GEM3_EXP_RESET_B + * 7 - FMC_LPC_PRSNT_M2C_B + * 4, 10 - 17 - not connected + */ + }; + + /* Another connection to this bus via PL i2c via PCA9306 - u45 */ + i2c-mux@74 { /* u34 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* + * IIC_EEPROM 1kB memory which uses 256B blocks + * where every block has different address. + * 0 - 256B address 0x54 + * 256B - 512B address 0x55 + * 512B - 768B address 0x56 + * 768B - 1024B address 0x57 + */ + eeprom: eeprom@54 { /* u23 */ + compatible = "atmel,24c08"; + reg = <0x54>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ + compatible = "idt,8t49n287"; + reg = <0x6c>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ + #clock-cells = <0>; + compatible = "infineon,irps5401"; + reg = <0x43>; + }; + irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ + #clock-cells = <0>; + compatible = "infineon,irps5401"; + reg = <0x4d>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + + /* 3, 6 not connected */ + }; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "m25p80"; /* n25q512a 128MiB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + partition@qspi-fsbl-uboot { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + }; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; + /* SATA OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + phy-names = "sata-phy"; + phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + no-1-8-v; + xlnx,mio_bank = <1>; + disable-wp; +}; + +&serdes { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + phy-names = "usb3-phy"; + phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; + maximum-speed = "super-speed"; +}; + +&watchdog0 { + status = "okay"; +}; + +&xilinx_ams { + status = "okay"; +}; + +&ams_ps { + status = "okay"; +}; + +&ams_pl { + status = "okay"; +}; -- cgit From cf0bcd7d02e9f1774a3a6643ec4739c8c0aef217 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 28 Mar 2018 15:43:51 +0200 Subject: arm64: zynqmp: Add support for Xilinx zcu106-revA Xilinx zcu106 is a customer board. It is reusing some parts from zcu102. Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 1 + arch/arm/dts/zynqmp-zcu106-revA.dts | 596 ++++++++++++++++++++++++++++++++++++ 2 files changed, 597 insertions(+) create mode 100644 arch/arm/dts/zynqmp-zcu106-revA.dts (limited to 'arch/arm') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 201661cb2c..d9e91a29d6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -154,6 +154,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zcu102-rev1.0.dtb \ zynqmp-zcu104-revA.dtb \ zynqmp-zcu104-revC.dtb \ + zynqmp-zcu106-revA.dtb \ zynqmp-zc1232-revA.dtb \ zynqmp-zc1254-revA.dtb \ zynqmp-zc1275-revA.dtb \ diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts new file mode 100644 index 0000000000..bbcd26031d --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -0,0 +1,596 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZCU106 + * + * (C) Copyright 2016, Xilinx, Inc. + * + * Michal Simek + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include +#include +#include + +/ { + model = "ZynqMP ZCU106 RevA"; + compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + gpio0 = &gpio; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &dcc; + spi0 = &qspi; + usb0 = &usb0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + sw19 { + label = "sw19"; + gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; + linux,code = ; + gpio-key,wakeup; + autorepeat; + }; + }; + + leds { + compatible = "gpio-leds"; + heartbeat_led { + label = "heartbeat"; + gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&can1 { + status = "okay"; +}; + +&dcc { + status = "okay"; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + +&gem3 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@c { + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + }; +}; + +&gpio { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + tca6416_u97: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + /* + * IRQ not connected + * Lines: + * 0 - SFP_SI5328_INT_ALM + * 1 - HDMI_SI5328_INT_ALM + * 5 - IIC_MUX_RESET_B + * 6 - GEM3_EXP_RESET_B + * 10 - FMC_HPC0_PRSNT_M2C_B + * 11 - FMC_HPC1_PRSNT_M2C_B + * 2-4, 7, 12-17 - not connected + */ + }; + + tca6416_u61: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + /* + * IRQ not connected + * Lines: + * 0 - VCCPSPLL_EN + * 1 - MGTRAVCC_EN + * 2 - MGTRAVTT_EN + * 3 - VCCPSDDRPLL_EN + * 4 - MIO26_PMU_INPUT_LS + * 5 - PL_PMBUS_ALERT + * 6 - PS_PMBUS_ALERT + * 7 - MAXIM_PMBUS_ALERT + * 10 - PL_DDR4_VTERM_EN + * 11 - PL_DDR4_VPP_2V5_EN + * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON + * 13 - PS_DIMM_SUSPEND_EN + * 14 - PS_DDR4_VTERM_EN + * 15 - PS_DDR4_VPP_2V5_EN + * 16 - 17 - not connected + */ + }; + + i2c-mux@75 { /* u60 */ + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* PS_PMBUS */ + ina226@40 { /* u76 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + ina226@41 { /* u77 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + ina226@42 { /* u78 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + ina226@43 { /* u87 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + ina226@44 { /* u85 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; + }; + ina226@45 { /* u86 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + ina226@46 { /* u93 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <5000>; + }; + ina226@47 { /* u88 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + ina226@4a { /* u15 */ + compatible = "ti,ina226"; + reg = <0x4a>; + shunt-resistor = <5000>; + }; + ina226@4b { /* u92 */ + compatible = "ti,ina226"; + reg = <0x4b>; + shunt-resistor = <5000>; + }; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* PL_PMBUS */ + ina226@40 { /* u79 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <2000>; + }; + ina226@41 { /* u81 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + ina226@42 { /* u80 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + ina226@43 { /* u84 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + ina226@44 { /* u16 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; + }; + ina226@45 { /* u65 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + ina226@46 { /* u74 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <5000>; + }; + ina226@47 { /* u75 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* MAXIM_PMBUS - 00 */ + max15301@a { /* u46 */ + compatible = "maxim,max15301"; + reg = <0xa>; + }; + max15303@b { /* u4 */ + compatible = "maxim,max15303"; + reg = <0xb>; + }; + max15303@10 { /* u13 */ + compatible = "maxim,max15303"; + reg = <0x10>; + }; + max15301@13 { /* u47 */ + compatible = "maxim,max15301"; + reg = <0x13>; + }; + max15303@14 { /* u7 */ + compatible = "maxim,max15303"; + reg = <0x14>; + }; + max15303@15 { /* u6 */ + compatible = "maxim,max15303"; + reg = <0x15>; + }; + max15303@16 { /* u10 */ + compatible = "maxim,max15303"; + reg = <0x16>; + }; + max15303@17 { /* u9 */ + compatible = "maxim,max15303"; + reg = <0x17>; + }; + max15301@18 { /* u63 */ + compatible = "maxim,max15301"; + reg = <0x18>; + }; + max15303@1a { /* u49 */ + compatible = "maxim,max15303"; + reg = <0x1a>; + }; + max15303@1b { /* u8 */ + compatible = "maxim,max15303"; + reg = <0x1b>; + }; + max15303@1d { /* u18 */ + compatible = "maxim,max15303"; + reg = <0x1d>; + }; + + max20751@72 { /* u95 */ + compatible = "maxim,max20751"; + reg = <0x72>; + }; + max20751@73 { /* u96 */ + compatible = "maxim,max20751"; + reg = <0x73>; + }; + }; + /* Bus 3 is not connected */ + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + /* PL i2c via PCA9306 - u45 */ + i2c-mux@74 { /* u34 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* + * IIC_EEPROM 1kB memory which uses 256B blocks + * where every block has different address. + * 0 - 256B address 0x54 + * 256B - 512B address 0x55 + * 512B - 768B address 0x56 + * 768B - 1024B address 0x57 + */ + eeprom: eeprom@54 { /* u23 */ + compatible = "atmel,24c08"; + reg = <0x54>; + }; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + si5341: clock-generator@36 { /* SI5341 - u69 */ + compatible = "si5341"; + reg = <0x36>; + }; + + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + si570_1: clock-generator@5d { /* USER SI570 - u42 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <300000000>; + clock-frequency = <300000000>; + }; + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; /* copy from zc702 */ + factory-fout = <156250000>; + clock-frequency = <148500000>; + }; + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + si5328: clock-generator@69 {/* SI5328 - u20 */ + compatible = "silabs,si5328"; + reg = <0x69>; + }; + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; /* FAN controller */ + temp@4c {/* lm96163 - u128 */ + compatible = "national,lm96163"; + reg = <0x4c>; + }; + }; + /* 6 - 7 unconnected */ + }; + + i2c-mux@75 { + compatible = "nxp,pca9548"; /* u135 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* HPC0_IIC */ + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* HPC1_IIC */ + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* SYSMON */ + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* DDR4 SODIMM */ + dev@19 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x19>; + }; + dev@30 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x30>; + }; + dev@35 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x35>; + }; + dev@36 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x36>; + }; + dev@51 { /* u-boot detection - maybe SPD */ + compatible = "xxx"; + reg = <0x51>; + }; + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* SEP 3 */ + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* SEP 2 */ + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* SEP 1 */ + }; + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* SEP 0 */ + }; + }; +}; + +&qspi { + status = "okay"; + is-dual = <1>; + flash@0 { + compatible = "m25p80"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + partition@qspi-fsbl-uboot { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + }; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; + /* SATA OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + phy-names = "sata-phy"; + phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + no-1-8-v; + xlnx,mio_bank = <1>; +}; + +&serdes { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + phy-names = "usb3-phy"; + phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; +}; + +&watchdog0 { + status = "okay"; +}; -- cgit From f190eaf002bf1434587d57c726b3dabfabbc8074 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 28 Mar 2018 15:55:27 +0200 Subject: arm64: zynqmp: Add support for Xilinx zcu111-revA Xilinx zcu111 is a customer board. It is reusing some parts from zcu102. Signed-off-by: Michal Simek --- arch/arm/dts/Makefile | 1 + arch/arm/dts/zynqmp-zcu111-revA.dts | 525 ++++++++++++++++++++++++++++++++++++ 2 files changed, 526 insertions(+) create mode 100644 arch/arm/dts/zynqmp-zcu111-revA.dts (limited to 'arch/arm') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d9e91a29d6..62fbf32a62 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -155,6 +155,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zcu104-revA.dtb \ zynqmp-zcu104-revC.dtb \ zynqmp-zcu106-revA.dtb \ + zynqmp-zcu111-revA.dtb \ zynqmp-zc1232-revA.dtb \ zynqmp-zc1254-revA.dtb \ zynqmp-zc1275-revA.dtb \ diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts new file mode 100644 index 0000000000..4002d78806 --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -0,0 +1,525 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Xilinx ZynqMP ZCU111 + * + * (C) Copyright 2017 - 2018, Xilinx, Inc. + * + * Michal Simek + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include +#include +#include + +/ { + model = "ZynqMP ZCU111 RevA"; + compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + gpio0 = &gpio; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &dcc; + spi0 = &qspi; + usb0 = &usb0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + /* Another 4GB connected to PL */ + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + sw19 { + label = "sw19"; + gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; + linux,code = ; + gpio-key,wakeup; + autorepeat; + }; + }; + + leds { + compatible = "gpio-leds"; + heartbeat_led { + label = "heartbeat"; + gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&dcc { + status = "okay"; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + +&gem3 { + status = "okay"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@c { + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + }; +}; + +&gpio { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + tca6416_u22: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; /* interrupt not connected */ + #gpio-cells = <2>; + /* + * IRQ not connected + * Lines: + * 0 - MAX6643_OT_B + * 1 - MAX6643_FANFAIL_B + * 2 - MIO26_PMU_INPUT_LS + * 4 - SFP_SI5382_INT_ALM + * 5 - IIC_MUX_RESET_B + * 6 - GEM3_EXP_RESET_B + * 10 - FMCP_HSPC_PRSNT_M2C_B + * 11 - CLK_SPI_MUX_SEL0 + * 12 - CLK_SPI_MUX_SEL1 + * 16 - IRPS5401_ALERT_B + * 17 - INA226_PMBUS_ALERT + * 3, 7, 13-15 - not connected + */ + }; + + i2c-mux@75 { /* u23 */ + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* PS_PMBUS */ + /* PMBUS_ALERT done via pca9544 */ + ina226@40 { /* u67 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <2000>; + }; + ina226@41 { /* u59 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + ina226@42 { /* u61 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + ina226@43 { /* u60 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + ina226@45 { /* u64 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + ina226@46 { /* u69 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <2000>; + }; + ina226@47 { /* u66 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + ina226@48 { /* u65 */ + compatible = "ti,ina226"; + reg = <0x48>; + shunt-resistor = <5000>; + }; + ina226@49 { /* u63 */ + compatible = "ti,ina226"; + reg = <0x49>; + shunt-resistor = <5000>; + }; + ina226@4a { /* u3 */ + compatible = "ti,ina226"; + reg = <0x4a>; + shunt-resistor = <5000>; + }; + ina226@4b { /* u71 */ + compatible = "ti,ina226"; + reg = <0x4b>; + shunt-resistor = <5000>; + }; + ina226@4c { /* u77 */ + compatible = "ti,ina226"; + reg = <0x4c>; + shunt-resistor = <5000>; + }; + ina226@4d { /* u73 */ + compatible = "ti,ina226"; + reg = <0x4d>; + shunt-resistor = <5000>; + }; + ina226@4e { /* u79 */ + compatible = "ti,ina226"; + reg = <0x4e>; + shunt-resistor = <5000>; + }; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* NC */ + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */ + #clock-cells = <0>; + compatible = "infineon,irps5401"; + reg = <0x43>; + }; + irps5401_44: irps54012@44 { /* IRPS5401 - u55 */ + #clock-cells = <0>; + compatible = "infineon,irps5401"; + reg = <0x44>; + }; + irps5401_45: irps54012@45 { /* IRPS5401 - u57 */ + #clock-cells = <0>; + compatible = "infineon,irps5401"; + reg = <0x45>; + }; + /* u68 IR38064 +0 */ + /* u70 IR38060 +1 */ + /* u74 IR38060 +2 */ + /* u75 IR38060 +6 */ + /* J19 header too */ + + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* SYSMON */ + }; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + i2c-mux@74 { /* u26 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* + * IIC_EEPROM 1kB memory which uses 256B blocks + * where every block has different address. + * 0 - 256B address 0x54 + * 256B - 512B address 0x55 + * 512B - 768B address 0x56 + * 768B - 1024B address 0x57 + */ + eeprom: eeprom@54 { /* u88 */ + compatible = "atmel,24c08"; + reg = <0x54>; + }; + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + si5341: clock-generator@36 { /* SI5341 - u46 */ + compatible = "si5341"; + reg = <0x36>; + }; + + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + si570_1: clock-generator@5d { /* USER SI570 - u47 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <300000000>; + clock-frequency = <300000000>; + }; + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <156250000>; + clock-frequency = <148500000>; + }; + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + si5328: clock-generator@69 { /* SI5328 - u48 */ + compatible = "silabs,si5328"; + reg = <0x69>; + }; + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + sc18is603@2f { /* sc18is602 - u93 */ + compatible = "nxp,sc18is603"; + reg = <0x2f>; + /* 4 gpios for CS not handled by driver */ + /* + * USB2ANY cable or + * LMK04208 - u90 or + * LMX2594 - u102 or + * LMX2594 - u103 or + * LMX2594 - u104 + */ + }; + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* FMC connector */ + }; + /* 7 NC */ + }; + + i2c-mux@75 { + compatible = "nxp,pca9548"; /* u27 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* FMCP_HSPC_IIC */ + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* NC */ + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* SYSMON */ + }; + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* DDR4 SODIMM */ + dev@19 { /* u-boot detection FIXME */ + compatible = "xxx"; + reg = <0x19>; + }; + dev@30 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x30>; + }; + dev@35 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x35>; + }; + dev@36 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x36>; + }; + dev@51 { /* u-boot detection - maybe SPD */ + compatible = "xxx"; + reg = <0x51>; + }; + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* SFP3 */ + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* SFP2 */ + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* SFP1 */ + }; + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* SFP0 */ + }; + }; +}; + +&qspi { + status = "okay"; + is-dual = <1>; + flash@0 { + compatible = "m25p80"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + partition@qspi-fsbl-uboot { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + }; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; + /* SATA OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + phy-names = "sata-phy"; + phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + no-1-8-v; + xlnx,mio_bank = <1>; +}; + +&serdes { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + phy-names = "usb3-phy"; + phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; +}; -- cgit