From a89929bbb372b3eee49282439ce37ddf45fd54d4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 3 Dec 2018 21:05:55 +0100 Subject: ARM: dts: rmobile: Add soc label to Gen3 Add label to the /soc node, so it can be referenced from the U-Boot DTs. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- V2: Rebase on u-boot/master --- arch/arm/dts/r8a7796.dtsi | 2 +- arch/arm/dts/r8a77965.dtsi | 2 +- arch/arm/dts/r8a77970.dtsi | 2 +- arch/arm/dts/r8a77995.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/r8a7796.dtsi b/arch/arm/dts/r8a7796.dtsi index 011f0e596a..2b25a1d146 100644 --- a/arch/arm/dts/r8a7796.dtsi +++ b/arch/arm/dts/r8a7796.dtsi @@ -259,7 +259,7 @@ clock-frequency = <0>; }; - soc { + soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; #address-cells = <2>; diff --git a/arch/arm/dts/r8a77965.dtsi b/arch/arm/dts/r8a77965.dtsi index 7a5d68be13..f28a82c1d4 100644 --- a/arch/arm/dts/r8a77965.dtsi +++ b/arch/arm/dts/r8a77965.dtsi @@ -144,7 +144,7 @@ <&a57_1>; }; - soc { + soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; #address-cells = <2>; diff --git a/arch/arm/dts/r8a77970.dtsi b/arch/arm/dts/r8a77970.dtsi index 8dc599edfa..4f9f8ba3c1 100644 --- a/arch/arm/dts/r8a77970.dtsi +++ b/arch/arm/dts/r8a77970.dtsi @@ -72,7 +72,7 @@ clock-frequency = <0>; }; - soc { + soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; diff --git a/arch/arm/dts/r8a77995.dtsi b/arch/arm/dts/r8a77995.dtsi index 1d49279ac9..5ae37c60fd 100644 --- a/arch/arm/dts/r8a77995.dtsi +++ b/arch/arm/dts/r8a77995.dtsi @@ -66,7 +66,7 @@ clock-frequency = <0>; }; - soc { + soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; #address-cells = <2>; -- cgit From 8c7d9e1f62918bf2c781966ef2980e5c9c000657 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 3 Dec 2018 20:17:50 +0100 Subject: ARM: dts: rmobile: Extract RPC node to u-boot specific DT The RPC DT bindings are still work in progress. Extract the RPC DT node from the DT to allow easier update and so it can be replaced once the DT bindings are stable. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- V2: Rebase on u-boot/master --- arch/arm/dts/r8a7795-u-boot.dtsi | 10 ++++++++++ arch/arm/dts/r8a7795.dtsi | 8 -------- arch/arm/dts/r8a7796-u-boot.dtsi | 10 ++++++++++ arch/arm/dts/r8a7796.dtsi | 8 -------- arch/arm/dts/r8a77965-u-boot.dtsi | 10 ++++++++++ arch/arm/dts/r8a77965.dtsi | 8 -------- arch/arm/dts/r8a77970-eagle-u-boot.dts | 25 +++++++++++++++++++++++++ arch/arm/dts/r8a77970-eagle.dts | 20 -------------------- arch/arm/dts/r8a77970-u-boot.dtsi | 10 ++++++++++ arch/arm/dts/r8a77970.dtsi | 8 -------- arch/arm/dts/r8a77990-u-boot.dtsi | 10 ++++++++++ arch/arm/dts/r8a77990.dtsi | 8 -------- arch/arm/dts/r8a77995-u-boot.dtsi | 10 ++++++++++ arch/arm/dts/r8a77995.dtsi | 8 -------- 14 files changed, 85 insertions(+), 68 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/r8a7795-u-boot.dtsi b/arch/arm/dts/r8a7795-u-boot.dtsi index 526966ab24..cc22c57ae3 100644 --- a/arch/arm/dts/r8a7795-u-boot.dtsi +++ b/arch/arm/dts/r8a7795-u-boot.dtsi @@ -10,3 +10,13 @@ &extalr_clk { u-boot,dm-pre-reloc; }; + +&soc { + rpc: rpc@0xee200000 { + compatible = "renesas,rpc-r8a7795", "renesas,rpc"; + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; + clocks = <&cpg CPG_MOD 917>; + bank-width = <2>; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/r8a7795.dtsi b/arch/arm/dts/r8a7795.dtsi index af77bfe4e4..e2713eea48 100644 --- a/arch/arm/dts/r8a7795.dtsi +++ b/arch/arm/dts/r8a7795.dtsi @@ -1812,14 +1812,6 @@ dma-channels = <2>; }; - rpc: rpc@0xee200000 { - compatible = "renesas,rpc-r8a7795", "renesas,rpc"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; - }; - sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7795", "renesas,rcar-gen3-sdhi"; diff --git a/arch/arm/dts/r8a7796-u-boot.dtsi b/arch/arm/dts/r8a7796-u-boot.dtsi index 7cc60bc54a..4655259afe 100644 --- a/arch/arm/dts/r8a7796-u-boot.dtsi +++ b/arch/arm/dts/r8a7796-u-boot.dtsi @@ -10,3 +10,13 @@ &extalr_clk { u-boot,dm-pre-reloc; }; + +&soc { + rpc: rpc@0xee200000 { + compatible = "renesas,rpc-r8a7796", "renesas,rpc"; + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; + clocks = <&cpg CPG_MOD 917>; + bank-width = <2>; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/r8a7796.dtsi b/arch/arm/dts/r8a7796.dtsi index 2b25a1d146..903fef7284 100644 --- a/arch/arm/dts/r8a7796.dtsi +++ b/arch/arm/dts/r8a7796.dtsi @@ -1588,14 +1588,6 @@ status = "disabled"; }; - rpc: rpc@0xee200000 { - compatible = "renesas,rpc-r8a7796", "renesas,rpc"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; - }; - sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7796", "renesas,rcar-gen3-sdhi"; diff --git a/arch/arm/dts/r8a77965-u-boot.dtsi b/arch/arm/dts/r8a77965-u-boot.dtsi index f0023114d1..ca80ef8f29 100644 --- a/arch/arm/dts/r8a77965-u-boot.dtsi +++ b/arch/arm/dts/r8a77965-u-boot.dtsi @@ -10,3 +10,13 @@ &extalr_clk { u-boot,dm-pre-reloc; }; + +&soc { + rpc: rpc@0xee200000 { + compatible = "renesas,rpc-r8a77965", "renesas,rpc"; + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; + clocks = <&cpg CPG_MOD 917>; + bank-width = <2>; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/r8a77965.dtsi b/arch/arm/dts/r8a77965.dtsi index f28a82c1d4..840512ecfa 100644 --- a/arch/arm/dts/r8a77965.dtsi +++ b/arch/arm/dts/r8a77965.dtsi @@ -863,14 +863,6 @@ status = "disabled"; }; - rpc: rpc@0xee200000 { - compatible = "renesas,rpc-r8a77965", "renesas,rpc"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; - }; - sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a77965"; reg = <0 0xee100000 0 0x2000>; diff --git a/arch/arm/dts/r8a77970-eagle-u-boot.dts b/arch/arm/dts/r8a77970-eagle-u-boot.dts index 7ab71a1c65..0c716deb6f 100644 --- a/arch/arm/dts/r8a77970-eagle-u-boot.dts +++ b/arch/arm/dts/r8a77970-eagle-u-boot.dts @@ -7,3 +7,28 @@ #include "r8a77970-eagle.dts" #include "r8a77970-u-boot.dtsi" + +/ { + aliases { + spi0 = &rpc; + }; +}; + +&rpc { + num-cs = <1>; + status = "okay"; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + + flash0: spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "s25fs512s", "spi-flash", "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + reg = <0>; + status = "okay"; + }; +}; diff --git a/arch/arm/dts/r8a77970-eagle.dts b/arch/arm/dts/r8a77970-eagle.dts index 5dcad63492..107ac5d393 100644 --- a/arch/arm/dts/r8a77970-eagle.dts +++ b/arch/arm/dts/r8a77970-eagle.dts @@ -17,7 +17,6 @@ aliases { serial0 = &scif0; ethernet0 = &avb; - spi0 = &rpc; }; chosen { @@ -91,25 +90,6 @@ }; }; -&rpc { - num-cs = <1>; - status = "okay"; - spi-max-frequency = <50000000>; - #address-cells = <1>; - #size-cells = <0>; - - flash0: spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "s25fs512s", "spi-flash", "jedec,spi-nor"; - spi-max-frequency = <50000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - reg = <0>; - status = "okay"; - }; -}; - &rwdt { timeout-sec = <60>; status = "okay"; diff --git a/arch/arm/dts/r8a77970-u-boot.dtsi b/arch/arm/dts/r8a77970-u-boot.dtsi index 8fb7fe92db..2903fdb523 100644 --- a/arch/arm/dts/r8a77970-u-boot.dtsi +++ b/arch/arm/dts/r8a77970-u-boot.dtsi @@ -10,3 +10,13 @@ &extalr_clk { u-boot,dm-pre-reloc; }; + +&soc { + rpc: rpc@0xee200000 { + compatible = "renesas,rpc-r8a77970", "renesas,rpc"; + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; + clocks = <&cpg CPG_MOD 917>; + bank-width = <2>; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/r8a77970.dtsi b/arch/arm/dts/r8a77970.dtsi index 4f9f8ba3c1..9205da2acd 100644 --- a/arch/arm/dts/r8a77970.dtsi +++ b/arch/arm/dts/r8a77970.dtsi @@ -614,14 +614,6 @@ #address-cells = <1>; #size-cells = <0>; }; - - rpc: rpc@0xee200000 { - compatible = "renesas,rpc-r8a77970", "renesas,rpc"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; - }; }; timer { diff --git a/arch/arm/dts/r8a77990-u-boot.dtsi b/arch/arm/dts/r8a77990-u-boot.dtsi index 564c258e92..052caa720d 100644 --- a/arch/arm/dts/r8a77990-u-boot.dtsi +++ b/arch/arm/dts/r8a77990-u-boot.dtsi @@ -6,3 +6,13 @@ */ #include "r8a779x-u-boot.dtsi" + +&soc { + rpc: rpc@0xee200000 { + compatible = "renesas,rpc-r8a77990", "renesas,rpc"; + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; + clocks = <&cpg CPG_MOD 917>; + bank-width = <2>; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/r8a77990.dtsi b/arch/arm/dts/r8a77990.dtsi index ad20ea14cd..87625870e6 100644 --- a/arch/arm/dts/r8a77990.dtsi +++ b/arch/arm/dts/r8a77990.dtsi @@ -331,14 +331,6 @@ compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; }; - - rpc: rpc@0xee200000 { - compatible = "renesas,rpc-r8a77990", "renesas,rpc"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; - }; }; timer { diff --git a/arch/arm/dts/r8a77995-u-boot.dtsi b/arch/arm/dts/r8a77995-u-boot.dtsi index e0852c8df2..1f6efafb8b 100644 --- a/arch/arm/dts/r8a77995-u-boot.dtsi +++ b/arch/arm/dts/r8a77995-u-boot.dtsi @@ -6,3 +6,13 @@ */ #include "r8a779x-u-boot.dtsi" + +&soc { + rpc: rpc@0xee200000 { + compatible = "renesas,rpc-r8a77995", "renesas,rpc"; + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; + clocks = <&cpg CPG_MOD 917>; + bank-width = <2>; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/r8a77995.dtsi b/arch/arm/dts/r8a77995.dtsi index 5ae37c60fd..d191d8ad70 100644 --- a/arch/arm/dts/r8a77995.dtsi +++ b/arch/arm/dts/r8a77995.dtsi @@ -780,14 +780,6 @@ }; }; }; - - rpc: rpc@0xee200000 { - compatible = "renesas,rpc-r8a77995", "renesas,rpc"; - reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>; - clocks = <&cpg CPG_MOD 917>; - bank-width = <2>; - status = "disabled"; - }; }; timer { -- cgit From f529bc551b6d60ac231598d317cfa24b0ddc18af Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 3 Dec 2018 20:34:13 +0100 Subject: ARM: dts: rmobile: Extract USB nodes on M3N The USB nodes are not in Linux 4.17 DTs in M3N, pull them into U-Boot specific DT extras until they hit mainline Linux, to make syncing of DTs easier. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- V2: Rebase on u-boot/master --- arch/arm/dts/r8a77965-u-boot.dtsi | 55 +++++++++++++++++++++++++++++++++++++++ arch/arm/dts/r8a77965.dtsi | 53 +++++++------------------------------ 2 files changed, 64 insertions(+), 44 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/r8a77965-u-boot.dtsi b/arch/arm/dts/r8a77965-u-boot.dtsi index ca80ef8f29..15d9467ec0 100644 --- a/arch/arm/dts/r8a77965-u-boot.dtsi +++ b/arch/arm/dts/r8a77965-u-boot.dtsi @@ -19,4 +19,59 @@ bank-width = <2>; status = "disabled"; }; + + ehci0: usb@ee080100 { + compatible = "generic-ehci"; + reg = <0 0xee080100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + companion= <&ohci0>; + power-domains = <&sysc 32>; + resets = <&cpg 703>; + }; + + usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a77965", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee080200 0 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc 32>; + resets = <&cpg 703>; + #phy-cells = <0>; + }; + + ehci1: usb@ee0a0100 { + compatible = "generic-ehci"; + reg = <0 0xee0a0100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1>; + phy-names = "usb"; + companion= <&ohci1>; + power-domains = <&sysc 32>; + resets = <&cpg 702>; + }; + + usb2_phy1: usb-phy@ee0a0200 { + compatible = "renesas,usb2-phy-r8a77965", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0a0200 0 0x700>; + clocks = <&cpg CPG_MOD 702>; + power-domains = <&sysc 32>; + resets = <&cpg 702>; + #phy-cells = <0>; + }; + + xhci0: usb@ee000000 { + compatible = "renesas,xhci-r8a77965", + "renesas,rcar-gen3-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc 32>; + resets = <&cpg 328>; + }; }; diff --git a/arch/arm/dts/r8a77965.dtsi b/arch/arm/dts/r8a77965.dtsi index 840512ecfa..a47f079c02 100644 --- a/arch/arm/dts/r8a77965.dtsi +++ b/arch/arm/dts/r8a77965.dtsi @@ -645,28 +645,18 @@ }; ehci0: usb@ee080100 { - compatible = "generic-ehci"; reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - phys = <&usb2_phy0>; - phy-names = "usb"; - companion= <&ohci0>; - power-domains = <&sysc 32>; - resets = <&cpg 703>; - status = "disabled"; + /* placeholder */ }; usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a77965", - "renesas,rcar-gen3-usb2-phy"; reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc 32>; - resets = <&cpg 703>; - #phy-cells = <0>; - status = "disabled"; + /* placeholder */ + }; + + usb2_phy1: usb-phy@ee0a0200 { + reg = <0 0xee0a0200 0 0x700>; + /* placeholder */ }; ohci1: usb@ee0a0000 { @@ -675,16 +665,8 @@ }; ehci1: usb@ee0a0100 { - compatible = "generic-ehci"; reg = <0 0xee0a0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1>; - phy-names = "usb"; - companion= <&ohci1>; - power-domains = <&sysc 32>; - resets = <&cpg 702>; - status = "disabled"; + /* placeholder */ }; i2c0: i2c@e6500000 { @@ -852,17 +834,6 @@ }; }; - usb2_phy1: usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a77965", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; - clocks = <&cpg CPG_MOD 702>; - power-domains = <&sysc 32>; - resets = <&cpg 702>; - #phy-cells = <0>; - status = "disabled"; - }; - sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a77965"; reg = <0 0xee100000 0 0x2000>; @@ -919,14 +890,8 @@ }; xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a77965", - "renesas,rcar-gen3-xhci"; reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc 32>; - resets = <&cpg 328>; - status = "disabled"; + /* placeholder */ }; wdt0: watchdog@e6020000 { -- cgit From 830b94f76867628b990d31b7813bb21e868e3dd9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 3 Dec 2018 20:39:07 +0100 Subject: ARM: dts: rmobile: Extract SDHI nodes on M3N The SDHI nodes are not in Linux 4.17 DTs in M3N, pull them into U-Boot specific DT extras until they hit mainline Linux, to make syncing of DTs easier. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- V2: Rebase on u-boot/master --- arch/arm/dts/r8a77965-u-boot.dtsi | 44 +++++++++++++++++++++++++++++++++++++++ arch/arm/dts/r8a77965.dtsi | 32 ++++------------------------ 2 files changed, 48 insertions(+), 28 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/r8a77965-u-boot.dtsi b/arch/arm/dts/r8a77965-u-boot.dtsi index 15d9467ec0..cbd29b3aed 100644 --- a/arch/arm/dts/r8a77965-u-boot.dtsi +++ b/arch/arm/dts/r8a77965-u-boot.dtsi @@ -20,6 +20,50 @@ status = "disabled"; }; + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a77965"; + reg = <0 0xee100000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + power-domains = <&sysc 32>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: sd@ee120000 { + compatible = "renesas,sdhi-r8a77965"; + reg = <0 0xee120000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + power-domains = <&sysc 32>; + resets = <&cpg 313>; + status = "disabled"; + }; + + sdhi2: sd@ee140000 { + compatible = "renesas,sdhi-r8a77965"; + reg = <0 0xee140000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc 32>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi3: sd@ee160000 { + compatible = "renesas,sdhi-r8a77965"; + reg = <0 0xee160000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + power-domains = <&sysc 32>; + resets = <&cpg 311>; + status = "disabled"; + }; + ehci0: usb@ee080100 { compatible = "generic-ehci"; reg = <0 0xee080100 0 0x100>; diff --git a/arch/arm/dts/r8a77965.dtsi b/arch/arm/dts/r8a77965.dtsi index a47f079c02..84ecb4631f 100644 --- a/arch/arm/dts/r8a77965.dtsi +++ b/arch/arm/dts/r8a77965.dtsi @@ -835,47 +835,23 @@ }; sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a77965"; reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; - power-domains = <&sysc 32>; - resets = <&cpg 314>; - status = "disabled"; + /* placeholder */ }; sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a77965"; reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; - power-domains = <&sysc 32>; - resets = <&cpg 313>; - status = "disabled"; + /* placeholder */ }; sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a77965"; reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - max-frequency = <200000000>; - power-domains = <&sysc 32>; - resets = <&cpg 312>; - status = "disabled"; + /* placeholder */ }; sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a77965"; reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; - power-domains = <&sysc 32>; - resets = <&cpg 311>; - status = "disabled"; + /* placeholder */ }; usb3_phy0: usb-phy@e65ee000 { -- cgit From 1172ade967ee594a8075f2d80083a2b04329da29 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 3 Dec 2018 20:45:22 +0100 Subject: ARM: dts: rmobile: Extract AVB node extras on V3M Eagle The AVB node is not complete in Linux 4.17 DTs on V3M Eagle, pull the AVB node extras into U-Boot specific DT until they hit mainline Linux, to make syncing of DTs easier. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- V2: Rebase on u-boot/master --- arch/arm/dts/r8a77970-eagle-u-boot.dts | 20 ++++++++++++++++++++ arch/arm/dts/r8a77970-eagle.dts | 11 ----------- 2 files changed, 20 insertions(+), 11 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/r8a77970-eagle-u-boot.dts b/arch/arm/dts/r8a77970-eagle-u-boot.dts index 0c716deb6f..5b17f1d1f0 100644 --- a/arch/arm/dts/r8a77970-eagle-u-boot.dts +++ b/arch/arm/dts/r8a77970-eagle-u-boot.dts @@ -7,6 +7,7 @@ #include "r8a77970-eagle.dts" #include "r8a77970-u-boot.dtsi" +#include / { aliases { @@ -14,6 +15,25 @@ }; }; +&avb { + pinctrl-0 = <&avb0_pins>; + pinctrl-names = "default"; + +}; + +&phy0 { + reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; +}; + +&pfc { + avb0_pins: avb { + mux { + groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; + function = "avb0"; + }; + }; +}; + &rpc { num-cs = <1>; status = "okay"; diff --git a/arch/arm/dts/r8a77970-eagle.dts b/arch/arm/dts/r8a77970-eagle.dts index 107ac5d393..7fee1aa1ac 100644 --- a/arch/arm/dts/r8a77970-eagle.dts +++ b/arch/arm/dts/r8a77970-eagle.dts @@ -8,7 +8,6 @@ /dts-v1/; #include "r8a77970.dtsi" -#include / { model = "Renesas Eagle board based on r8a77970"; @@ -32,8 +31,6 @@ }; &avb { - pinctrl-0 = <&avb0_pins>; - pinctrl-names = "default"; renesas,no-ether-link; phy-handle = <&phy0>; phy-mode = "rgmii-id"; @@ -44,7 +41,6 @@ reg = <0>; interrupt-parent = <&gpio1>; interrupts = <17 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; }; }; @@ -72,13 +68,6 @@ }; &pfc { - avb0_pins: avb { - mux { - groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; - function = "avb0"; - }; - }; - i2c0_pins: i2c0 { groups = "i2c0"; function = "i2c0"; -- cgit From d2038b26e78bdac0931cf214c9b749fa13e0982c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 3 Dec 2018 20:48:16 +0100 Subject: ARM: dts: rmobile: Extract CPLD node on H3 and M3W ULCB The CPLD node is missing in Linux 4.17 DTs on H3/M3W ULCB, pull the node into U-Boot specific DT until it hits mainline Linux, to make syncing of DTs easier. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- V2: Rebase on u-boot/master --- arch/arm/dts/r8a7795-h3ulcb-u-boot.dts | 11 +++++++++++ arch/arm/dts/r8a7796-m3ulcb-u-boot.dts | 11 +++++++++++ arch/arm/dts/ulcb.dtsi | 9 --------- 3 files changed, 22 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts b/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts index 06bd4f24ca..5cb5e9c6fb 100644 --- a/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts +++ b/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts @@ -7,3 +7,14 @@ #include "r8a7795-h3ulcb.dts" #include "r8a7795-u-boot.dtsi" + +/ { + cpld { + compatible = "renesas,ulcb-cpld"; + status = "okay"; + gpio-sck = <&gpio6 8 0>; + gpio-mosi = <&gpio6 7 0>; + gpio-miso = <&gpio6 10 0>; + gpio-sstbz = <&gpio2 3 0>; + }; +}; diff --git a/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts b/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts index a1d13ccf28..78bd4f26bd 100644 --- a/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts +++ b/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts @@ -7,3 +7,14 @@ #include "r8a7796-m3ulcb.dts" #include "r8a7796-u-boot.dtsi" + +/ { + cpld { + compatible = "renesas,ulcb-cpld"; + status = "okay"; + gpio-sck = <&gpio6 8 0>; + gpio-mosi = <&gpio6 7 0>; + gpio-miso = <&gpio6 10 0>; + gpio-sstbz = <&gpio2 3 0>; + }; +}; diff --git a/arch/arm/dts/ulcb.dtsi b/arch/arm/dts/ulcb.dtsi index e16c7f245e..c805265343 100644 --- a/arch/arm/dts/ulcb.dtsi +++ b/arch/arm/dts/ulcb.dtsi @@ -24,15 +24,6 @@ stdout-path = "serial0:115200n8"; }; - cpld { - compatible = "renesas,ulcb-cpld"; - status = "okay"; - gpio-sck = <&gpio6 8 0>; - gpio-mosi = <&gpio6 7 0>; - gpio-miso = <&gpio6 10 0>; - gpio-sstbz = <&gpio2 3 0>; - }; - audio_clkout: audio-clkout { /* * This is same as <&rcar_sound 0> -- cgit From 750a147b3c73217235681aea4b700f9da181e654 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 3 Dec 2018 20:55:01 +0100 Subject: ARM: dts: rmobile: Extract SDHI extras on H3 and M3W ULCB The SDHI nodes are missing features supported in upstream U-Boot, like mode support properties. Pull the extras into U-Boot specific DT until it hits mainline Linux, to make syncing of DTs easier. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- V2: Rebase on u-boot/master --- arch/arm/dts/r8a7795-h3ulcb-u-boot.dts | 21 +++++++++++++++++++++ arch/arm/dts/r8a7796-m3ulcb-u-boot.dts | 21 +++++++++++++++++++++ arch/arm/dts/ulcb.dtsi | 12 +++--------- 3 files changed, 45 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts b/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts index 5cb5e9c6fb..ebbd234d78 100644 --- a/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts +++ b/arch/arm/dts/r8a7795-h3ulcb-u-boot.dts @@ -18,3 +18,24 @@ gpio-sstbz = <&gpio2 3 0>; }; }; + +&sdhi2_pins { + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; + power-source = <1800>; +}; + +&sdhi2_pins_uhs { + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; +}; + +&sdhi0 { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + max-frequency = <208000000>; +}; + +&sdhi2 { + mmc-hs400-1_8v; + max-frequency = <200000000>; +}; diff --git a/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts b/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts index 78bd4f26bd..4e960081f9 100644 --- a/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts +++ b/arch/arm/dts/r8a7796-m3ulcb-u-boot.dts @@ -18,3 +18,24 @@ gpio-sstbz = <&gpio2 3 0>; }; }; + +&sdhi2_pins { + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; + power-source = <1800>; +}; + +&sdhi2_pins_uhs { + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; +}; + +&sdhi0 { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + max-frequency = <208000000>; +}; + +&sdhi2 { + mmc-hs400-1_8v; + max-frequency = <200000000>; +}; diff --git a/arch/arm/dts/ulcb.dtsi b/arch/arm/dts/ulcb.dtsi index c805265343..6f814845f8 100644 --- a/arch/arm/dts/ulcb.dtsi +++ b/arch/arm/dts/ulcb.dtsi @@ -299,13 +299,13 @@ }; sdhi2_pins: sd2 { - groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; + groups = "sdhi2_data8", "sdhi2_ctrl"; function = "sdhi2"; - power-source = <1800>; + power-source = <3300>; }; sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; + groups = "sdhi2_data8", "sdhi2_ctrl"; function = "sdhi2"; power-source = <1800>; }; @@ -387,12 +387,8 @@ vqmmc-supply = <&vccq_sdhi0>; cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; bus-width = <4>; - sd-uhs-sdr12; - sd-uhs-sdr25; sd-uhs-sdr50; - sd-uhs-sdr104; status = "okay"; - max-frequency = <208000000>; }; &sdhi2 { @@ -405,10 +401,8 @@ vqmmc-supply = <®_1p8v>; bus-width = <8>; mmc-hs200-1_8v; - mmc-hs400-1_8v; non-removable; status = "okay"; - max-frequency = <200000000>; }; &ssi1 { -- cgit From 1bce3ec801a38fef5e3c96e2e65cf152f9fba9ec Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 3 Dec 2018 20:58:13 +0100 Subject: ARM: dts: rmobile: Extract SDHI extras on H3, M3W, M3N Salvator-X The SDHI nodes are missing features supported in upstream U-Boot, like mode support properties. Pull the extras into U-Boot specific DT until it hits mainline Linux, to make syncing of DTs easier. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- V2: Rebase on u-boot/master --- arch/arm/dts/r8a7795-salvator-x-u-boot.dts | 28 ++++++++++++++++++++++++++ arch/arm/dts/r8a7796-salvator-x-u-boot.dts | 28 ++++++++++++++++++++++++++ arch/arm/dts/r8a77965-salvator-x-u-boot.dts | 31 +++++++++++++++++++++++++++++ arch/arm/dts/salvator-common.dtsi | 17 +++------------- 4 files changed, 90 insertions(+), 14 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/r8a7795-salvator-x-u-boot.dts b/arch/arm/dts/r8a7795-salvator-x-u-boot.dts index 666fbf5a83..8be5e41a51 100644 --- a/arch/arm/dts/r8a7795-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a7795-salvator-x-u-boot.dts @@ -7,3 +7,31 @@ #include "r8a7795-salvator-x.dts" #include "r8a7795-u-boot.dtsi" + +&sdhi2_pins { + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; + power-source = <1800>; +}; + +&sdhi2_pins_uhs { + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; +}; + +&sdhi0 { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + max-frequency = <208000000>; +}; + +&sdhi2 { + mmc-hs400-1_8v; + max-frequency = <200000000>; +}; + +&sdhi3 { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + max-frequency = <208000000>; +}; diff --git a/arch/arm/dts/r8a7796-salvator-x-u-boot.dts b/arch/arm/dts/r8a7796-salvator-x-u-boot.dts index 7a8ad27795..44b2f9fb37 100644 --- a/arch/arm/dts/r8a7796-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a7796-salvator-x-u-boot.dts @@ -7,3 +7,31 @@ #include "r8a7796-salvator-x.dts" #include "r8a7796-u-boot.dtsi" + +&sdhi2_pins { + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; + power-source = <1800>; +}; + +&sdhi2_pins_uhs { + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; +}; + +&sdhi0 { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + max-frequency = <208000000>; +}; + +&sdhi2 { + mmc-hs400-1_8v; + max-frequency = <200000000>; +}; + +&sdhi3 { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + max-frequency = <208000000>; +}; diff --git a/arch/arm/dts/r8a77965-salvator-x-u-boot.dts b/arch/arm/dts/r8a77965-salvator-x-u-boot.dts index 06002b629a..9e0cd26f40 100644 --- a/arch/arm/dts/r8a77965-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a77965-salvator-x-u-boot.dts @@ -7,3 +7,34 @@ #include "r8a77965-salvator-x.dts" #include "r8a77965-u-boot.dtsi" + +&sdhi2_pins { + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; + power-source = <1800>; +}; + +&sdhi2_pins_uhs { + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; +}; + +&sdhi0 { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + max-frequency = <208000000>; + status = "okay"; +}; + +&sdhi2 { + mmc-hs400-1_8v; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdhi3 { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + max-frequency = <208000000>; + status = "okay"; +}; diff --git a/arch/arm/dts/salvator-common.dtsi b/arch/arm/dts/salvator-common.dtsi index b036a713ea..2a7f36abd2 100644 --- a/arch/arm/dts/salvator-common.dtsi +++ b/arch/arm/dts/salvator-common.dtsi @@ -480,13 +480,13 @@ }; sdhi2_pins: sd2 { - groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; + groups = "sdhi2_data8", "sdhi2_ctrl"; function = "sdhi2"; - power-source = <1800>; + power-source = <3300>; }; sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; + groups = "sdhi2_data8", "sdhi2_ctrl"; function = "sdhi2"; power-source = <1800>; }; @@ -618,13 +618,8 @@ cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; bus-width = <4>; - sd-uhs-sdr12; - sd-uhs-sdr25; sd-uhs-sdr50; - sd-uhs-sdr104; status = "okay"; - - max-frequency = <208000000>; }; &sdhi2 { @@ -637,11 +632,9 @@ vqmmc-supply = <®_1p8v>; bus-width = <8>; mmc-hs200-1_8v; - mmc-hs400-1_8v; non-removable; fixed-emmc-driver-type = <1>; status = "okay"; - max-frequency = <200000000>; }; &sdhi3 { @@ -654,12 +647,8 @@ cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; bus-width = <4>; - sd-uhs-sdr12; - sd-uhs-sdr25; sd-uhs-sdr50; - sd-uhs-sdr104; status = "okay"; - max-frequency = <208000000>; }; &ssi1 { -- cgit From 6bdb7a80cb06f1f96d5c0468e8881c7fd81be3df Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 3 Dec 2018 22:12:47 +0100 Subject: ARM: dts: rmobile: Extract SDHI nodes on E3 Ebisu The SDHI nodes are not in Linux 4.17 DTs in E3, pull them into U-Boot specific DT extras until they hit mainline Linux, to make syncing of DTs easier. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- V2: Rebase on u-boot/master --- arch/arm/dts/r8a77990-ebisu-u-boot.dts | 158 +++++++++++++++++++++++++++++++++ arch/arm/dts/r8a77990-ebisu.dts | 36 -------- arch/arm/dts/r8a77990-u-boot.dtsi | 24 +++++ arch/arm/dts/r8a77990.dtsi | 24 ----- 4 files changed, 182 insertions(+), 60 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/r8a77990-ebisu-u-boot.dts b/arch/arm/dts/r8a77990-ebisu-u-boot.dts index 8d4ea88a91..17b749545f 100644 --- a/arch/arm/dts/r8a77990-ebisu-u-boot.dts +++ b/arch/arm/dts/r8a77990-ebisu-u-boot.dts @@ -7,3 +7,161 @@ #include "r8a77990-ebisu.dts" #include "r8a77990-u-boot.dtsi" + +/ { + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + + vcc_sdhi1: regulator-vcc-sdhi1 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; +}; + +&pfc { + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; + + sdhi1_pins: sd1 { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <3300>; + }; + + sdhi1_pins_uhs: sd1_uhs { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <1800>; + }; + + sdhi3_pins: sd2 { + groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds"; + function = "sdhi3"; + power-source = <1800>; + }; + + sdhi3_pins_uhs: sd2_uhs { + groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds"; + function = "sdhi3"; + power-source = <1800>; + }; +}; + +&sdhi0 { + /* full size SD */ + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; + max-frequency = <208000000>; +}; + +&sdhi1 { + /* microSD */ + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi1>; + vqmmc-supply = <&vccq_sdhi1>; + cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>; + bus-width = <4>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; + max-frequency = <208000000>; +}; + +&sdhi3 { + /* used for on-board 8bit eMMC */ + pinctrl-0 = <&sdhi3_pins>; + pinctrl-1 = <&sdhi3_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/dts/r8a77990-ebisu.dts b/arch/arm/dts/r8a77990-ebisu.dts index 0f269d0469..cea08d7488 100644 --- a/arch/arm/dts/r8a77990-ebisu.dts +++ b/arch/arm/dts/r8a77990-ebisu.dts @@ -142,42 +142,6 @@ function = "scif_clk"; }; - sdhi0_pins: sd0 { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <3300>; - }; - - sdhi0_pins_uhs: sd0_uhs { - groups = "sdhi0_data4", "sdhi0_ctrl"; - function = "sdhi0"; - power-source = <1800>; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <3300>; - }; - - sdhi1_pins_uhs: sd1_uhs { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <1800>; - }; - - sdhi3_pins: sd2 { - groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds"; - function = "sdhi3"; - power-source = <1800>; - }; - - sdhi3_pins_uhs: sd2_uhs { - groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds"; - function = "sdhi3"; - power-source = <1800>; - }; - usb0_pins: usb0 { groups = "usb0"; function = "usb0"; diff --git a/arch/arm/dts/r8a77990-u-boot.dtsi b/arch/arm/dts/r8a77990-u-boot.dtsi index 052caa720d..288e57e4bc 100644 --- a/arch/arm/dts/r8a77990-u-boot.dtsi +++ b/arch/arm/dts/r8a77990-u-boot.dtsi @@ -15,4 +15,28 @@ bank-width = <2>; status = "disabled"; }; + + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a77990"; + reg = <0 0xee100000 0 0x2000>; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + status = "disabled"; + }; + + sdhi1: sd@ee120000 { + compatible = "renesas,sdhi-r8a77990"; + reg = <0 0xee120000 0 0x2000>; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + status = "disabled"; + }; + + sdhi3: sd@ee160000 { + compatible = "renesas,sdhi-r8a77990"; + reg = <0 0xee160000 0 0x2000>; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + status = "disabled"; + }; }; diff --git a/arch/arm/dts/r8a77990.dtsi b/arch/arm/dts/r8a77990.dtsi index 87625870e6..593d35a267 100644 --- a/arch/arm/dts/r8a77990.dtsi +++ b/arch/arm/dts/r8a77990.dtsi @@ -223,30 +223,6 @@ reg = <0 0xe6160000 0 0x0200>; }; - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a77990"; - reg = <0 0xee100000 0 0x2000>; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; - status = "disabled"; - }; - - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a77990"; - reg = <0 0xee120000 0 0x2000>; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; - status = "disabled"; - }; - - sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a77990"; - reg = <0 0xee160000 0 0x2000>; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; - status = "disabled"; - }; - sysc: system-controller@e6180000 { compatible = "renesas,r8a77990-sysc"; reg = <0 0xe6180000 0 0x0400>; -- cgit From 47179e57372e11630014e5229b23de0f68f57577 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 3 Dec 2018 22:14:09 +0100 Subject: ARM: dts: rmobile: Extract SCIF2 node on E3 Ebisu The SCIF2 node is not in Linux 4.17 DTs on E3, pull it into U-Boot specific DT extras until it hits mainline Linux, to make syncing of DTs easier. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- V2: Rebase on u-boot/master --- arch/arm/dts/r8a77990-ebisu-u-boot.dts | 19 +++++++++++++++++++ arch/arm/dts/r8a77990-ebisu.dts | 16 ---------------- 2 files changed, 19 insertions(+), 16 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/r8a77990-ebisu-u-boot.dts b/arch/arm/dts/r8a77990-ebisu-u-boot.dts index 17b749545f..b030d5c649 100644 --- a/arch/arm/dts/r8a77990-ebisu-u-boot.dts +++ b/arch/arm/dts/r8a77990-ebisu-u-boot.dts @@ -77,6 +77,19 @@ }; &pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_a"; + function = "scif_clk"; + }; + sdhi0_pins: sd0 { groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; @@ -114,6 +127,12 @@ }; }; +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &sdhi0 { /* full size SD */ pinctrl-0 = <&sdhi0_pins>; diff --git a/arch/arm/dts/r8a77990-ebisu.dts b/arch/arm/dts/r8a77990-ebisu.dts index cea08d7488..e337c902cb 100644 --- a/arch/arm/dts/r8a77990-ebisu.dts +++ b/arch/arm/dts/r8a77990-ebisu.dts @@ -122,9 +122,6 @@ }; &pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - avb_pins: avb { mux { groups = "avb_link", "avb_mii"; @@ -132,16 +129,6 @@ }; }; - scif2_pins: scif2 { - groups = "scif2_data_a"; - function = "scif2"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk_a"; - function = "scif_clk"; - }; - usb0_pins: usb0 { groups = "usb0"; function = "usb0"; @@ -208,8 +195,5 @@ }; &scif2 { - pinctrl-0 = <&scif2_pins>; - pinctrl-names = "default"; - status = "okay"; }; -- cgit From 4e96b693eecb927925d8e844b3d6b61af1847152 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 3 Dec 2018 21:30:44 +0100 Subject: ARM: dts: rmobile: Extract i2c6 on M2W Porter The i2c6 node is missing in mainline Linux thus far, pull it into U-Boot specific DT until it hits mainline Linux, to make syncing of DTs easier. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- V2: Rebase on u-boot/master --- arch/arm/dts/r8a7791-porter-u-boot.dts | 5 +++++ arch/arm/dts/r8a7791-porter.dts | 5 ----- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/r8a7791-porter-u-boot.dts b/arch/arm/dts/r8a7791-porter-u-boot.dts index 797fa9d6e7..275f6b4375 100644 --- a/arch/arm/dts/r8a7791-porter-u-boot.dts +++ b/arch/arm/dts/r8a7791-porter-u-boot.dts @@ -11,3 +11,8 @@ &scif0 { u-boot,dm-pre-reloc; }; + +&i2c6 { + status = "okay"; + clock-frequency = <400000>; +}; diff --git a/arch/arm/dts/r8a7791-porter.dts b/arch/arm/dts/r8a7791-porter.dts index fa9a57d770..f2d5723fbd 100644 --- a/arch/arm/dts/r8a7791-porter.dts +++ b/arch/arm/dts/r8a7791-porter.dts @@ -372,11 +372,6 @@ clock-frequency = <400000>; }; -&i2c6 { - status = "okay"; - clock-frequency = <400000>; -}; - &sata0 { status = "okay"; }; -- cgit From 3b255531b60b05308971e4ec0b10fdc75cd3b1b4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 3 Dec 2018 21:39:48 +0100 Subject: ARM: dts: rmobile: Sync Gen2 DTs with Linux 4.19.6 Synchronize DTs with mainline Linux 4.19.6 , commit 96db90800c06d3fe3fa08eb6222fe201286bb778 Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- V2: Rebase on u-boot/master --- arch/arm/dts/r8a7790-lager.dts | 8 ++-- arch/arm/dts/r8a7790.dtsi | 101 +++++++++++++++++++++++++++++++++++---- arch/arm/dts/r8a7791-koelsch.dts | 11 ++--- arch/arm/dts/r8a7791-porter.dts | 41 ++++++++++++++-- arch/arm/dts/r8a7791.dtsi | 51 ++++++++++++++++++-- arch/arm/dts/r8a7792-blanche.dts | 5 ++ arch/arm/dts/r8a7792.dtsi | 19 +++++++- arch/arm/dts/r8a7793-gose.dts | 11 ++--- arch/arm/dts/r8a7793.dtsi | 52 ++++++++++++++++++-- arch/arm/dts/r8a7794-alt.dts | 14 ++++-- arch/arm/dts/r8a7794-silk.dts | 8 ++-- arch/arm/dts/r8a7794.dtsi | 28 ++++++++++- 12 files changed, 309 insertions(+), 40 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/r8a7790-lager.dts b/arch/arm/dts/r8a7790-lager.dts index dcda98c6ae..50312e752e 100644 --- a/arch/arm/dts/r8a7790-lager.dts +++ b/arch/arm/dts/r8a7790-lager.dts @@ -899,9 +899,6 @@ status = "okay"; port { - #address-cells = <1>; - #size-cells = <0>; - vin1ep0: endpoint { remote-endpoint = <&adv7180>; bus-width = <8>; @@ -926,6 +923,11 @@ }; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &ssi1 { shared-pin; }; diff --git a/arch/arm/dts/r8a7790.dtsi b/arch/arm/dts/r8a7790.dtsi index ed09e56c36..0925bdca43 100644 --- a/arch/arm/dts/r8a7790.dtsi +++ b/arch/arm/dts/r8a7790.dtsi @@ -76,12 +76,12 @@ compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1300000000>; - voltage-tolerance = <1>; /* 1% */ clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; - clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7790_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ /* kHz - uV - OPPs unknown yet */ operating-points = <1400000 1000000>, @@ -101,6 +101,16 @@ power-domains = <&sysc R8A7790_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; }; cpu2: cpu@2 { @@ -112,6 +122,16 @@ power-domains = <&sysc R8A7790_PD_CA15_CPU2>; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; }; cpu3: cpu@3 { @@ -123,6 +143,16 @@ power-domains = <&sysc R8A7790_PD_CA15_CPU3>; next-level-cache = <&L2_CA15>; capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; }; cpu4: cpu@100 { @@ -199,6 +229,24 @@ clock-frequency = <0>; }; + pmu-0 { + compatible = "arm,cortex-a15-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + pmu-1 { + compatible = "arm,cortex-a7-pmu"; + interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + /* External SCIF clock */ scif_clk: scif { compatible = "fixed-clock"; @@ -215,6 +263,16 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7790-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7790", "renesas,rcar-gen2-gpio"; @@ -440,7 +498,7 @@ smp-sram@0 { compatible = "renesas,smp-sram"; - reg = <0 0x10>; + reg = <0 0x100>; }; }; @@ -1541,7 +1599,7 @@ interrupt-controller; reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; - interrupts = ; + interrupts = ; clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; @@ -1612,6 +1670,33 @@ resets = <&cpg 127>; }; + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 119>; + }; + + fdp1@fe944000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe944000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 118>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 118>; + }; + + fdp1@fe948000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe948000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 117>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 117>; + }; + jpu: jpeg-codec@fe980000 { compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu"; @@ -1770,10 +1855,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; /* External USB clock - can be overridden by the board */ diff --git a/arch/arm/dts/r8a7791-koelsch.dts b/arch/arm/dts/r8a7791-koelsch.dts index be96bfd4f3..ce22db01fb 100644 --- a/arch/arm/dts/r8a7791-koelsch.dts +++ b/arch/arm/dts/r8a7791-koelsch.dts @@ -640,6 +640,11 @@ status = "okay"; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &sata0 { status = "okay"; }; @@ -847,9 +852,6 @@ pinctrl-names = "default"; port { - #address-cells = <1>; - #size-cells = <0>; - vin0ep2: endpoint { remote-endpoint = <&adv7612_out>; bus-width = <24>; @@ -868,9 +870,6 @@ pinctrl-names = "default"; port { - #address-cells = <1>; - #size-cells = <0>; - vin1ep: endpoint { remote-endpoint = <&adv7180>; bus-width = <8>; diff --git a/arch/arm/dts/r8a7791-porter.dts b/arch/arm/dts/r8a7791-porter.dts index f2d5723fbd..f02036e5de 100644 --- a/arch/arm/dts/r8a7791-porter.dts +++ b/arch/arm/dts/r8a7791-porter.dts @@ -372,10 +372,43 @@ clock-frequency = <400000>; }; +&i2c6 { + status = "okay"; + clock-frequency = <100000>; + + pmic@5a { + compatible = "dlg,da9063l"; + reg = <0x5a>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + + wdt { + compatible = "dlg,da9063-watchdog"; + }; + }; + + vdd_dvfs: regulator@68 { + compatible = "dlg,da9210"; + reg = <0x68>; + interrupt-parent = <&irqc0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + &sata0 { status = "okay"; }; +&cpu0 { + cpu0-supply = <&vdd_dvfs>; +}; + /* composite video input */ &vin0 { status = "okay"; @@ -383,9 +416,6 @@ pinctrl-names = "default"; port { - #address-cells = <1>; - #size-cells = <0>; - vin0ep: endpoint { remote-endpoint = <&adv7180>; bus-width = <8>; @@ -478,6 +508,11 @@ }; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &ssi1 { shared-pin; }; diff --git a/arch/arm/dts/r8a7791.dtsi b/arch/arm/dts/r8a7791.dtsi index d728738ba8..991ac6feed 100644 --- a/arch/arm/dts/r8a7791.dtsi +++ b/arch/arm/dts/r8a7791.dtsi @@ -75,11 +75,11 @@ compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1500000000>; - voltage-tolerance = <1>; /* 1% */ clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; - clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7791_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ /* kHz - uV - OPPs unknown yet */ operating-points = <1500000 1000000>, @@ -98,6 +98,16 @@ clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; power-domains = <&sysc R8A7791_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; }; L2_CA15: cache-controller-0 { @@ -123,6 +133,13 @@ clock-frequency = <0>; }; + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + /* External SCIF clock */ scif_clk: scif { compatible = "fixed-clock"; @@ -139,6 +156,16 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7791-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7791", "renesas,rcar-gen2-gpio"; @@ -404,7 +431,7 @@ smp-sram@0 { compatible = "renesas,smp-sram"; - reg = <0 0x10>; + reg = <0 0x100>; }; }; @@ -1618,6 +1645,24 @@ resets = <&cpg 127>; }; + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 119>; + }; + + fdp1@fe944000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe944000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 118>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 118>; + }; + jpu: jpeg-codec@fe980000 { compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu"; diff --git a/arch/arm/dts/r8a7792-blanche.dts b/arch/arm/dts/r8a7792-blanche.dts index 023d870bed..f92301290b 100644 --- a/arch/arm/dts/r8a7792-blanche.dts +++ b/arch/arm/dts/r8a7792-blanche.dts @@ -236,6 +236,11 @@ }; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; diff --git a/arch/arm/dts/r8a7792.dtsi b/arch/arm/dts/r8a7792.dtsi index 8e26dede30..63a978ec81 100644 --- a/arch/arm/dts/r8a7792.dtsi +++ b/arch/arm/dts/r8a7792.dtsi @@ -82,6 +82,13 @@ clock-frequency = <0>; }; + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + /* External SCIF clock */ scif_clk: scif { compatible = "fixed-clock"; @@ -98,6 +105,16 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7792-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7792", "renesas,rcar-gen2-gpio"; @@ -338,7 +355,7 @@ smp-sram@0 { compatible = "renesas,smp-sram"; - reg = <0 0x10>; + reg = <0 0x100>; }; }; diff --git a/arch/arm/dts/r8a7793-gose.dts b/arch/arm/dts/r8a7793-gose.dts index 9c893458ce..6b2f3a4fd1 100644 --- a/arch/arm/dts/r8a7793-gose.dts +++ b/arch/arm/dts/r8a7793-gose.dts @@ -596,6 +596,11 @@ status = "okay"; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; @@ -755,9 +760,6 @@ pinctrl-names = "default"; port { - #address-cells = <1>; - #size-cells = <0>; - vin0ep2: endpoint { remote-endpoint = <&adv7612_out>; bus-width = <24>; @@ -777,9 +779,6 @@ status = "okay"; port { - #address-cells = <1>; - #size-cells = <0>; - vin1ep: endpoint { remote-endpoint = <&adv7180_out>; bus-width = <8>; diff --git a/arch/arm/dts/r8a7793.dtsi b/arch/arm/dts/r8a7793.dtsi index 8201b4e8d1..620a570307 100644 --- a/arch/arm/dts/r8a7793.dtsi +++ b/arch/arm/dts/r8a7793.dtsi @@ -67,10 +67,10 @@ compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1500000000>; - voltage-tolerance = <1>; /* 1% */ clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; - clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7793_PD_CA15_CPU0>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ /* kHz - uV - OPPs unknown yet */ operating-points = <1500000 1000000>, @@ -89,6 +89,17 @@ clock-frequency = <1500000000>; clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; power-domains = <&sysc R8A7793_PD_CA15_CPU1>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; + next-level-cache = <&L2_CA15>; }; L2_CA15: cache-controller-0 { @@ -107,6 +118,13 @@ clock-frequency = <0>; }; + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + /* External SCIF clock */ scif_clk: scif { compatible = "fixed-clock"; @@ -123,6 +141,16 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7793-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7793", "renesas,rcar-gen2-gpio"; @@ -389,7 +417,7 @@ smp-sram@0 { compatible = "renesas,smp-sram"; - reg = <0 0x10>; + reg = <0 0x100>; }; }; @@ -1287,6 +1315,24 @@ resets = <&cpg 408>; }; + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 119>; + }; + + fdp1@fe944000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe944000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 118>; + power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 118>; + }; + du: display@feb00000 { compatible = "renesas,du-r8a7793"; reg = <0 0xfeb00000 0 0x40000>; diff --git a/arch/arm/dts/r8a7794-alt.dts b/arch/arm/dts/r8a7794-alt.dts index af3c67eb02..ef7e2a837d 100644 --- a/arch/arm/dts/r8a7794-alt.dts +++ b/arch/arm/dts/r8a7794-alt.dts @@ -178,6 +178,12 @@ }; }; }; + + eeprom@50 { + compatible = "renesas,r1ex24002", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; }; /* @@ -327,6 +333,11 @@ status = "okay"; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &sdhi0 { pinctrl-0 = <&sdhi0_pins>; pinctrl-1 = <&sdhi0_pins_uhs>; @@ -372,9 +383,6 @@ pinctrl-names = "default"; port { - #address-cells = <1>; - #size-cells = <0>; - vin0ep: endpoint { remote-endpoint = <&adv7180>; bus-width = <8>; diff --git a/arch/arm/dts/r8a7794-silk.dts b/arch/arm/dts/r8a7794-silk.dts index 50dad43c10..daec965889 100644 --- a/arch/arm/dts/r8a7794-silk.dts +++ b/arch/arm/dts/r8a7794-silk.dts @@ -472,9 +472,6 @@ pinctrl-names = "default"; port { - #address-cells = <1>; - #size-cells = <0>; - vin0ep: endpoint { remote-endpoint = <&adv7180>; bus-width = <8>; @@ -537,6 +534,11 @@ }; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &ssi1 { shared-pin; }; diff --git a/arch/arm/dts/r8a7794.dtsi b/arch/arm/dts/r8a7794.dtsi index 0cc07b30d1..ea2ca4bdaf 100644 --- a/arch/arm/dts/r8a7794.dtsi +++ b/arch/arm/dts/r8a7794.dtsi @@ -100,6 +100,13 @@ clock-frequency = <0>; }; + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + /* External SCIF clock */ scif_clk: scif { compatible = "fixed-clock"; @@ -116,6 +123,16 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7794-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7794", "renesas,rcar-gen2-gpio"; @@ -345,7 +362,7 @@ smp-sram@0 { compatible = "renesas,smp-sram"; - reg = <0 0x10>; + reg = <0 0x100>; }; }; @@ -1320,6 +1337,15 @@ resets = <&cpg 128>; }; + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 119>; + }; + du: display@feb00000 { compatible = "renesas,du-r8a7794"; reg = <0 0xfeb00000 0 0x40000>; -- cgit From cbff9f80cedd4bd4c00ed3fe506b1fc2b209c681 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 3 Dec 2018 21:43:05 +0100 Subject: ARM: dts: rmobile: Sync Gen3 DTs with Linux 4.19.6 Synchronize DTs with mainline Linux 4.19.6 , commit 96db90800c06d3fe3fa08eb6222fe201286bb778 Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- V2: Rebase on u-boot/master --- arch/arm/dts/r8a7795-salvator-x.dts | 48 +- arch/arm/dts/r8a7795.dtsi | 2512 ++++++++++++++++++++-------------- arch/arm/dts/r8a7796-salvator-x.dts | 30 +- arch/arm/dts/r8a7796.dtsi | 2453 +++++++++++++++++++-------------- arch/arm/dts/r8a77965-salvator-x.dts | 28 + arch/arm/dts/r8a77965.dtsi | 1970 +++++++++++++++++++------- arch/arm/dts/r8a77970-eagle.dts | 116 ++ arch/arm/dts/r8a77970.dtsi | 661 ++++++--- arch/arm/dts/r8a77990-ebisu.dts | 139 +- arch/arm/dts/r8a77990.dtsi | 205 ++- arch/arm/dts/r8a77995-draak.dts | 130 +- arch/arm/dts/r8a77995.dtsi | 976 +++++++------ arch/arm/dts/salvator-common.dtsi | 217 ++- arch/arm/dts/salvator-x.dtsi | 7 +- arch/arm/dts/ulcb.dtsi | 48 +- 15 files changed, 6215 insertions(+), 3325 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/r8a7795-salvator-x.dts b/arch/arm/dts/r8a7795-salvator-x.dts index 36373d6cce..446822f575 100644 --- a/arch/arm/dts/r8a7795-salvator-x.dts +++ b/arch/arm/dts/r8a7795-salvator-x.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source for the Salvator-X board + * Device Tree Source for the Salvator-X board with R-Car H3 ES2.0 * * Copyright (C) 2015 Renesas Electronics Corp. */ @@ -53,6 +53,12 @@ status = "okay"; }; +&sound_card { + dais = <&rsnd_port0 /* ak4613 */ + &rsnd_port1 /* HDMI0 */ + &rsnd_port2>; /* HDMI1 */ +}; + &hdmi0 { status = "okay"; @@ -63,6 +69,12 @@ remote-endpoint = <&hdmi0_con>; }; }; + port@2 { + reg = <2>; + dw_hdmi0_snd_in: endpoint { + remote-endpoint = <&rsnd_endpoint1>; + }; + }; }; }; @@ -80,6 +92,12 @@ remote-endpoint = <&hdmi1_con>; }; }; + port@2 { + reg = <2>; + dw_hdmi1_snd_in: endpoint { + remote-endpoint = <&rsnd_endpoint2>; + }; + }; }; }; @@ -91,6 +109,34 @@ status = "okay"; }; +&rcar_sound { + ports { + /* rsnd_port0 is on salvator-common */ + rsnd_port1: port@1 { + rsnd_endpoint1: endpoint { + remote-endpoint = <&dw_hdmi0_snd_in>; + + dai-format = "i2s"; + bitclock-master = <&rsnd_endpoint1>; + frame-master = <&rsnd_endpoint1>; + + playback = <&ssi2>; + }; + }; + rsnd_port2: port@2 { + rsnd_endpoint2: endpoint { + remote-endpoint = <&dw_hdmi1_snd_in>; + + dai-format = "i2s"; + bitclock-master = <&rsnd_endpoint2>; + frame-master = <&rsnd_endpoint2>; + + playback = <&ssi3>; + }; + }; + }; +}; + &pfc { usb2_pins: usb2 { groups = "usb2"; diff --git a/arch/arm/dts/r8a7795.dtsi b/arch/arm/dts/r8a7795.dtsi index e2713eea48..c87eed77de 100644 --- a/arch/arm/dts/r8a7795.dtsi +++ b/arch/arm/dts/r8a7795.dtsi @@ -27,6 +27,91 @@ i2c7 = &i2c_dvfs; }; + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <900000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <960000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -44,7 +129,7 @@ }; a57_1: cpu@1 { - compatible = "arm,cortex-a57","arm,armv8"; + compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x1>; device_type = "cpu"; power-domains = <&sysc R8A7795_PD_CA57_CPU1>; @@ -56,7 +141,7 @@ }; a57_2: cpu@2 { - compatible = "arm,cortex-a57","arm,armv8"; + compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x2>; device_type = "cpu"; power-domains = <&sysc R8A7795_PD_CA57_CPU2>; @@ -68,7 +153,7 @@ }; a57_3: cpu@3 { - compatible = "arm,cortex-a57","arm,armv8"; + compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x3>; device_type = "cpu"; power-domains = <&sysc R8A7795_PD_CA57_CPU3>; @@ -91,7 +176,7 @@ }; a53_1: cpu@101 { - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x101>; device_type = "cpu"; power-domains = <&sysc R8A7795_PD_CA53_CPU1>; @@ -102,7 +187,7 @@ }; a53_2: cpu@102 { - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x102>; device_type = "cpu"; power-domains = <&sysc R8A7795_PD_CA53_CPU2>; @@ -113,7 +198,7 @@ }; a53_3: cpu@103 { - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x103>; device_type = "cpu"; power-domains = <&sysc R8A7795_PD_CA53_CPU3>; @@ -152,91 +237,6 @@ clock-frequency = <0>; }; - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <830000>; - clock-latency-ns = <300000>; - opp-suspend; - }; - opp-1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - opp-1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <960000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - }; - - cluster1_opp: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - }; - /* External PCIe clock - can be overridden by the board */ pcie_bus_clk: pcie_bus { compatible = "fixed-clock"; @@ -244,18 +244,6 @@ clock-frequency = <0>; }; - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, - <&a57_1>, - <&a57_2>, - <&a57_3>; - }; - pmu_a53 { compatible = "arm,cortex-a53-pmu"; interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, @@ -268,6 +256,18 @@ <&a53_3>; }; + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a57_0>, + <&a57_1>, + <&a57_2>, + <&a57_3>; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; @@ -288,24 +288,7 @@ #size-cells = <2>; ranges; - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - wdt0: watchdog@e6020000 { + rwdt: watchdog@e6020000 { compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; clocks = <&cpg CPG_MOD 402>; @@ -434,6 +417,11 @@ resets = <&cpg 905>; }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7795"; + reg = <0 0xe6060000 0 0x50c>; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a7795-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; @@ -449,20 +437,25 @@ reg = <0 0xe6160000 0 0x0200>; }; - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - sysc: system-controller@e6180000 { compatible = "renesas,r8a7795-sysc"; reg = <0 0xe6180000 0 0x0400>; #power-domain-cells = <1>; }; - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a7795"; - reg = <0 0xe6060000 0 0x50c>; + tsc: thermal@e6198000 { + compatible = "renesas,r8a7795-thermal"; + reg = <0 0xe6198000 0 0x100>, + <0 0xe61a0000 0 0x100>, + <0 0xe61a8000 0 0x100>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <1>; + status = "okay"; }; intc_ex: interrupt-controller@e61c0000 { @@ -481,153 +474,335 @@ resets = <&cpg 407>; }; - ipmmu_vi0: mmu@febd0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_vi1: mmu@febe0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfebe0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 15>; + resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; - ipmmu_vp0: mmu@fe990000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 16>; - power-domains = <&sysc R8A7795_PD_A3VP>; - #iommu-cells = <1>; + i2c2: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; - ipmmu_vp1: mmu@fe980000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfe980000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 17>; - power-domains = <&sysc R8A7795_PD_A3VP>; - #iommu-cells = <1>; + arm_cc630p: crypto@e6601000 { + compatible = "arm,cryptocell-630p-ree"; + interrupts = ; + reg = <0x0 0xe6601000 0 0x1000>; + clocks = <&cpg CPG_MOD 229>; + resets = <&cpg 229>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; }; - ipmmu_vc0: mmu@fe6b0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - power-domains = <&sysc R8A7795_PD_A3VC>; - #iommu-cells = <1>; + i2c3: i2c@e66d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 928>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; - ipmmu_vc1: mmu@fe6f0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfe6f0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 13>; - power-domains = <&sysc R8A7795_PD_A3VC>; - #iommu-cells = <1>; + i2c4: i2c@e66d8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 927>; + dmas = <&dmac0 0x99>, <&dmac0 0x98>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; - ipmmu_pv0: mmu@fd800000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; + i2c5: i2c@e66e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 919>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 919>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; - ipmmu_pv1: mmu@fd950000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfd950000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 7>; + i2c6: i2c@e66e8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 918>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 918>; + dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; - ipmmu_pv2: mmu@fd960000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfd960000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 8>; + i2c_dvfs: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7795", + "renesas,rcar-gen3-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 926>; + dmas = <&dmac0 0x11>, <&dmac0 0x10>; + dma-names = "tx", "rx"; status = "disabled"; }; - ipmmu_pv3: mmu@fd970000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xfd970000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 9>; + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a7795", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 520>; status = "disabled"; }; - ipmmu_ir: mmu@ff8b0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xff8b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 3>; - power-domains = <&sysc R8A7795_PD_A3IR>; - #iommu-cells = <1>; + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a7795", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6550000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 519>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 519>; status = "disabled"; }; - ipmmu_hc: mmu@e6570000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a7795", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6560000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 518>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>, + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 518>; status = "disabled"; }; - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 10>; + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a7795", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66a0000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dma-names = "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 517>; status = "disabled"; }; - ipmmu_mp0: mmu@ec670000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; + hscif4: serial@e66b0000 { + compatible = "renesas,hscif-r8a7795", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66b0000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x38>; + dma-names = "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 516>; status = "disabled"; }; - ipmmu_ds0: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7795", + "renesas,rcar-gen3-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0>; + phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 704>; + status = "disabled"; }; - ipmmu_ds1: mmu@e7740000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; + hsusb3: usb@e659c000 { + compatible = "renesas,usbhs-r8a7795", + "renesas,rcar-gen3-usbhs"; + reg = <0 0xe659c000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 705>; + dmas = <&usb_dmac2 0>, <&usb_dmac2 1>, + <&usb_dmac3 0>, <&usb_dmac3 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy3>; + phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 705>; + status = "disabled"; }; - ipmmu_mm: mmu@e67b0000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7795-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7795-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac2: dma-controller@e6460000 { + compatible = "renesas,r8a7795-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe6460000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 326>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 326>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac3: dma-controller@e6470000 { + compatible = "renesas,r8a7795-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe6470000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 329>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 329>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb3_phy0: usb-phy@e65ee000 { + compatible = "renesas,r8a7795-usb3-phy", + "renesas,rcar-gen3-usb3-phy"; + reg = <0 0xe65ee000 0 0x90>; + clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, + <&usb_extal_clk>; + clock-names = "usb3-if", "usb3s_clk", "usb_extal"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 328>; + #phy-cells = <0>; + status = "disabled"; }; dmac0: dma-controller@e6700000 { @@ -756,154 +931,207 @@ <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; }; - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7795", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; + ipmmu_ds0: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xe6740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>, - <&ipmmu_mp0 2>, <&ipmmu_mp0 3>, - <&ipmmu_mp0 4>, <&ipmmu_mp0 5>, - <&ipmmu_mp0 6>, <&ipmmu_mp0 7>, - <&ipmmu_mp0 8>, <&ipmmu_mp0 9>, - <&ipmmu_mp0 10>, <&ipmmu_mp0 11>, - <&ipmmu_mp0 12>, <&ipmmu_mp0 13>, - <&ipmmu_mp0 14>, <&ipmmu_mp0 15>; + #iommu-cells = <1>; }; - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7795", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; + ipmmu_ds1: mmu@e7740000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 1>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, - <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, - <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, - <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, - <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, - <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, - <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, - <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; + #iommu-cells = <1>; }; - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7795", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; + ipmmu_hc: mmu@e6570000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xe6570000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 2>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; + #iommu-cells = <1>; }; - can0: can@e6c30000 { - compatible = "renesas,can-r8a7795", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7795_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; - assigned-clock-rates = <40000000>; + ipmmu_ir: mmu@ff8b0000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xff8b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 3>; + power-domains = <&sysc R8A7795_PD_A3IR>; + #iommu-cells = <1>; + }; + + ipmmu_mm: mmu@e67b0000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = , + ; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; + #iommu-cells = <1>; }; - can1: can@e6c38000 { - compatible = "renesas,can-r8a7795", + ipmmu_mp0: mmu@ec670000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xec670000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 4>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv0: mmu@fd800000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfd800000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 6>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv1: mmu@fd950000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfd950000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 7>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv2: mmu@fd960000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfd960000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 8>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv3: mmu@fd970000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfd970000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 9>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xffc80000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 10>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vc0: mmu@fe6b0000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfe6b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 12>; + power-domains = <&sysc R8A7795_PD_A3VC>; + #iommu-cells = <1>; + }; + + ipmmu_vc1: mmu@fe6f0000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfe6f0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 13>; + power-domains = <&sysc R8A7795_PD_A3VC>; + #iommu-cells = <1>; + }; + + ipmmu_vi0: mmu@febd0000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 14>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vi1: mmu@febe0000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfebe0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 15>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vp0: mmu@fe990000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfe990000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 16>; + power-domains = <&sysc R8A7795_PD_A3VP>; + #iommu-cells = <1>; + }; + + ipmmu_vp1: mmu@fe980000 { + compatible = "renesas,ipmmu-r8a7795"; + reg = <0 0xfe980000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 17>; + power-domains = <&sysc R8A7795_PD_A3VP>; + #iommu-cells = <1>; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7795", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 812>; + phy-mode = "rgmii"; + iommus = <&ipmmu_ds0 16>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + can0: can@e6c30000 { + compatible = "renesas,can-r8a7795", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c30000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7795_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6c38000 { + compatible = "renesas,can-r8a7795", "renesas,rcar-gen3-can"; reg = <0 0xe6c38000 0 0x1000>; interrupts = ; @@ -943,211 +1171,173 @@ }; }; - drif00: rif@e6f40000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f40000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 515>; - clock-names = "fck"; - dmas = <&dmac1 0x20>, <&dmac2 0x20>; - dma-names = "rx", "rx"; + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 515>; - renesas,bonding = <&drif01>; + resets = <&cpg 523>; + #pwm-cells = <2>; status = "disabled"; }; - drif01: rif@e6f50000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f50000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 514>; - clock-names = "fck"; - dmas = <&dmac1 0x22>, <&dmac2 0x22>; - dma-names = "rx", "rx"; + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 514>; - renesas,bonding = <&drif00>; + resets = <&cpg 523>; + #pwm-cells = <2>; status = "disabled"; }; - drif10: rif@e6f60000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f60000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 513>; - clock-names = "fck"; - dmas = <&dmac1 0x24>, <&dmac2 0x24>; - dma-names = "rx", "rx"; + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 513>; - renesas,bonding = <&drif11>; + resets = <&cpg 523>; + #pwm-cells = <2>; status = "disabled"; }; - drif11: rif@e6f70000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f70000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 512>; - clock-names = "fck"; - dmas = <&dmac1 0x26>, <&dmac2 0x26>; - dma-names = "rx", "rx"; + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 512>; - renesas,bonding = <&drif10>; + resets = <&cpg 523>; + #pwm-cells = <2>; status = "disabled"; }; - drif20: rif@e6f80000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f80000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 511>; - clock-names = "fck"; - dmas = <&dmac1 0x28>, <&dmac2 0x28>; - dma-names = "rx", "rx"; + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 511>; - renesas,bonding = <&drif21>; + resets = <&cpg 523>; + #pwm-cells = <2>; status = "disabled"; }; - drif21: rif@e6f90000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f90000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 510>; - clock-names = "fck"; - dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 510>; - renesas,bonding = <&drif20>; + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; status = "disabled"; }; - drif30: rif@e6fa0000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fa0000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 509>; - clock-names = "fck"; - dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; - dma-names = "rx", "rx"; + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 509>; - renesas,bonding = <&drif31>; + resets = <&cpg 523>; + #pwm-cells = <2>; status = "disabled"; }; - drif31: rif@e6fb0000 { - compatible = "renesas,r8a7795-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fb0000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 508>; - clock-names = "fck"; - dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; - dma-names = "rx", "rx"; + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7795", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 508>; - renesas,bonding = <&drif30>; + resets = <&cpg 207>; status = "disabled"; }; - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7795", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>, <&cpg CPG_CORE R8A7795_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 520>; + resets = <&cpg 206>; status = "disabled"; }; - hscif1: serial@e6550000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6550000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 519>, + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a7795", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e88000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 310>, <&cpg CPG_CORE R8A7795_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x33>, <&dmac1 0x32>, - <&dmac2 0x33>, <&dmac2 0x32>; + dmas = <&dmac1 0x13>, <&dmac1 0x12>, + <&dmac2 0x13>, <&dmac2 0x12>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 519>; + resets = <&cpg 310>; status = "disabled"; }; - hscif2: serial@e6560000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6560000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 518>, + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a7795", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>, <&cpg CPG_CORE R8A7795_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x35>, <&dmac1 0x34>, - <&dmac2 0x35>, <&dmac2 0x34>; - dma-names = "tx", "rx", "tx", "rx"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 518>; + resets = <&cpg 204>; status = "disabled"; }; - hscif3: serial@e66a0000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66a0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 517>, + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a7795", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>, <&cpg CPG_CORE R8A7795_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; dma-names = "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 517>; + resets = <&cpg 203>; status = "disabled"; }; - hscif4: serial@e66b0000 { - compatible = "renesas,hscif-r8a7795", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe66b0000 0 96>; - interrupts = ; - clocks = <&cpg CPG_MOD 516>, + scif5: serial@e6f30000 { + compatible = "renesas,scif-r8a7795", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6f30000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>, <&cpg CPG_CORE R8A7795_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x39>, <&dmac0 0x38>; - dma-names = "tx", "rx"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, + <&dmac2 0x5b>, <&dmac2 0x5a>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 516>; + resets = <&cpg 202>; status = "disabled"; }; @@ -1213,304 +1403,379 @@ status = "disabled"; }; - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7795"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 207>; + resets = <&cpg 811>; + renesas,id = <0>; status = "disabled"; - }; - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; + port@1 { + #address-cells = <1>; + #size-cells = <0>; - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; + reg = <1>; - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; + vin0csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin0>; + }; + vin0csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin0>; + }; + }; + }; }; - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a7795", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A7795_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7795"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 202>; + resets = <&cpg 810>; + renesas,id = <1>; status = "disabled"; - }; - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7795", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin1csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin1>; + }; + vin1csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin1>; + }; + }; + }; }; - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7795"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; + resets = <&cpg 809>; + renesas,id = <2>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin2csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin2>; + }; + vin2csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin2>; + }; + }; + }; }; - i2c1: i2c@e6508000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a7795"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 808>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; + resets = <&cpg 808>; + renesas,id = <3>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin3csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin3>; + }; + vin3csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin3>; + }; + }; + }; }; - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; + vin4: video@e6ef4000 { + compatible = "renesas,vin-r8a7795"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 807>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; + resets = <&cpg 807>; + renesas,id = <4>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin4csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin4>; + }; + vin4csi41: endpoint@3 { + reg = <3>; + remote-endpoint= <&csi41vin4>; + }; + }; + }; }; - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; + vin5: video@e6ef5000 { + compatible = "renesas,vin-r8a7795"; + reg = <0 0xe6ef5000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 806>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; + resets = <&cpg 806>; + renesas,id = <5>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin5csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin5>; + }; + vin5csi41: endpoint@3 { + reg = <3>; + remote-endpoint= <&csi41vin5>; + }; + }; + }; }; - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 927>; + vin6: video@e6ef6000 { + compatible = "renesas,vin-r8a7795"; + reg = <0 0xe6ef6000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 805>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 927>; - dmas = <&dmac0 0x99>, <&dmac0 0x98>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; + resets = <&cpg 805>; + renesas,id = <6>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin6csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin6>; + }; + vin6csi41: endpoint@3 { + reg = <3>; + remote-endpoint= <&csi41vin6>; + }; + }; + }; }; - i2c5: i2c@e66e0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 919>; + vin7: video@e6ef7000 { + compatible = "renesas,vin-r8a7795"; + reg = <0 0xe6ef7000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 804>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 919>; - dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; + resets = <&cpg 804>; + renesas,id = <7>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin7csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin7>; + }; + vin7csi41: endpoint@3 { + reg = <3>; + remote-endpoint= <&csi41vin7>; + }; + }; + }; }; - i2c6: i2c@e66e8000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7795", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66e8000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 918>; + drif00: rif@e6f40000 { + compatible = "renesas,r8a7795-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f40000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 515>; + clock-names = "fck"; + dmas = <&dmac1 0x20>, <&dmac2 0x20>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 918>; - dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; + resets = <&cpg 515>; + renesas,bonding = <&drif01>; status = "disabled"; }; - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; + drif01: rif@e6f50000 { + compatible = "renesas,r8a7795-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f50000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 514>; + clock-names = "fck"; + dmas = <&dmac1 0x22>, <&dmac2 0x22>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; + resets = <&cpg 514>; + renesas,bonding = <&drif00>; status = "disabled"; }; - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; + drif10: rif@e6f60000 { + compatible = "renesas,r8a7795-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f60000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 513>; + clock-names = "fck"; + dmas = <&dmac1 0x24>, <&dmac2 0x24>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; + resets = <&cpg 513>; + renesas,bonding = <&drif11>; status = "disabled"; }; - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; + drif11: rif@e6f70000 { + compatible = "renesas,r8a7795-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f70000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 512>; + clock-names = "fck"; + dmas = <&dmac1 0x26>, <&dmac2 0x26>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; + resets = <&cpg 512>; + renesas,bonding = <&drif10>; status = "disabled"; }; - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; + drif20: rif@e6f80000 { + compatible = "renesas,r8a7795-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f80000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 511>; + clock-names = "fck"; + dmas = <&dmac1 0x28>, <&dmac2 0x28>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; + resets = <&cpg 511>; + renesas,bonding = <&drif21>; status = "disabled"; }; - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; + drif21: rif@e6f90000 { + compatible = "renesas,r8a7795-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f90000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 510>; + clock-names = "fck"; + dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; + resets = <&cpg 510>; + renesas,bonding = <&drif20>; status = "disabled"; }; - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; + drif30: rif@e6fa0000 { + compatible = "renesas,r8a7795-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6fa0000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 509>; + clock-names = "fck"; + dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; + resets = <&cpg 509>; + renesas,bonding = <&drif31>; status = "disabled"; }; - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 0x8>; - clocks = <&cpg CPG_MOD 523>; + drif31: rif@e6fb0000 { + compatible = "renesas,r8a7795-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6fb0000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 508>; + clock-names = "fck"; + dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 523>; - #pwm-cells = <2>; + resets = <&cpg 508>; + renesas,bonding = <&drif30>; status = "disabled"; }; @@ -1708,201 +1973,172 @@ dma-names = "rx", "tx", "rxu", "txu"; }; }; - }; - - sata: sata@ee300000 { - compatible = "renesas,sata-r8a7795", - "renesas,rcar-gen3-sata"; - reg = <0 0xee300000 0 0x200000>; - interrupts = ; - clocks = <&cpg CPG_MOD 815>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 815>; - status = "disabled"; - iommus = <&ipmmu_hc 2>; - }; - - usb3_phy0: usb-phy@e65ee000 { - compatible = "renesas,r8a7795-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, - <&usb_extal_clk>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 328>; - #phy-cells = <0>; - status = "disabled"; - }; - - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a7795-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 328>; - status = "disabled"; - }; - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7795-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; - }; - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7795-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + port@2 { + reg = <2>; + }; + }; }; - usb_dmac2: dma-controller@e6460000 { - compatible = "renesas,r8a7795-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe6460000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 326>; + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7795", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 326>; + resets = <&cpg 502>; #dma-cells = <1>; - dma-channels = <2>; + dma-channels = <16>; + iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>, + <&ipmmu_mp0 2>, <&ipmmu_mp0 3>, + <&ipmmu_mp0 4>, <&ipmmu_mp0 5>, + <&ipmmu_mp0 6>, <&ipmmu_mp0 7>, + <&ipmmu_mp0 8>, <&ipmmu_mp0 9>, + <&ipmmu_mp0 10>, <&ipmmu_mp0 11>, + <&ipmmu_mp0 12>, <&ipmmu_mp0 13>, + <&ipmmu_mp0 14>, <&ipmmu_mp0 15>; }; - usb_dmac3: dma-controller@e6470000 { - compatible = "renesas,r8a7795-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe6470000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 329>; + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a7795", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 329>; + resets = <&cpg 501>; #dma-cells = <1>; - dma-channels = <2>; - }; - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7795", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 314>; - status = "disabled"; - }; - - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a7795", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 313>; - status = "disabled"; + dma-channels = <16>; + iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, + <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, + <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, + <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, + <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, + <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, + <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, + <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; }; - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a7795", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - max-frequency = <200000000>; + xhci0: usb@ee000000 { + compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 312>; + resets = <&cpg 328>; status = "disabled"; }; - sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a7795", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; + usb3_peri0: usb@ee020000 { + compatible = "renesas,r8a7795-usb3-peri", + "renesas,rcar-gen3-usb3-peri"; + reg = <0 0xee020000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 311>; + resets = <&cpg 328>; status = "disabled"; }; - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a7795", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; + ohci0: usb@ee080000 { + compatible = "generic-ohci"; + reg = <0 0xee080000 0 0x100>; interrupts = ; clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 703>; - #phy-cells = <0>; status = "disabled"; }; - usb2_phy1: usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a7795", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; + ohci1: usb@ee0a0000 { + compatible = "generic-ohci"; + reg = <0 0xee0a0000 0 0x100>; + interrupts = ; clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1>; + phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 702>; - #phy-cells = <0>; status = "disabled"; }; - usb2_phy2: usb-phy@ee0c0200 { - compatible = "renesas,usb2-phy-r8a7795", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0c0200 0 0x700>; + ohci2: usb@ee0c0000 { + compatible = "generic-ohci"; + reg = <0 0xee0c0000 0 0x100>; + interrupts = ; clocks = <&cpg CPG_MOD 701>; + phys = <&usb2_phy2>; + phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 701>; - #phy-cells = <0>; status = "disabled"; }; - usb2_phy3: usb-phy@ee0e0200 { - compatible = "renesas,usb2-phy-r8a7795", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0e0200 0 0x700>; + ohci3: usb@ee0e0000 { + compatible = "generic-ohci"; + reg = <0 0xee0e0000 0 0x100>; interrupts = ; clocks = <&cpg CPG_MOD 700>; + phys = <&usb2_phy3>; + phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 700>; - #phy-cells = <0>; status = "disabled"; }; @@ -1958,88 +2194,129 @@ status = "disabled"; }; - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; + usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a7795", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee080200 0 0x700>; interrupts = ; clocks = <&cpg CPG_MOD 703>; - phys = <&usb2_phy0>; - phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 703>; + #phy-cells = <0>; status = "disabled"; }; - ohci1: usb@ee0a0000 { - compatible = "generic-ohci"; - reg = <0 0xee0a0000 0 0x100>; - interrupts = ; + usb2_phy1: usb-phy@ee0a0200 { + compatible = "renesas,usb2-phy-r8a7795", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0a0200 0 0x700>; clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1>; - phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 702>; + #phy-cells = <0>; status = "disabled"; }; - ohci2: usb@ee0c0000 { - compatible = "generic-ohci"; - reg = <0 0xee0c0000 0 0x100>; - interrupts = ; + usb2_phy2: usb-phy@ee0c0200 { + compatible = "renesas,usb2-phy-r8a7795", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0c0200 0 0x700>; clocks = <&cpg CPG_MOD 701>; - phys = <&usb2_phy2>; - phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 701>; + #phy-cells = <0>; status = "disabled"; }; - ohci3: usb@ee0e0000 { - compatible = "generic-ohci"; - reg = <0 0xee0e0000 0 0x100>; + usb2_phy3: usb-phy@ee0e0200 { + compatible = "renesas,usb2-phy-r8a7795", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0e0200 0 0x700>; interrupts = ; clocks = <&cpg CPG_MOD 700>; - phys = <&usb2_phy3>; - phy-names = "usb"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 700>; + #phy-cells = <0>; status = "disabled"; }; - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7795", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0>; - phy-names = "usb"; + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7795", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee100000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 704>; + resets = <&cpg 314>; status = "disabled"; }; - hsusb3: usb@e659c000 { - compatible = "renesas,usbhs-r8a7795", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe659c000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 705>; - dmas = <&usb_dmac2 0>, <&usb_dmac2 1>, - <&usb_dmac3 0>, <&usb_dmac3 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy3>; - phy-names = "usb"; + sdhi1: sd@ee120000 { + compatible = "renesas,sdhi-r8a7795", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee120000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 705>; + resets = <&cpg 313>; status = "disabled"; }; + sdhi2: sd@ee140000 { + compatible = "renesas,sdhi-r8a7795", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi3: sd@ee160000 { + compatible = "renesas,sdhi-r8a7795", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee160000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + sata: sata@ee300000 { + compatible = "renesas,sata-r8a7795", + "renesas,rcar-gen3-sata"; + reg = <0 0xee300000 0 0x200000>; + interrupts = ; + clocks = <&cpg CPG_MOD 815>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 815>; + status = "disabled"; + iommus = <&ipmmu_hc 2>; + }; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + pciec0: pcie@fe000000 { compatible = "renesas,pcie-r8a7795", "renesas,pcie-rcar-gen3"; @@ -2130,28 +2407,28 @@ reg = <0 0xfe890000 0 0x2000>; interrupts = ; clocks = <&cpg CPG_MOD 820>; - power-domains = <&sysc R8A7795_PD_A3VC>; - resets = <&cpg 820>; - }; - - vspbc: vsp@fe920000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe920000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 624>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 624>; + power-domains = <&sysc R8A7795_PD_A3VC>; + resets = <&cpg 820>; + }; - renesas,fcp = <&fcpvb1>; + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 119>; + renesas,fcp = <&fcpf0>; }; - fcpvb1: fcp@fe92f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe92f000 0 0x200>; - clocks = <&cpg CPG_MOD 606>; + fdp1@fe944000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe944000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 118>; power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 606>; - iommus = <&ipmmu_vp1 7>; + resets = <&cpg 118>; + renesas,fcp = <&fcpf1>; }; fcpf0: fcp@fe950000 { @@ -2172,17 +2449,6 @@ iommus = <&ipmmu_vp1 1>; }; - vspbd: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 626>; - - renesas,fcp = <&fcpvb0>; - }; - fcpvb0: fcp@fe96f000 { compatible = "renesas,fcpv"; reg = <0 0xfe96f000 0 0x200>; @@ -2192,15 +2458,13 @@ iommus = <&ipmmu_vp0 5>; }; - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; + fcpvb1: fcp@fe92f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe92f000 0 0x200>; + clocks = <&cpg CPG_MOD 606>; power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 631>; - - renesas,fcp = <&fcpvi0>; + resets = <&cpg 606>; + iommus = <&ipmmu_vp1 7>; }; fcpvi0: fcp@fe9af000 { @@ -2212,17 +2476,6 @@ iommus = <&ipmmu_vp0 8>; }; - vspi1: vsp@fe9b0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9b0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 630>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 630>; - - renesas,fcp = <&fcpvi1>; - }; - fcpvi1: fcp@fe9bf000 { compatible = "renesas,fcpv"; reg = <0 0xfe9bf000 0 0x200>; @@ -2232,9 +2485,58 @@ iommus = <&ipmmu_vp1 9>; }; + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 603>; + iommus = <&ipmmu_vi0 8>; + }; + + fcpvd1: fcp@fea2f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea2f000 0 0x200>; + clocks = <&cpg CPG_MOD 602>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 602>; + iommus = <&ipmmu_vi0 9>; + }; + + fcpvd2: fcp@fea37000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea37000 0 0x200>; + clocks = <&cpg CPG_MOD 601>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 601>; + iommus = <&ipmmu_vi1 10>; + }; + + vspbd: vsp@fe960000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe960000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 626>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 626>; + + renesas,fcp = <&fcpvb0>; + }; + + vspbc: vsp@fe920000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe920000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 624>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 624>; + + renesas,fcp = <&fcpvb1>; + }; + vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x8000>; + reg = <0 0xfea20000 0 0x5000>; interrupts = ; clocks = <&cpg CPG_MOD 623>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -2243,18 +2545,9 @@ renesas,fcp = <&fcpvd0>; }; - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; - }; - vspd1: vsp@fea28000 { compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x8000>; + reg = <0 0xfea28000 0 0x5000>; interrupts = ; clocks = <&cpg CPG_MOD 622>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -2263,18 +2556,9 @@ renesas,fcp = <&fcpvd1>; }; - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 602>; - iommus = <&ipmmu_vi0 9>; - }; - vspd2: vsp@fea30000 { compatible = "renesas,vsp2"; - reg = <0 0xfea30000 0 0x8000>; + reg = <0 0xfea30000 0 0x5000>; interrupts = ; clocks = <&cpg CPG_MOD 621>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -2283,33 +2567,159 @@ renesas,fcp = <&fcpvd2>; }; - fcpvd2: fcp@fea37000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea37000 0 0x200>; - clocks = <&cpg CPG_MOD 601>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 601>; - iommus = <&ipmmu_vi1 10>; + vspi0: vsp@fe9a0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9a0000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 631>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 631>; + + renesas,fcp = <&fcpvi0>; }; - fdp1@fe940000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe940000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 119>; + vspi1: vsp@fe9b0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9b0000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 630>; power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 119>; - renesas,fcp = <&fcpf0>; + resets = <&cpg 630>; + + renesas,fcp = <&fcpvi1>; }; - fdp1@fe944000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe944000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 118>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 118>; - renesas,fcp = <&fcpf1>; + csi20: csi2@fea80000 { + compatible = "renesas,r8a7795-csi2"; + reg = <0 0xfea80000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi20vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi20>; + }; + csi20vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi20>; + }; + csi20vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi20>; + }; + csi20vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi20>; + }; + csi20vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi20>; + }; + csi20vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi20>; + }; + csi20vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi20>; + }; + csi20vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi20>; + }; + }; + }; + }; + + csi40: csi2@feaa0000 { + compatible = "renesas,r8a7795-csi2"; + reg = <0 0xfeaa0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi40vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi40>; + }; + csi40vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi40>; + }; + csi40vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi40>; + }; + csi40vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi40>; + }; + }; + }; + }; + + csi41: csi2@feab0000 { + compatible = "renesas,r8a7795-csi2"; + reg = <0 0xfeab0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 715>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 715>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi41vin4: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin4csi41>; + }; + csi41vin5: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin5csi41>; + }; + csi41vin6: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin6csi41>; + }; + csi41vin7: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin7csi41>; + }; + }; + }; }; hdmi0: hdmi@fead0000 { @@ -2334,6 +2744,10 @@ port@1 { reg = <1>; }; + port@2 { + /* HDMI sound */ + reg = <2>; + }; }; }; @@ -2359,6 +2773,10 @@ port@1 { reg = <1>; }; + port@2 { + /* HDMI sound */ + reg = <2>; + }; }; }; @@ -2409,38 +2827,12 @@ }; }; - tsc: thermal@e6198000 { - compatible = "renesas,r8a7795-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>, - <0 0xe61a8000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - status = "okay"; + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; }; }; - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 - (GIC_CPU_MASK_SIMPLE(8) | - IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 - (GIC_CPU_MASK_SIMPLE(8) | - IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 - (GIC_CPU_MASK_SIMPLE(8) | - IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 - (GIC_CPU_MASK_SIMPLE(8) | - IRQ_TYPE_LEVEL_LOW)>; - }; - thermal-zones { sensor_thermal1: sensor-thermal1 { polling-delay-passive = <250>; @@ -2450,12 +2842,12 @@ trips { sensor1_passive: sensor1-passive { temperature = <95000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "passive"; }; sensor1_crit: sensor1-crit { temperature = <120000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -2476,12 +2868,12 @@ trips { sensor2_passive: sensor2-passive { temperature = <95000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "passive"; }; sensor2_crit: sensor2-crit { temperature = <120000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -2502,12 +2894,12 @@ trips { sensor3_passive: sensor3-passive { temperature = <95000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "passive"; }; sensor3_crit: sensor3-crit { temperature = <120000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -2521,6 +2913,14 @@ }; }; + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; + /* External USB clocks - can be overridden by the board */ usb3s0_clk: usb3s0 { compatible = "fixed-clock"; diff --git a/arch/arm/dts/r8a7796-salvator-x.dts b/arch/arm/dts/r8a7796-salvator-x.dts index 62aa27dbfd..052d72acc8 100644 --- a/arch/arm/dts/r8a7796-salvator-x.dts +++ b/arch/arm/dts/r8a7796-salvator-x.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source for the Salvator-X board + * Device Tree Source for the Salvator-X board with R-Car M3-W * * Copyright (C) 2016 Renesas Electronics Corp. */ @@ -37,6 +37,11 @@ "dclkin.0", "dclkin.1", "dclkin.2"; }; +&sound_card { + dais = <&rsnd_port0 /* ak4613 */ + &rsnd_port1>; /* HDMI0 */ +}; + &hdmi0 { status = "okay"; @@ -47,9 +52,32 @@ remote-endpoint = <&hdmi0_con>; }; }; + port@2 { + reg = <2>; + dw_hdmi0_snd_in: endpoint { + remote-endpoint = <&rsnd_endpoint1>; + }; + }; }; }; &hdmi0_con { remote-endpoint = <&rcar_dw_hdmi0_out>; }; + +&rcar_sound { + ports { + /* rsnd_port0 is on salvator-common */ + rsnd_port1: port@1 { + rsnd_endpoint1: endpoint { + remote-endpoint = <&dw_hdmi0_snd_in>; + + dai-format = "i2s"; + bitclock-master = <&rsnd_endpoint1>; + frame-master = <&rsnd_endpoint1>; + + playback = <&ssi2>; + }; + }; + }; +}; diff --git a/arch/arm/dts/r8a7796.dtsi b/arch/arm/dts/r8a7796.dtsi index 903fef7284..bf860f06d6 100644 --- a/arch/arm/dts/r8a7796.dtsi +++ b/arch/arm/dts/r8a7796.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for the r8a7796 SoC * - * Copyright (C) 2016 Renesas Electronics Corp. + * Copyright (C) 2016-2017 Renesas Electronics Corp. */ #include @@ -57,6 +57,72 @@ clock-frequency = <0>; }; + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <900000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <900000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <960000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -74,7 +140,7 @@ }; a57_1: cpu@1 { - compatible = "arm,cortex-a57","arm,armv8"; + compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x1>; device_type = "cpu"; power-domains = <&sysc R8A7796_PD_CA57_CPU1>; @@ -97,7 +163,7 @@ }; a53_1: cpu@101 { - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x101>; device_type = "cpu"; power-domains = <&sysc R8A7796_PD_CA53_CPU1>; @@ -108,7 +174,7 @@ }; a53_2: cpu@102 { - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x102>; device_type = "cpu"; power-domains = <&sysc R8A7796_PD_CA53_CPU2>; @@ -119,7 +185,7 @@ }; a53_3: cpu@103 { - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x103>; device_type = "cpu"; power-domains = <&sysc R8A7796_PD_CA53_CPU3>; @@ -158,72 +224,6 @@ clock-frequency = <0>; }; - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1500000000 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1600000000 { - opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - opp-1700000000 { - opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <900000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <960000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - }; - - cluster1_opp: opp_table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - }; - opp-1300000000 { - opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <820000>; - clock-latency-ns = <300000>; - turbo-mode; - }; - }; - /* External PCIe clock - can be overridden by the board */ pcie_bus_clk: pcie_bus { compatible = "fixed-clock"; @@ -231,13 +231,6 @@ clock-frequency = <0>; }; - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, <&a57_1>; - }; - pmu_a53 { compatible = "arm,cortex-a53-pmu"; interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, @@ -247,6 +240,13 @@ interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; }; + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a57_0>, <&a57_1>; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; @@ -266,24 +266,7 @@ #size-cells = <2>; ranges; - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - - wdt0: watchdog@e6020000 { + rwdt: watchdog@e6020000 { compatible = "renesas,r8a7796-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; @@ -418,242 +401,72 @@ reg = <0 0xe6060000 0 0x50c>; }; - ipmmu_vi0: mmu@febd0000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 9>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7796-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; }; - ipmmu_vc0: mmu@fe6b0000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 8>; - power-domains = <&sysc R8A7796_PD_A3VC>; - #iommu-cells = <1>; - status = "disabled"; + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7796-rst"; + reg = <0 0xe6160000 0 0x0200>; }; - ipmmu_pv0: mmu@fd800000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 5>; + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7796-sysc"; + reg = <0 0xe6180000 0 0x0400>; + #power-domain-cells = <1>; + }; + + tsc: thermal@e6198000 { + compatible = "renesas,r8a7796-thermal"; + reg = <0 0xe6198000 0 0x100>, + <0 0xe61a0000 0 0x100>, + <0 0xe61a8000 0 0x100>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 522>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; + resets = <&cpg 522>; + #thermal-sensor-cells = <1>; + status = "okay"; }; - ipmmu_pv1: mmu@fd950000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xfd950000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a7796", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = ; + clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - status = "disabled"; + resets = <&cpg 407>; }; - ipmmu_ir: mmu@ff8b0000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xff8b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 3>; - power-domains = <&sysc R8A7796_PD_A3IR>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_hc: mmu@e6570000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 7>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: mmu@ec670000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds0: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: mmu@e7740000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: mmu@e67b0000 { - compatible = "renesas,ipmmu-r8a7796"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7796-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a7796-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a7796-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a7796", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a7796", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - pwm0: pwm@e6e30000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm1: pwm@e6e31000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e31000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm2: pwm@e6e32000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e32000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm3: pwm@e6e33000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e33000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm4: pwm@e6e34000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e34000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm5: pwm@e6e35000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e35000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - pwm6: pwm@e6e36000 { - compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; - reg = <0 0xe6e36000 0 8>; - #pwm-cells = <2>; - clocks = <&cpg CPG_MOD 523>; - resets = <&cpg 523>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a7796", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <110>; + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7796", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -755,244 +568,37 @@ status = "disabled"; }; - can0: can@e6c30000 { - compatible = "renesas,can-r8a7796", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7796_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; - assigned-clock-rates = <40000000>; + i2c_dvfs: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7796", + "renesas,rcar-gen3-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 916>; + resets = <&cpg 926>; + dmas = <&dmac0 0x11>, <&dmac0 0x10>; + dma-names = "tx", "rx"; status = "disabled"; }; - can1: can@e6c38000 { - compatible = "renesas,can-r8a7796", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A7796_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; - assigned-clock-rates = <40000000>; + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a7796", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 915>; - status = "disabled"; - }; - - canfd: can@e66c0000 { - compatible = "renesas,r8a7796-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A7796_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 914>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - - drif00: rif@e6f40000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f40000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 515>; - clock-names = "fck"; - dmas = <&dmac1 0x20>, <&dmac2 0x20>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 515>; - renesas,bonding = <&drif01>; - status = "disabled"; - }; - - drif01: rif@e6f50000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f50000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 514>; - clock-names = "fck"; - dmas = <&dmac1 0x22>, <&dmac2 0x22>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 514>; - renesas,bonding = <&drif00>; - status = "disabled"; - }; - - drif10: rif@e6f60000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f60000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 513>; - clock-names = "fck"; - dmas = <&dmac1 0x24>, <&dmac2 0x24>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 513>; - renesas,bonding = <&drif11>; - status = "disabled"; - }; - - drif11: rif@e6f70000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f70000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 512>; - clock-names = "fck"; - dmas = <&dmac1 0x26>, <&dmac2 0x26>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 512>; - renesas,bonding = <&drif10>; - status = "disabled"; - }; - - drif20: rif@e6f80000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f80000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 511>; - clock-names = "fck"; - dmas = <&dmac1 0x28>, <&dmac2 0x28>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 511>; - renesas,bonding = <&drif21>; - status = "disabled"; - }; - - drif21: rif@e6f90000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6f90000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 510>; - clock-names = "fck"; - dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 510>; - renesas,bonding = <&drif20>; - status = "disabled"; - }; - - drif30: rif@e6fa0000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fa0000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 509>; - clock-names = "fck"; - dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 509>; - renesas,bonding = <&drif31>; - status = "disabled"; - }; - - drif31: rif@e6fb0000 { - compatible = "renesas,r8a7796-drif", - "renesas,rcar-gen3-drif"; - reg = <0 0xe6fb0000 0 0x64>; - interrupts = ; - clocks = <&cpg CPG_MOD 508>; - clock-names = "fck"; - dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; - dma-names = "rx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 508>; - renesas,bonding = <&drif30>; - status = "disabled"; - }; - - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a7796", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - hscif0: serial@e6540000 { - compatible = "renesas,hscif-r8a7796", - "renesas,rcar-gen3-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 0x60>; - interrupts = ; - clocks = <&cpg CPG_MOD 520>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x31>, <&dmac1 0x30>, - <&dmac2 0x31>, <&dmac2 0x30>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 520>; + resets = <&cpg 520>; status = "disabled"; }; @@ -1066,162 +672,61 @@ status = "disabled"; }; - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7796", + "renesas,rcar-gen3-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0>; + phy-names = "usb"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 207>; + resets = <&cpg 704>; status = "disabled"; }; - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7796-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 206>; - status = "disabled"; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; }; - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 204>; - status = "disabled"; - }; - - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 203>; - status = "disabled"; - }; - - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a7796", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE R8A7796_CLK_S3D1>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 202>; - status = "disabled"; - }; - - msiof0: spi@e6e90000 { - compatible = "renesas,msiof-r8a7796", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6e90000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 211>; - dmas = <&dmac1 0x41>, <&dmac1 0x40>, - <&dmac2 0x41>, <&dmac2 0x40>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 211>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof1: spi@e6ea0000 { - compatible = "renesas,msiof-r8a7796", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6ea0000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 210>; - dmas = <&dmac1 0x43>, <&dmac1 0x42>, - <&dmac2 0x43>, <&dmac2 0x42>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 210>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - msiof2: spi@e6c00000 { - compatible = "renesas,msiof-r8a7796", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c00000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 209>; - dmas = <&dmac0 0x45>, <&dmac0 0x44>; - dma-names = "tx", "rx"; + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7796-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 209>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; }; - msiof3: spi@e6c10000 { - compatible = "renesas,msiof-r8a7796", - "renesas,rcar-gen3-msiof"; - reg = <0 0xe6c10000 0 0x0064>; - interrupts = ; - clocks = <&cpg CPG_MOD 208>; - dmas = <&dmac0 0x47>, <&dmac0 0x46>; - dma-names = "tx", "rx"; + usb3_phy0: usb-phy@e65ee000 { + compatible = "renesas,r8a7796-usb3-phy", + "renesas,rcar-gen3-usb3-phy"; + reg = <0 0xe65ee000 0 0x90>; + clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, + <&usb_extal_clk>; + clock-names = "usb3-if", "usb3s_clk", "usb_extal"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 208>; - #address-cells = <1>; - #size-cells = <0>; + resets = <&cpg 328>; + #phy-cells = <0>; status = "disabled"; }; @@ -1351,306 +856,803 @@ <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; }; - audma0: dma-controller@ec700000 { - compatible = "renesas,dmac-r8a7796", - "renesas,rcar-dmac"; - reg = <0 0xec700000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 502>; - clock-names = "fck"; + ipmmu_ds0: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xe6740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 502>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, - <&ipmmu_mp 2>, <&ipmmu_mp 3>, - <&ipmmu_mp 4>, <&ipmmu_mp 5>, - <&ipmmu_mp 6>, <&ipmmu_mp 7>, - <&ipmmu_mp 8>, <&ipmmu_mp 9>, - <&ipmmu_mp 10>, <&ipmmu_mp 11>, - <&ipmmu_mp 12>, <&ipmmu_mp 13>, - <&ipmmu_mp 14>, <&ipmmu_mp 15>; + #iommu-cells = <1>; }; - audma1: dma-controller@ec720000 { - compatible = "renesas,dmac-r8a7796", - "renesas,rcar-dmac"; - reg = <0 0xec720000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 501>; - clock-names = "fck"; + ipmmu_ds1: mmu@e7740000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 1>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 501>; - #dma-cells = <1>; - dma-channels = <16>; - iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, - <&ipmmu_mp 18>, <&ipmmu_mp 19>, - <&ipmmu_mp 20>, <&ipmmu_mp 21>, - <&ipmmu_mp 22>, <&ipmmu_mp 23>, - <&ipmmu_mp 24>, <&ipmmu_mp 25>, - <&ipmmu_mp 26>, <&ipmmu_mp 27>, - <&ipmmu_mp 28>, <&ipmmu_mp 29>, - <&ipmmu_mp 30>, <&ipmmu_mp 31>; + #iommu-cells = <1>; }; - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7796-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 330>; + ipmmu_hc: mmu@e6570000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xe6570000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 2>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 330>; - #dma-cells = <1>; - dma-channels = <2>; + #iommu-cells = <1>; }; - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,r8a7796-usb-dmac", - "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = ; - interrupt-names = "ch0", "ch1"; - clocks = <&cpg CPG_MOD 331>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 331>; - #dma-cells = <1>; - dma-channels = <2>; + ipmmu_ir: mmu@ff8b0000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xff8b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 3>; + power-domains = <&sysc R8A7796_PD_A3IR>; + #iommu-cells = <1>; }; - hsusb: usb@e6590000 { - compatible = "renesas,usbhs-r8a7796", - "renesas,rcar-gen3-usbhs"; - reg = <0 0xe6590000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 704>; - dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, - <&usb_dmac1 0>, <&usb_dmac1 1>; - dma-names = "ch0", "ch1", "ch2", "ch3"; - renesas,buswait = <11>; - phys = <&usb2_phy0>; - phy-names = "usb"; + ipmmu_mm: mmu@e67b0000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = , + ; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mp: mmu@ec670000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xec670000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 4>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv0: mmu@fd800000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xfd800000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 5>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv1: mmu@fd950000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xfd950000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 6>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xffc80000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 7>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vc0: mmu@fe6b0000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xfe6b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 8>; + power-domains = <&sysc R8A7796_PD_A3VC>; + #iommu-cells = <1>; + }; + + ipmmu_vi0: mmu@febd0000 { + compatible = "renesas,ipmmu-r8a7796"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 9>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7796", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 812>; + phy-mode = "rgmii"; + iommus = <&ipmmu_ds0 16>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + can0: can@e6c30000 { + compatible = "renesas,can-r8a7796", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c30000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7796_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6c38000 { + compatible = "renesas,can-r8a7796", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c38000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7796_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + canfd: can@e66c0000 { + compatible = "renesas,r8a7796-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A7796_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e88000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scif5: serial@e6f30000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6f30000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, + <&dmac2 0x5b>, <&dmac2 0x5a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a7796", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 211>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a7796", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a7796", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 209>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 209>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a7796", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7796"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 811>; + renesas,id = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin0csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin0>; + }; + vin0csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin0>; + }; + }; + }; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7796"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 704>; + resets = <&cpg 810>; + renesas,id = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin1csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin1>; + }; + vin1csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin1>; + }; + }; + }; }; - usb3_phy0: usb-phy@e65ee000 { - compatible = "renesas,r8a7796-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, - <&usb_extal_clk>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7796"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 328>; - #phy-cells = <0>; + resets = <&cpg 809>; + renesas,id = <2>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin2csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin2>; + }; + vin2csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin2>; + }; + }; + }; }; - xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a7796", - "renesas,rcar-gen3-xhci"; - reg = <0 0xee000000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a7796"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 808>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 328>; + resets = <&cpg 808>; + renesas,id = <3>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin3csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin3>; + }; + vin3csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin3>; + }; + }; + }; }; - usb3_peri0: usb@ee020000 { - compatible = "renesas,r8a7796-usb3-peri", - "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; - interrupts = ; - clocks = <&cpg CPG_MOD 328>; + vin4: video@e6ef4000 { + compatible = "renesas,vin-r8a7796"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 807>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 328>; + resets = <&cpg 807>; + renesas,id = <4>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin4csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin4>; + }; + vin4csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin4>; + }; + }; + }; }; - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - phys = <&usb2_phy0>; - phy-names = "usb"; + vin5: video@e6ef5000 { + compatible = "renesas,vin-r8a7796"; + reg = <0 0xe6ef5000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 806>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 703>; + resets = <&cpg 806>; + renesas,id = <5>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin5csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin5>; + }; + vin5csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin5>; + }; + }; + }; }; - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - phys = <&usb2_phy0>; - phy-names = "usb"; - companion= <&ohci0>; + vin6: video@e6ef6000 { + compatible = "renesas,vin-r8a7796"; + reg = <0 0xe6ef6000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 805>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 703>; + resets = <&cpg 805>; + renesas,id = <6>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin6csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin6>; + }; + vin6csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin6>; + }; + }; + }; + }; + + vin7: video@e6ef7000 { + compatible = "renesas,vin-r8a7796"; + reg = <0 0xe6ef7000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 804>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 804>; + renesas,id = <7>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin7csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin7>; + }; + vin7csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin7>; + }; + }; + }; }; - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a7796", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; + drif00: rif@e6f40000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f40000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 515>; + clock-names = "fck"; + dmas = <&dmac1 0x20>, <&dmac2 0x20>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 703>; - #phy-cells = <0>; + resets = <&cpg 515>; + renesas,bonding = <&drif01>; status = "disabled"; }; - ohci1: usb@ee0a0000 { - compatible = "generic-ohci"; - reg = <0 0xee0a0000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1>; - phy-names = "usb"; + drif01: rif@e6f50000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f50000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 514>; + clock-names = "fck"; + dmas = <&dmac1 0x22>, <&dmac2 0x22>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 702>; + resets = <&cpg 514>; + renesas,bonding = <&drif00>; status = "disabled"; }; - ehci1: usb@ee0a0100 { - compatible = "generic-ehci"; - reg = <0 0xee0a0100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 702>; - phys = <&usb2_phy1>; - phy-names = "usb"; - companion= <&ohci1>; + drif10: rif@e6f60000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f60000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 513>; + clock-names = "fck"; + dmas = <&dmac1 0x24>, <&dmac2 0x24>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 702>; + resets = <&cpg 513>; + renesas,bonding = <&drif11>; status = "disabled"; }; - usb2_phy1: usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a7796", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; - clocks = <&cpg CPG_MOD 702>; + drif11: rif@e6f70000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f70000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 512>; + clock-names = "fck"; + dmas = <&dmac1 0x26>, <&dmac2 0x26>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 702>; - #phy-cells = <0>; + resets = <&cpg 512>; + renesas,bonding = <&drif10>; status = "disabled"; }; - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7796", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee100000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - max-frequency = <200000000>; + drif20: rif@e6f80000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f80000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 511>; + clock-names = "fck"; + dmas = <&dmac1 0x28>, <&dmac2 0x28>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 314>; + resets = <&cpg 511>; + renesas,bonding = <&drif21>; status = "disabled"; }; - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a7796", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee120000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - max-frequency = <200000000>; + drif21: rif@e6f90000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f90000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 510>; + clock-names = "fck"; + dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 313>; + resets = <&cpg 510>; + renesas,bonding = <&drif20>; status = "disabled"; }; - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a7796", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - max-frequency = <200000000>; + drif30: rif@e6fa0000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6fa0000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 509>; + clock-names = "fck"; + dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 312>; + resets = <&cpg 509>; + renesas,bonding = <&drif31>; status = "disabled"; }; - sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a7796", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee160000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - max-frequency = <200000000>; + drif31: rif@e6fb0000 { + compatible = "renesas,r8a7796-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6fb0000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 508>; + clock-names = "fck"; + dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; + dma-names = "rx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 311>; + resets = <&cpg 508>; + renesas,bonding = <&drif30>; status = "disabled"; }; - tsc: thermal@e6198000 { - compatible = "renesas,r8a7796-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>, - <0 0xe61a8000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 522>; - #thermal-sensor-cells = <1>; - status = "okay"; - }; - rcar_sound: sound@ec500000 { /* * #sound-dai-cells is required @@ -1845,16 +1847,335 @@ dma-names = "rx", "tx", "rxu", "txu"; }; }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + }; + }; + + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7796", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, + <&ipmmu_mp 2>, <&ipmmu_mp 3>, + <&ipmmu_mp 4>, <&ipmmu_mp 5>, + <&ipmmu_mp 6>, <&ipmmu_mp 7>, + <&ipmmu_mp 8>, <&ipmmu_mp 9>, + <&ipmmu_mp 10>, <&ipmmu_mp 11>, + <&ipmmu_mp 12>, <&ipmmu_mp 13>, + <&ipmmu_mp 14>, <&ipmmu_mp 15>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a7796", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, + <&ipmmu_mp 18>, <&ipmmu_mp 19>, + <&ipmmu_mp 20>, <&ipmmu_mp 21>, + <&ipmmu_mp 22>, <&ipmmu_mp 23>, + <&ipmmu_mp 24>, <&ipmmu_mp 25>, + <&ipmmu_mp 26>, <&ipmmu_mp 27>, + <&ipmmu_mp 28>, <&ipmmu_mp 29>, + <&ipmmu_mp 30>, <&ipmmu_mp 31>; + }; + + xhci0: usb@ee000000 { + compatible = "renesas,xhci-r8a7796", + "renesas,rcar-gen3-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + + usb3_peri0: usb@ee020000 { + compatible = "renesas,r8a7796-usb3-peri", + "renesas,rcar-gen3-usb3-peri"; + reg = <0 0xee020000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + + ohci0: usb@ee080000 { + compatible = "generic-ohci"; + reg = <0 0xee080000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + + ohci1: usb@ee0a0000 { + compatible = "generic-ohci"; + reg = <0 0xee0a0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1>; + phy-names = "usb"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + ehci0: usb@ee080100 { + compatible = "generic-ehci"; + reg = <0 0xee080100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + companion= <&ohci0>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + + ehci1: usb@ee0a0100 { + compatible = "generic-ehci"; + reg = <0 0xee0a0100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1>; + phy-names = "usb"; + companion= <&ohci1>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a7796", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee080200 0 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 703>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb2_phy1: usb-phy@ee0a0200 { + compatible = "renesas,usb2-phy-r8a7796", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0a0200 0 0x700>; + clocks = <&cpg CPG_MOD 702>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 702>; + #phy-cells = <0>; + status = "disabled"; + }; + + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7796", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee100000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: sd@ee120000 { + compatible = "renesas,sdhi-r8a7796", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee120000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 313>; + status = "disabled"; + }; + + sdhi2: sd@ee140000 { + compatible = "renesas,sdhi-r8a7796", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi3: sd@ee160000 { + compatible = "renesas,sdhi-r8a7796", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee160000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 408>; }; pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a7796", + "renesas,pcie-rcar-gen3"; reg = <0 0xfe000000 0 0x80000>; - /* placeholder */ + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; }; pciec1: pcie@ee800000 { + compatible = "renesas,pcie-r8a7796", + "renesas,pcie-rcar-gen3"; reg = <0 0xee800000 0 0x80000>; - /* placeholder */ + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000 + 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000 + 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000 + 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; + + imr-lx4@fe860000 { + compatible = "renesas,r8a7796-imr-lx4", + "renesas,imr-lx4"; + reg = <0 0xfe860000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 823>; + power-domains = <&sysc R8A7796_PD_A3VC>; + resets = <&cpg 823>; + }; + + imr-lx4@fe870000 { + compatible = "renesas,r8a7796-imr-lx4", + "renesas,imr-lx4"; + reg = <0 0xfe870000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 822>; + power-domains = <&sysc R8A7796_PD_A3VC>; + resets = <&cpg 822>; }; fdp1@fe940000 { @@ -1875,17 +2196,6 @@ resets = <&cpg 615>; }; - vspb: vsp@fe960000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe960000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 626>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 626>; - - renesas,fcp = <&fcpvb0>; - }; - fcpvb0: fcp@fe96f000 { compatible = "renesas,fcpv"; reg = <0 0xfe96f000 0 0x200>; @@ -1894,17 +2204,6 @@ resets = <&cpg 607>; }; - vspi0: vsp@fe9a0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9a0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 631>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 631>; - - renesas,fcp = <&fcpvi0>; - }; - fcpvi0: fcp@fe9af000 { compatible = "renesas,fcpv"; reg = <0 0xfe9af000 0 0x200>; @@ -1914,9 +2213,47 @@ iommus = <&ipmmu_vc0 19>; }; + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 603>; + iommus = <&ipmmu_vi0 8>; + }; + + fcpvd1: fcp@fea2f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea2f000 0 0x200>; + clocks = <&cpg CPG_MOD 602>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 602>; + iommus = <&ipmmu_vi0 9>; + }; + + fcpvd2: fcp@fea37000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea37000 0 0x200>; + clocks = <&cpg CPG_MOD 601>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 601>; + iommus = <&ipmmu_vi0 10>; + }; + + vspb: vsp@fe960000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe960000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 626>; + power-domains = <&sysc R8A7796_PD_A3VC>; + resets = <&cpg 626>; + + renesas,fcp = <&fcpvb0>; + }; + vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x8000>; + reg = <0 0xfea20000 0 0x5000>; interrupts = ; clocks = <&cpg CPG_MOD 623>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -1925,18 +2262,9 @@ renesas,fcp = <&fcpvd0>; }; - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; - }; - vspd1: vsp@fea28000 { compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x8000>; + reg = <0 0xfea28000 0 0x5000>; interrupts = ; clocks = <&cpg CPG_MOD 622>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -1945,18 +2273,9 @@ renesas,fcp = <&fcpvd1>; }; - fcpvd1: fcp@fea2f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea2f000 0 0x200>; - clocks = <&cpg CPG_MOD 602>; - power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 602>; - iommus = <&ipmmu_vi0 9>; - }; - vspd2: vsp@fea30000 { compatible = "renesas,vsp2"; - reg = <0 0xfea30000 0 0x8000>; + reg = <0 0xfea30000 0 0x5000>; interrupts = ; clocks = <&cpg CPG_MOD 621>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -1965,13 +2284,126 @@ renesas,fcp = <&fcpvd2>; }; - fcpvd2: fcp@fea37000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea37000 0 0x200>; - clocks = <&cpg CPG_MOD 601>; + vspi0: vsp@fe9a0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9a0000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 631>; + power-domains = <&sysc R8A7796_PD_A3VC>; + resets = <&cpg 631>; + + renesas,fcp = <&fcpvi0>; + }; + + csi20: csi2@fea80000 { + compatible = "renesas,r8a7796-csi2"; + reg = <0 0xfea80000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - resets = <&cpg 601>; - iommus = <&ipmmu_vi0 10>; + resets = <&cpg 714>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi20vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi20>; + }; + csi20vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi20>; + }; + csi20vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi20>; + }; + csi20vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi20>; + }; + csi20vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi20>; + }; + csi20vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi20>; + }; + csi20vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi20>; + }; + csi20vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi20>; + }; + }; + }; + }; + + csi40: csi2@feaa0000 { + compatible = "renesas,r8a7796-csi2"; + reg = <0 0xfeaa0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi40vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi40>; + }; + csi40vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi40>; + }; + csi40vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi40>; + }; + csi40vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi40>; + }; + csi40vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi40>; + }; + csi40vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi40>; + }; + csi40vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi40>; + }; + csi40vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi40>; + }; + }; + + }; }; hdmi0: hdmi@fead0000 { @@ -1996,6 +2428,10 @@ port@1 { reg = <1>; }; + port@2 { + /* HDMI sound */ + reg = <2>; + }; }; }; @@ -2039,35 +2475,12 @@ }; }; - imr-lx4@fe860000 { - compatible = "renesas,r8a7796-imr-lx4", - "renesas,imr-lx4"; - reg = <0 0xfe860000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 823>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 823>; - }; - - imr-lx4@fe870000 { - compatible = "renesas,r8a7796-imr-lx4", - "renesas,imr-lx4"; - reg = <0 0xfe870000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 822>; - power-domains = <&sysc R8A7796_PD_A3VC>; - resets = <&cpg 822>; + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; }; }; - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; - }; - thermal-zones { sensor_thermal1: sensor-thermal1 { polling-delay-passive = <250>; @@ -2077,12 +2490,12 @@ trips { sensor1_passive: sensor1-passive { temperature = <95000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "passive"; }; sensor1_crit: sensor1-crit { temperature = <120000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -2103,12 +2516,12 @@ trips { sensor2_passive: sensor2-passive { temperature = <95000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "passive"; }; sensor2_crit: sensor2-crit { temperature = <120000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -2129,12 +2542,12 @@ trips { sensor3_passive: sensor3-passive { temperature = <95000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "passive"; }; sensor3_crit: sensor3-crit { temperature = <120000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -2148,6 +2561,14 @@ }; }; + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + }; + /* External USB clocks - can be overridden by the board */ usb3s0_clk: usb3s0 { compatible = "fixed-clock"; diff --git a/arch/arm/dts/r8a77965-salvator-x.dts b/arch/arm/dts/r8a77965-salvator-x.dts index 75d890d91d..340a3c72b6 100644 --- a/arch/arm/dts/r8a77965-salvator-x.dts +++ b/arch/arm/dts/r8a77965-salvator-x.dts @@ -19,3 +19,31 @@ reg = <0x0 0x48000000 0x0 0x78000000>; }; }; + +&du { + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 721>, + <&versaclock5 1>, + <&x21_clk>, + <&versaclock5 2>; + clock-names = "du.0", "du.1", "du.3", + "dclkin.0", "dclkin.1", "dclkin.3"; +}; + +&hdmi0 { + status = "okay"; + + ports { + port@1 { + reg = <1>; + rcar_dw_hdmi0_out: endpoint { + remote-endpoint = <&hdmi0_con>; + }; + }; + }; +}; + +&hdmi0_con { + remote-endpoint = <&rcar_dw_hdmi0_out>; +}; diff --git a/arch/arm/dts/r8a77965.dtsi b/arch/arm/dts/r8a77965.dtsi index 84ecb4631f..ef8cdc6a16 100644 --- a/arch/arm/dts/r8a77965.dtsi +++ b/arch/arm/dts/r8a77965.dtsi @@ -8,8 +8,9 @@ * Copyright (C) 2016 Renesas Electronics Corp. */ -#include +#include #include +#include #define CPG_AUDIO_CLK_I 10 @@ -19,12 +20,44 @@ #size-cells = <2>; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; i2c7 = &i2c_dvfs; }; - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; }; cpus { @@ -35,23 +68,23 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; device_type = "cpu"; - power-domains = <&sysc 0>; + power-domains = <&sysc R8A77965_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; }; a57_1: cpu@1 { - compatible = "arm,cortex-a57","arm,armv8"; + compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x1>; device_type = "cpu"; - power-domains = <&sysc 1>; + power-domains = <&sysc R8A77965_PD_CA57_CPU1>; next-level-cache = <&L2_CA57>; enable-method = "psci"; }; L2_CA57: cache-controller-0 { compatible = "cache"; - power-domains = <&sysc 12>; + power-domains = <&sysc R8A77965_PD_CA57_SCU>; cache-unified; cache-level = <2>; }; @@ -71,34 +104,24 @@ clock-frequency = <0>; }; - /* - * The external audio clocks are configured as 0 Hz fixed frequency - * clocks by default. - * Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - audio_clk_b: audio_clk_b { + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a57_0>, + <&a57_1>; }; - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; }; /* External SCIF clock - to be overridden by boards that provide it */ @@ -108,42 +131,6 @@ clock-frequency = <0>; }; - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - /* External USB clocks - can be overridden by the board */ - usb3s0_clk: usb3s0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; - }; - - pmu_a57 { - compatible = "arm,cortex-a57-pmu"; - interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a57_0>, - <&a57_1>; - }; - soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; @@ -151,52 +138,14 @@ #size-cells = <2>; ranges; - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc 32>; - resets = <&cpg 408>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a77965"; - reg = <0 0xe6060000 0 0x50c>; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a77965-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a77965-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a77965-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a77965-wdt", + "renesas,rcar-gen3-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; }; gpio0: gpio@e6050000 { @@ -210,7 +159,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 912>; }; @@ -225,7 +174,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 911>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 911>; }; @@ -240,7 +189,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 910>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 910>; }; @@ -255,7 +204,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 909>; }; @@ -270,7 +219,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 908>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 908>; }; @@ -285,7 +234,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 907>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 907>; }; @@ -300,7 +249,7 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 906>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 906>; }; @@ -315,10 +264,51 @@ #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 905>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 905>; }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a77965"; + reg = <0 0xe6060000 0 0x50c>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a77965-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a77965-rst"; + reg = <0 0xe6160000 0 0x0200>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a77965-sysc"; + reg = <0 0xe6180000 0 0x0400>; + #power-domain-cells = <1>; + }; + + tsc: thermal@e6198000 { + compatible = "renesas,r8a77965-thermal"; + reg = <0 0xe6198000 0 0x100>, + <0 0xe61a0000 0 0x100>, + <0 0xe61a8000 0 0x100>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <1>; + status = "okay"; + }; + intc_ex: interrupt-controller@e61c0000 { compatible = "renesas,intc-ex-r8a77965", "renesas,irqc"; #interrupt-cells = <2>; @@ -331,85 +321,362 @@ GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 407>; }; - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a77965", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc 32>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <16>; + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77965", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; }; - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a77965", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc 32>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <16>; + i2c1: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77965", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; }; - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a77965", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = ; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77965", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77965", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 928>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c4: i2c@e66d8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77965", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 927>; + dmas = <&dmac0 0x99>, <&dmac0 0x98>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c5: i2c@e66e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77965", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 919>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c6: i2c@e66e8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77965", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 918>; + dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c_dvfs: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a77965", + "renesas,rcar-gen3-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 926>; + dmas = <&dmac0 0x11>, <&dmac0 0x10>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a77965", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 520>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a77965", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6550000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 519>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 519>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a77965", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6560000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 518>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>, + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 518>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a77965", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 517>; + status = "disabled"; + }; + + hscif4: serial@e66b0000 { + compatible = "renesas,hscif-r8a77965", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66b0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x38>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 516>; + status = "disabled"; + }; + + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7796", + "renesas,rcar-gen3-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a77965-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a77965-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb3_phy0: usb-phy@e65ee000 { + compatible = "renesas,r8a77965-usb3-phy", + "renesas,rcar-gen3-usb3-phy"; + reg = <0 0xe65ee000 0 0x90>; + clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, + <&usb_extal_clk>; + clock-names = "usb3-if", "usb3s_clk", "usb_extal"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 328>; + #phy-cells = <0>; + status = "disabled"; + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a77965", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + dmac1: dma-controller@e7300000 { + compatible = "renesas,dmac-r8a77965", + "renesas,rcar-dmac"; + reg = <0 0xe7300000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + dmac2: dma-controller@e7310000 { + compatible = "renesas,dmac-r8a77965", + "renesas,rcar-dmac"; + reg = <0 0xe7310000 0 0x10000>; + interrupts = ; clock-names = "fck"; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 217>; #dma-cells = <1>; dma-channels = <16>; }; - scif0: serial@e6e60000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e60000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 207>, - <&cpg CPG_CORE 20>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x51>, <&dmac1 0x50>, - <&dmac2 0x51>, <&dmac2 0x50>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; - resets = <&cpg 207>; - status = "disabled"; + ipmmu_ds0: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xe6740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + #iommu-cells = <1>; }; - scif1: serial@e6e68000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e68000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE 20>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x53>, <&dmac1 0x52>, - <&dmac2 0x53>, <&dmac2 0x52>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; - resets = <&cpg 206>; - status = "disabled"; + ipmmu_ds1: mmu@e7740000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 1>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + #iommu-cells = <1>; }; - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE 20>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - power-domains = <&sysc 32>; - resets = <&cpg 310>; - status = "disabled"; + ipmmu_hc: mmu@e6570000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xe6570000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 2>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + #iommu-cells = <1>; }; - scif3: serial@e6c50000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c50000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 204>, - <&cpg CPG_CORE 20>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x57>, <&dmac0 0x56>; - dma-names = "tx", "rx"; - power-domains = <&sysc 32>; - resets = <&cpg 204>; - status = "disabled"; + ipmmu_ir: mmu@ff8b0000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xff8b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 3>; + power-domains = <&sysc R8A77965_PD_A3IR>; + #iommu-cells = <1>; }; - scif4: serial@e6c40000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6c40000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 203>, - <&cpg CPG_CORE 20>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac0 0x59>, <&dmac0 0x58>; - dma-names = "tx", "rx"; - power-domains = <&sysc 32>; - resets = <&cpg 203>; - status = "disabled"; + ipmmu_mm: mmu@e67b0000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = , + ; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + #iommu-cells = <1>; }; - scif5: serial@e6f30000 { - compatible = "renesas,scif-r8a77965", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6f30000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 202>, - <&cpg CPG_CORE 20>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, - <&dmac2 0x5b>, <&dmac2 0x5a>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc 32>; - resets = <&cpg 202>; - status = "disabled"; + ipmmu_mp: mmu@ec670000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xec670000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 4>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv0: mmu@fd800000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xfd800000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 6>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xffc80000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 10>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vc0: mmu@fe6b0000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xfe6b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 12>; + power-domains = <&sysc R8A77965_PD_A3VC>; + #iommu-cells = <1>; + }; + + ipmmu_vi0: mmu@febd0000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 14>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vp0: mmu@fe990000 { + compatible = "renesas,ipmmu-r8a77965"; + reg = <0 0xfe990000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 16>; + power-domains = <&sysc R8A77965_PD_A3VP>; + #iommu-cells = <1>; }; avb: ethernet@e6800000 { @@ -571,7 +830,7 @@ "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; - power-domains = <&sysc 32>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; #address-cells = <1>; @@ -579,193 +838,981 @@ status = "disabled"; }; - csi20: csi2@fea80000 { - reg = <0 0xfea80000 0 0x10000>; - /* placeholder */ + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a77965", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a77965", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a77965", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e88000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a77965", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a77965", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scif5: serial@e6f30000 { + compatible = "renesas,scif-r8a77965", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6f30000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>, + <&cpg CPG_CORE R8A77965_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, + <&dmac2 0x5b>, <&dmac2 0x5a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a77965", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 211>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a77965", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a77965", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 209>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 209>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a77965", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a77965"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 811>; + renesas,id = <0>; + status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin0csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin0>; + }; + vin0csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin0>; + }; + }; }; }; - csi40: csi2@feaa0000 { - reg = <0 0xfeaa0000 0 0x10000>; - /* placeholder */ + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a77965"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 810>; + renesas,id = <1>; + status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; - }; - }; - vin0: video@e6ef0000 { - reg = <0 0xe6ef0000 0 0x1000>; - /* placeholder */ - }; + port@1 { + #address-cells = <1>; + #size-cells = <0>; - vin1: video@e6ef1000 { - reg = <0 0xe6ef1000 0 0x1000>; - /* placeholder */ + reg = <1>; + + vin1csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin1>; + }; + vin1csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin1>; + }; + }; + }; }; vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a77965"; reg = <0 0xe6ef2000 0 0x1000>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 809>; + renesas,id = <2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin2csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin2>; + }; + vin2csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin2>; + }; + }; + }; }; vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a77965"; reg = <0 0xe6ef3000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 808>; + renesas,id = <3>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin3csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin3>; + }; + vin3csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin3>; + }; + }; + }; + }; + + vin4: video@e6ef4000 { + compatible = "renesas,vin-r8a77965"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 807>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 807>; + renesas,id = <4>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin4csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin4>; + }; + vin4csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin4>; + }; + }; + }; + }; + + vin5: video@e6ef5000 { + compatible = "renesas,vin-r8a77965"; + reg = <0 0xe6ef5000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 806>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 806>; + renesas,id = <5>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin5csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin5>; + }; + vin5csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin5>; + }; + }; + }; + }; + + vin6: video@e6ef6000 { + compatible = "renesas,vin-r8a77965"; + reg = <0 0xe6ef6000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 805>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 805>; + renesas,id = <6>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin6csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin6>; + }; + vin6csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin6>; + }; + }; + }; + }; + + vin7: video@e6ef7000 { + compatible = "renesas,vin-r8a77965"; + reg = <0 0xe6ef7000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 804>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 804>; + renesas,id = <7>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin7csi20: endpoint@0 { + reg = <0>; + remote-endpoint= <&csi20vin7>; + }; + vin7csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin7>; + }; + }; + }; + }; + + rcar_sound: sound@ec500000 { + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ /* placeholder */ + + rcar_sound,dvc { + dvc0: dvc-0 { + }; + dvc1: dvc-1 { + }; + }; + + rcar_sound,src { + src0: src-0 { + }; + src1: src-1 { + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + }; + ssi1: ssi-1 { + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + }; + }; + + xhci0: usb@ee000000 { + compatible = "renesas,xhci-r8a77965", + "renesas,rcar-gen3-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + + usb3_peri0: usb@ee020000 { + compatible = "renesas,r8a77965-usb3-peri", + "renesas,rcar-gen3-usb3-peri"; + reg = <0 0xee020000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + + ohci0: usb@ee080000 { + compatible = "generic-ohci"; + reg = <0 0xee080000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + + ohci1: usb@ee0a0000 { + compatible = "generic-ohci"; + reg = <0 0xee0a0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1>; + phy-names = "usb"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + ehci0: usb@ee080100 { + compatible = "generic-ehci"; + reg = <0 0xee080100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + + ehci1: usb@ee0a0100 { + compatible = "generic-ehci"; + reg = <0 0xee0a0100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a77965", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee080200 0 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 703>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb2_phy1: usb-phy@ee0a0200 { + compatible = "renesas,usb2-phy-r8a77965", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0a0200 0 0x700>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 703>; + #phy-cells = <0>; + status = "disabled"; + }; + + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a77965", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee100000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: sd@ee120000 { + compatible = "renesas,sdhi-r8a77965", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee120000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 313>; + status = "disabled"; + }; + + sdhi2: sd@ee140000 { + compatible = "renesas,sdhi-r8a77965", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi3: sd@ee160000 { + compatible = "renesas,sdhi-r8a77965", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee160000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 408>; }; - vin4: video@e6ef4000 { - reg = <0 0xe6ef4000 0 0x1000>; - /* placeholder */ + pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a77965", + "renesas,pcie-rcar-gen3"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; }; - vin5: video@e6ef5000 { - reg = <0 0xe6ef5000 0 0x1000>; - /* placeholder */ + pciec1: pcie@ee800000 { + compatible = "renesas,pcie-r8a77965", + "renesas,pcie-rcar-gen3"; + reg = <0 0xee800000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000 + 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000 + 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000 + 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; }; - vin6: video@e6ef6000 { - reg = <0 0xe6ef6000 0 0x1000>; - /* placeholder */ + fcpf0: fcp@fe950000 { + compatible = "renesas,fcpf"; + reg = <0 0xfe950000 0 0x200>; + clocks = <&cpg CPG_MOD 615>; + power-domains = <&sysc R8A77965_PD_A3VP>; + resets = <&cpg 615>; }; - vin7: video@e6ef7000 { - reg = <0 0xe6ef7000 0 0x1000>; - /* placeholder */ - }; + vspb: vsp@fe960000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe960000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 626>; + power-domains = <&sysc R8A77965_PD_A3VP>; + resets = <&cpg 626>; - ohci0: usb@ee080000 { - reg = <0 0xee080000 0 0x100>; - /* placeholder */ + renesas,fcp = <&fcpvb0>; }; - ehci0: usb@ee080100 { - reg = <0 0xee080100 0 0x100>; - /* placeholder */ + fcpvb0: fcp@fe96f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe96f000 0 0x200>; + clocks = <&cpg CPG_MOD 607>; + power-domains = <&sysc R8A77965_PD_A3VP>; + resets = <&cpg 607>; }; - usb2_phy0: usb-phy@ee080200 { - reg = <0 0xee080200 0 0x700>; - /* placeholder */ - }; + vspi0: vsp@fe9a0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9a0000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 631>; + power-domains = <&sysc R8A77965_PD_A3VP>; + resets = <&cpg 631>; - usb2_phy1: usb-phy@ee0a0200 { - reg = <0 0xee0a0200 0 0x700>; - /* placeholder */ + renesas,fcp = <&fcpvi0>; }; - ohci1: usb@ee0a0000 { - reg = <0 0xee0a0000 0 0x100>; - /* placeholder */ + fcpvi0: fcp@fe9af000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe9af000 0 0x200>; + clocks = <&cpg CPG_MOD 611>; + power-domains = <&sysc R8A77965_PD_A3VP>; + resets = <&cpg 611>; }; - ehci1: usb@ee0a0100 { - reg = <0 0xee0a0100 0 0x100>; - /* placeholder */ - }; + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x5000>; + interrupts = ; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 623>; - i2c0: i2c@e6500000 { - reg = <0 0xe6500000 0 0x40>; - /* placeholder */ + renesas,fcp = <&fcpvd0>; }; - i2c1: i2c@e6508000 { - reg = <0 0xe6508000 0 0x40>; - /* placeholder */ + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 603>; }; - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x5000>; + interrupts = ; + clocks = <&cpg CPG_MOD 622>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 622>; - reg = <0 0xe6510000 0 0x40>; - /* placeholder */ + renesas,fcp = <&fcpvd1>; }; - i2c3: i2c@e66d0000 { - reg = <0 0xe66d0000 0 0x40>; - /* placeholder */ + fcpvd1: fcp@fea2f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea2f000 0 0x200>; + clocks = <&cpg CPG_MOD 602>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 602>; }; - i2c4: i2c@e66d8000 { - #address-cells = <1>; - #size-cells = <0>; + csi20: csi2@fea80000 { + compatible = "renesas,r8a77965-csi2"; + reg = <0 0xfea80000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; - reg = <0 0xe66d8000 0 0x40>; - /* placeholder */ - }; + ports { + #address-cells = <1>; + #size-cells = <0>; - i2c5: i2c@e66e0000 { - reg = <0 0xe66e0000 0 0x40>; - /* placeholder */ - }; + port@1 { + #address-cells = <1>; + #size-cells = <0>; - i2c6: i2c@e66e8000 { - reg = <0 0xe66e8000 0 0x40>; - /* placeholder */ - }; + reg = <1>; - i2c_dvfs: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,iic-r8a77965", - "renesas,rcar-gen3-iic", - "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x425>; - interrupts = ; - clocks = <&cpg CPG_MOD 926>; - power-domains = <&sysc 32>; - resets = <&cpg 926>; - dmas = <&dmac0 0x11>, <&dmac0 0x10>; - dma-names = "tx", "rx"; - status = "disabled"; + csi20vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi20>; + }; + csi20vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi20>; + }; + csi20vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi20>; + }; + csi20vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi20>; + }; + csi20vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi20>; + }; + csi20vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi20>; + }; + csi20vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi20>; + }; + csi20vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi20>; + }; + }; + }; }; - pwm0: pwm@e6e30000 { - reg = <0 0xe6e30000 0 8>; - /* placeholder */ - }; + csi40: csi2@feaa0000 { + compatible = "renesas,r8a77965-csi2"; + reg = <0 0xfeaa0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; - pwm1: pwm@e6e31000 { - reg = <0 0xe6e31000 0 8>; - #pwm-cells = <2>; - /* placeholder */ - }; + ports { + #address-cells = <1>; + #size-cells = <0>; - pwm2: pwm@e6e32000 { - reg = <0 0xe6e32000 0 8>; - /* placeholder */ - }; + port@1 { + #address-cells = <1>; + #size-cells = <0>; - pwm3: pwm@e6e33000 { - reg = <0 0xe6e33000 0 8>; - /* placeholder */ - }; + reg = <1>; - pwm4: pwm@e6e34000 { - reg = <0 0xe6e34000 0 8>; - /* placeholder */ + csi40vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi40>; + }; + csi40vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi40>; + }; + csi40vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi40>; + }; + csi40vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi40>; + }; + csi40vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi40>; + }; + csi40vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi40>; + }; + csi40vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi40>; + }; + csi40vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi40>; + }; + }; + }; }; - pwm5: pwm@e6e35000 { - reg = <0 0xe6e35000 0 8>; - /* placeholder */ - }; + hdmi0: hdmi@fead0000 { + compatible = "renesas,r8a77965-hdmi", + "renesas,rcar-gen3-hdmi"; + reg = <0 0xfead0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 729>, + <&cpg CPG_CORE R8A77965_CLK_HDMI>; + clock-names = "iahb", "isfr"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 729>; + status = "disabled"; - pwm6: pwm@e6e36000 { - reg = <0 0xe6e36000 0 8>; - /* placeholder */ + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dw_hdmi0_in: endpoint { + remote-endpoint = <&du_out_hdmi0>; + }; + }; + port@1 { + reg = <1>; + }; + }; }; du: display@feb00000 { - reg = <0 0xfeb00000 0 0x80000>, - <0 0xfeb90000 0 0x14>; - /* placeholder */ + compatible = "renesas,du-r8a77965"; + reg = <0 0xfeb00000 0 0x80000>; + reg-names = "du"; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 721>; + clock-names = "du.0", "du.1", "du.3"; + status = "disabled"; + + vsps = <&vspd0 0 &vspd1 0 &vspd0 1>; ports { #address-cells = <1>; @@ -779,6 +1826,7 @@ port@1 { reg = <1>; du_out_hdmi0: endpoint { + remote-endpoint = <&dw_hdmi0_in>; }; }; port@2 { @@ -789,90 +1837,74 @@ }; }; - hsusb: usb@e6590000 { - reg = <0 0xe6590000 0 0x100>; - /* placeholder */ - }; - - pciec0: pcie@fe000000 { - reg = <0 0xfe000000 0 0x80000>; - /* placeholder */ - }; - - pciec1: pcie@ee800000 { - reg = <0 0xee800000 0 0x80000>; - /* placeholder */ + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; }; + }; - rcar_sound: sound@ec500000 { - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ - /* placeholder */ + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; - rcar_sound,dvc { - dvc0: dvc-0 { - }; - dvc1: dvc-1 { + thermal-zones { + sensor_thermal1: sensor-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; }; }; + }; - rcar_sound,src { - src0: src-0 { - }; - src1: src-1 { - }; - }; + sensor_thermal2: sensor-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 1>; - rcar_sound,ssi { - ssi0: ssi-0 { - }; - ssi1: ssi-1 { + trips { + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; }; }; }; - sdhi0: sd@ee100000 { - reg = <0 0xee100000 0 0x2000>; - /* placeholder */ - }; - - sdhi1: sd@ee120000 { - reg = <0 0xee120000 0 0x2000>; - /* placeholder */ - }; - - sdhi2: sd@ee140000 { - reg = <0 0xee140000 0 0x2000>; - /* placeholder */ - }; - - sdhi3: sd@ee160000 { - reg = <0 0xee160000 0 0x2000>; - /* placeholder */ - }; - - usb3_phy0: usb-phy@e65ee000 { - reg = <0 0xe65ee000 0 0x90>; - #phy-cells = <0>; - /* placeholder */ - }; + sensor_thermal3: sensor-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 2>; - usb3_peri0: usb@ee020000 { - reg = <0 0xee020000 0 0x400>; - /* placeholder */ + trips { + sensor3_crit: sensor3-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; }; + }; - xhci0: usb@ee000000 { - reg = <0 0xee000000 0 0xc00>; - /* placeholder */ - }; + /* External USB clocks - can be overridden by the board */ + usb3s0_clk: usb3s0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - wdt0: watchdog@e6020000 { - reg = <0 0xe6020000 0 0x0c>; - /* placeholder */ - }; + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; }; }; diff --git a/arch/arm/dts/r8a77970-eagle.dts b/arch/arm/dts/r8a77970-eagle.dts index 7fee1aa1ac..b6d5332157 100644 --- a/arch/arm/dts/r8a77970-eagle.dts +++ b/arch/arm/dts/r8a77970-eagle.dts @@ -28,9 +28,57 @@ /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x38000000>; }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; + + d3p3: regulator-fixed { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + lvds-decoder { + compatible = "thine,thc63lvd1024"; + + vcc-supply = <&d3p3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + thc63lvd1024_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + + port@2 { + reg = <2>; + thc63lvd1024_out: endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; + }; + }; }; &avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + renesas,no-ether-link; phy-handle = <&phy0>; phy-mode = "rgmii-id"; @@ -44,6 +92,16 @@ }; }; +&canfd { + pinctrl-0 = <&canfd0_pins>; + pinctrl-names = "default"; + status = "okay"; + + channel0 { + status = "okay"; + }; +}; + &extal_clk { clock-frequency = <16666666>; }; @@ -65,9 +123,51 @@ gpio-controller; #gpio-cells = <2>; }; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio1>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&thc63lvd1024_out>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; }; &pfc { + avb_pins: avb0 { + groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; + function = "avb0"; + }; + + canfd0_pins: canfd0 { + groups = "canfd0_data_a"; + function = "canfd0"; + }; + i2c0_pins: i2c0 { groups = "i2c0"; function = "i2c0"; @@ -90,3 +190,19 @@ status = "okay"; }; + +&du { + status = "okay"; +}; + +&lvds0 { + status = "okay"; + + ports { + port@1 { + lvds0_out: endpoint { + remote-endpoint = <&thc63lvd1024_in>; + }; + }; + }; +}; diff --git a/arch/arm/dts/r8a77970.dtsi b/arch/arm/dts/r8a77970.dtsi index 9205da2acd..a0808c90ab 100644 --- a/arch/arm/dts/r8a77970.dtsi +++ b/arch/arm/dts/r8a77970.dtsi @@ -38,6 +38,16 @@ enable-method = "psci"; }; + a53_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <1>; + clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; + power-domains = <&sysc R8A77970_PD_CA53_CPU1>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + L2_CA53: cache-controller { compatible = "cache"; power-domains = <&sysc R8A77970_PD_CA53_SCU>; @@ -60,11 +70,25 @@ clock-frequency = <0>; }; + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a53_0>, <&a53_1>; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; }; + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + /* External SCIF clock - to be overridden by boards that provide it */ scif_clk: scif { compatible = "fixed-clock"; @@ -80,23 +104,6 @@ #size-cells = <2>; ranges; - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1010000 0 0x1000>, - <0 0xf1020000 0 0x20000>, - <0 0xf1040000 0 0x20000>, - <0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - rwdt: watchdog@e6020000 { compatible = "renesas,r8a77970-wdt", "renesas,rcar-gen3-wdt"; @@ -107,75 +114,6 @@ status = "disabled"; }; - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a77970-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a77970-rst"; - reg = <0 0xe6160000 0 0x200>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a77970-sysc"; - reg = <0 0xe6180000 0 0x440>; - #power-domain-cells = <1>; - }; - - ipmmu_vi0: mmu@febd0000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 9>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ir: mmu@ff8b0000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xff8b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 3>; - power-domains = <&sysc R8A77970_PD_A3IR>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 7>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_ds1: mmu@e7740000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_mm: mmu@e67b0000 { - compatible = "renesas,ipmmu-r8a77970"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a77970"; - reg = <0 0xe6060000 0 0x504>; - }; - gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a77970", "renesas,rcar-gen3-gpio"; @@ -266,6 +204,32 @@ resets = <&cpg 907>; }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a77970"; + reg = <0 0xe6060000 0 0x504>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a77970-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a77970-rst"; + reg = <0 0xe6160000 0 0x200>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a77970-sysc"; + reg = <0 0xe6180000 0 0x440>; + #power-domain-cells = <1>; + }; + intc_ex: interrupt-controller@e61c0000 { compatible = "renesas,intc-ex-r8a77970", "renesas,irqc"; #interrupt-cells = <2>; @@ -282,67 +246,6 @@ resets = <&cpg 407>; }; - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a77970", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <8>; - iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, - <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, - <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, - <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a77970", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <8>; - iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, - <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, - <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, - <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; - }; - i2c0: i2c@e6500000 { compatible = "renesas,i2c-r8a77970", "renesas,rcar-gen3-i2c"; @@ -499,6 +402,77 @@ status = "disabled"; }; + canfd: can@e66c0000 { + compatible = "renesas,r8a77970-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A77970_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a77970", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 812>; + phy-mode = "rgmii"; + iommus = <&ipmmu_rt 3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a77970", "renesas,rcar-gen3-scif", @@ -570,57 +544,358 @@ status = "disabled"; }; - avb: ethernet@e6800000 { - compatible = "renesas,etheravb-r8a77970", - "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19", - "ch20", "ch21", "ch22", "ch23", - "ch24"; - clocks = <&cpg CPG_MOD 812>; + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a77970"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; - resets = <&cpg 812>; - phy-mode = "rgmii"; - iommus = <&ipmmu_rt 3>; - #address-cells = <1>; - #size-cells = <0>; + resets = <&cpg 811>; + renesas,id = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin0csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin0>; + }; + }; + }; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a77970"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 810>; + renesas,id = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin1csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin1>; + }; + }; + }; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a77970"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 809>; + renesas,id = <2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin2csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin2>; + }; + }; + }; + }; + + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a77970"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 808>; + renesas,id = <3>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin3csi40: endpoint@2 { + reg = <2>; + remote-endpoint= <&csi40vin3>; + }; + }; + }; + }; + + dmac1: dma-controller@e7300000 { + compatible = "renesas,dmac-r8a77970", + "renesas,rcar-dmac"; + reg = <0 0xe7300000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <8>; + iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, + <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, + <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, + <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; + }; + + dmac2: dma-controller@e7310000 { + compatible = "renesas,dmac-r8a77970", + "renesas,rcar-dmac"; + reg = <0 0xe7310000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7"; + clocks = <&cpg CPG_MOD 217>; + clock-names = "fck"; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 217>; + #dma-cells = <1>; + dma-channels = <8>; + iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, + <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, + <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, + <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; + }; + + ipmmu_ds1: mmu@e7740000 { + compatible = "renesas,ipmmu-r8a77970"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ir: mmu@ff8b0000 { + compatible = "renesas,ipmmu-r8a77970"; + reg = <0 0xff8b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 3>; + power-domains = <&sysc R8A77970_PD_A3IR>; + #iommu-cells = <1>; + }; + + ipmmu_mm: mmu@e67b0000 { + compatible = "renesas,ipmmu-r8a77970"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = , + ; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a77970"; + reg = <0 0xffc80000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 7>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vi0: mmu@febd0000 { + compatible = "renesas,ipmmu-r8a77970"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 9>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1010000 0 0x1000>, + <0 0xf1020000 0 0x20000>, + <0 0xf1040000 0 0x20000>, + <0 0xf1060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x5000>; + interrupts = ; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 623>; + renesas,fcp = <&fcpvd0>; + }; + + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 603>; + }; + + csi40: csi2@feaa0000 { + compatible = "renesas,r8a77970-csi2"; + reg = <0 0xfeaa0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi40vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi40>; + }; + csi40vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi40>; + }; + csi40vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi40>; + }; + csi40vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi40>; + }; + }; + }; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a77970"; + reg = <0 0xfeb00000 0 0x80000>; + interrupts = ; + clocks = <&cpg CPG_MOD 724>; + clock-names = "du.0"; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 724>; + vsps = <&vspd0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + }; + }; + + lvds0: lvds-encoder@feb90000 { + compatible = "renesas,r8a77970-lvds"; + reg = <0 0xfeb90000 0 0x14>; + clocks = <&cpg CPG_MOD 727>; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 727>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = + <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; + }; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; }; }; timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; }; diff --git a/arch/arm/dts/r8a77990-ebisu.dts b/arch/arm/dts/r8a77990-ebisu.dts index e337c902cb..2bc3a4884b 100644 --- a/arch/arm/dts/r8a77990-ebisu.dts +++ b/arch/arm/dts/r8a77990-ebisu.dts @@ -28,72 +28,6 @@ /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x38000000>; }; - - reg_1p8v: regulator0 { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator1 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_sdhi0: regulator-vcc-sdhi0 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1 - 1800000 0>; - }; - - vcc_sdhi1: regulator-vcc-sdhi1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI1 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1 - 1800000 0>; - }; }; &avb { @@ -121,6 +55,10 @@ clock-frequency = <48000000>; }; +&ohci0 { + status = "okay"; +}; + &pfc { avb_pins: avb { mux { @@ -129,71 +67,36 @@ }; }; - usb0_pins: usb0 { - groups = "usb0"; + usb0_pins: usb { + groups = "usb0_b"; function = "usb0"; }; -}; -&usb2_phy0 { - pinctrl-0 = <&usb0_pins>; - pinctrl-name = "default"; - - status = "okay"; + usb30_pins: usb30 { + groups = "usb30"; + function = "usb30"; + }; }; -&sdhi0 { - /* full size SD */ - pinctrl-0 = <&sdhi0_pins>; - pinctrl-1 = <&sdhi0_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; - bus-width = <4>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; +&rwdt { + timeout-sec = <60>; status = "okay"; - max-frequency = <208000000>; }; -&sdhi1 { - /* microSD */ - pinctrl-0 = <&sdhi1_pins>; - pinctrl-1 = <&sdhi1_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi1>; - vqmmc-supply = <&vccq_sdhi1>; - cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>; - bus-width = <4>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; +&scif2 { status = "okay"; - max-frequency = <208000000>; }; -&sdhi3 { - /* used for on-board 8bit eMMC */ - pinctrl-0 = <&sdhi3_pins>; - pinctrl-1 = <&sdhi3_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - bus-width = <8>; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - non-removable; +&usb2_phy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + status = "okay"; }; -&scif2 { +&xhci0 { + pinctrl-0 = <&usb30_pins>; + pinctrl-names = "default"; + status = "okay"; }; diff --git a/arch/arm/dts/r8a77990.dtsi b/arch/arm/dts/r8a77990.dtsi index 593d35a267..ae89260baa 100644 --- a/arch/arm/dts/r8a77990.dtsi +++ b/arch/arm/dts/r8a77990.dtsi @@ -18,16 +18,24 @@ #address-cells = <1>; #size-cells = <0>; - /* 1 core only at this point */ a53_0: cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; - reg = <0x0>; + reg = <0>; device_type = "cpu"; power-domains = <&sysc 5>; next-level-cache = <&L2_CA53>; enable-method = "psci"; }; + a53_1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <1>; + device_type = "cpu"; + power-domains = <&sysc 6>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + L2_CA53: cache-controller-0 { compatible = "cache"; power-domains = <&sysc 21>; @@ -45,8 +53,9 @@ pmu_a53 { compatible = "arm,cortex-a53-pmu"; - interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&a53_0>; + interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a53_0>, <&a53_1>; }; psci { @@ -61,6 +70,16 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a77990-wdt", + "renesas,rcar-gen3-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc 32>; + resets = <&cpg 402>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a77990", "renesas,rcar-gen3-gpio"; @@ -166,43 +185,6 @@ resets = <&cpg 906>; }; - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - phys = <&usb2_phy0>; - phy-names = "usb"; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - }; - - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - phys = <&usb2_phy0>; - phy-names = "usb"; - companion = <&ohci0>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 703>; - status = "disabled"; - }; - - usb2_phy0: usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a7790", - "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; - resets = <&cpg 703>; - #phy-cells = <0>; - status = "disabled"; - }; - pfc: pin-controller@e6060000 { compatible = "renesas,pfc-r8a77990"; reg = <0 0xe6060000 0 0x508>; @@ -229,10 +211,91 @@ #power-domain-cells = <1>; }; + ipmmu_ds0: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xe6740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ds1: mmu@e7740000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 1>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_hc: mmu@e6570000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xe6570000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 2>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mm: mmu@e67b0000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = , + ; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mp: mmu@ec670000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xec670000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 4>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv0: mmu@fd800000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xfd800000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 6>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xffc80000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 10>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vc0: mmu@fe6b0000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xfe6b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 12>; + power-domains = <&sysc R8A77990_PD_A3VC>; + #iommu-cells = <1>; + }; + + ipmmu_vi0: mmu@febd0000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 14>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vp0: mmu@fe990000 { + compatible = "renesas,ipmmu-r8a77990"; + reg = <0 0xfe990000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 16>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + avb: ethernet@e6800000 { compatible = "renesas,etheravb-r8a77990", "renesas,etheravb-rcar-gen3"; - reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; + reg = <0 0xe6800000 0 0x800>; interrupts = , , , @@ -286,6 +349,54 @@ status = "disabled"; }; + xhci0: usb@ee000000 { + compatible = "renesas,xhci-r8a77990", + "renesas,rcar-gen3-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + + ohci0: usb@ee080000 { + compatible = "generic-ohci"; + reg = <0 0xee080000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc 32>; + resets = <&cpg 703>; + status = "disabled"; + }; + + ehci0: usb@ee080100 { + compatible = "generic-ehci"; + reg = <0 0xee080100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&sysc 32>; + resets = <&cpg 703>; + status = "disabled"; + }; + + usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a77990", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee080200 0 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc 32>; + resets = <&cpg 703>; + #phy-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; @@ -296,7 +407,7 @@ <0x0 0xf1040000 0 0x20000>, <0x0 0xf1060000 0 0x20000>; interrupts = ; + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc 32>; @@ -311,9 +422,9 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; }; diff --git a/arch/arm/dts/r8a77995-draak.dts b/arch/arm/dts/r8a77995-draak.dts index 711d487a8e..a8e8f2669d 100644 --- a/arch/arm/dts/r8a77995-draak.dts +++ b/arch/arm/dts/r8a77995-draak.dts @@ -56,6 +56,27 @@ }; }; + composite-in { + compatible = "composite-video-connector"; + + port { + composite_con_in: endpoint { + remote-endpoint = <&adv7180_in>; + }; + }; + }; + + hdmi-in { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&adv7612_in>; + }; + }; + }; + memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ @@ -79,6 +100,12 @@ regulator-boot-on; regulator-always-on; }; + + x12_clk: x12 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <74250000>; + }; }; &extal_clk { @@ -88,7 +115,7 @@ &pfc { avb0_pins: avb { mux { - groups = "avb0_link", "avb0_mdc", "avb0_mii"; + groups = "avb0_link", "avb0_mdio", "avb0_mii"; function = "avb0"; }; }; @@ -139,6 +166,11 @@ groups = "usb0"; function = "usb0"; }; + + vin4_pins_cvbs: vin4 { + groups = "vin4_data8", "vin4_sync", "vin4_clk"; + function = "vin4"; + }; }; &i2c0 { @@ -151,6 +183,77 @@ reg = <0x50>; pagesize = <8>; }; + + composite-in@20 { + compatible = "adi,adv7180cp"; + reg = <0x20>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7180_in: endpoint { + remote-endpoint = <&composite_con_in>; + }; + }; + + port@3 { + reg = <3>; + + /* + * The VIN4 video input path is shared between + * CVBS and HDMI inputs through SW[49-53] + * switches. + * + * CVBS is the default selection, link it to + * VIN4 here. + */ + adv7180_out: endpoint { + remote-endpoint = <&vin4_in>; + }; + }; + }; + + }; + + hdmi-decoder@4c { + compatible = "adi,adv7612"; + reg = <0x4c>; + default-input = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adv7612_in: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; + + port@2 { + reg = <2>; + + /* + * The VIN4 video input path is shared between + * CVBS and HDMI inputs through SW[49-53] + * switches. + * + * CVBS is the default selection, leave HDMI + * not connected here. + */ + adv7612_out: endpoint { + pclk-sample = <0>; + hsync-active = <0>; + vsync-active = <0>; + }; + }; + }; + }; }; &i2c1 { @@ -164,6 +267,11 @@ pinctrl-names = "default"; status = "okay"; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&x12_clk>; + clock-names = "du.0", "du.1", "dclkin.0"; + ports { port@0 { endpoint { @@ -243,3 +351,23 @@ timeout-sec = <60>; status = "okay"; }; + +&vin4 { + pinctrl-0 = <&vin4_pins_cvbs>; + pinctrl-names = "default"; + + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vin4_in: endpoint { + remote-endpoint = <&adv7180_out>; + }; + }; + }; +}; diff --git a/arch/arm/dts/r8a77995.dtsi b/arch/arm/dts/r8a77995.dtsi index d191d8ad70..1efef62182 100644 --- a/arch/arm/dts/r8a77995.dtsi +++ b/arch/arm/dts/r8a77995.dtsi @@ -15,9 +15,11 @@ #address-cells = <2>; #size-cells = <2>; - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; }; cpus { @@ -48,18 +50,16 @@ clock-frequency = <0>; }; - /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - pmu_a53 { compatible = "arm,cortex-a53-pmu"; interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; }; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + scif_clk: scif { compatible = "fixed-clock"; #clock-cells = <0>; @@ -73,23 +73,6 @@ #size-cells = <2>; ranges; - gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xf1010000 0 0x1000>, - <0x0 0xf1020000 0 0x20000>, - <0x0 0xf1040000 0 0x20000>, - <0x0 0xf1060000 0 0x20000>; - interrupts = ; - clocks = <&cpg CPG_MOD 408>; - clock-names = "clk"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 408>; - }; - rwdt: watchdog@e6020000 { compatible = "renesas,r8a77995-wdt", "renesas,rcar-gen3-wdt"; @@ -100,211 +83,9 @@ status = "disabled"; }; - ipmmu_vi0: mmu@febd0000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xfebd0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_vp0: mmu@fe990000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xfe990000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 16>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_vc0: mmu@fe6b0000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xfe6b0000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_pv0: mmu@fd800000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xfd800000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_hc: mmu@e6570000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xe6570000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_rt: mmu@ffc80000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xffc80000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 10>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mp: mmu@ec670000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xec670000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 4>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ds0: mmu@e6740000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xe6740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_ds1: mmu@e7740000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xe7740000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; - #iommu-cells = <1>; - status = "disabled"; - }; - - ipmmu_mm: mmu@e67b0000 { - compatible = "renesas,ipmmu-r8a77995"; - reg = <0 0xe67b0000 0 0x1000>; - interrupts = , - ; - #iommu-cells = <1>; - status = "disabled"; - }; - - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a77995-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>; - clock-names = "extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - rst: reset-controller@e6160000 { - compatible = "renesas,r8a77995-rst"; - reg = <0 0xe6160000 0 0x0200>; - }; - - pfc: pin-controller@e6060000 { - compatible = "renesas,pfc-r8a77995"; - reg = <0 0xe6060000 0 0x508>; - }; - - prr: chipid@fff00044 { - compatible = "renesas,prr"; - reg = <0 0xfff00044 0 4>; - }; - - sysc: system-controller@e6180000 { - compatible = "renesas,r8a77995-sysc"; - reg = <0 0xe6180000 0 0x0400>; - #power-domain-cells = <1>; - }; - - intc_ex: interrupt-controller@e61c0000 { - compatible = "renesas,intc-ex-r8a77995", "renesas,irqc"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; - interrupts = ; - clocks = <&cpg CPG_MOD 407>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 407>; - }; - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a77995", - "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7"; - clocks = <&cpg CPG_MOD 219>; - clock-names = "fck"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 219>; - #dma-cells = <1>; - dma-channels = <8>; - }; - - dmac1: dma-controller@e7300000 { - compatible = "renesas,dmac-r8a77995", - "renesas,rcar-dmac"; - reg = <0 0xe7300000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7"; - clocks = <&cpg CPG_MOD 218>; - clock-names = "fck"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 218>; - #dma-cells = <1>; - dma-channels = <8>; - }; - - dmac2: dma-controller@e7310000 { - compatible = "renesas,dmac-r8a77995", - "renesas,rcar-dmac"; - reg = <0 0xe7310000 0 0x10000>; - interrupts = ; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7"; - clocks = <&cpg CPG_MOD 217>; - clock-names = "fck"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 217>; - #dma-cells = <1>; - dma-channels = <8>; - }; - gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6050000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -319,8 +100,7 @@ gpio1: gpio@e6051000 { compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6051000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -335,8 +115,7 @@ gpio2: gpio@e6052000 { compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6052000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -351,8 +130,7 @@ gpio3: gpio@e6053000 { compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6053000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -367,8 +145,7 @@ gpio4: gpio@e6054000 { compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6054000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -383,8 +160,7 @@ gpio5: gpio@e6055000 { compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6055000 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -399,8 +175,7 @@ gpio6: gpio@e6055400 { compatible = "renesas,gpio-r8a77995", - "renesas,rcar-gen3-gpio", - "renesas,gpio-rcar"; + "renesas,rcar-gen3-gpio"; reg = <0 0xe6055400 0 0x50>; interrupts = ; #gpio-cells = <2>; @@ -413,35 +188,159 @@ resets = <&cpg 906>; }; - can0: can@e6c30000 { - compatible = "renesas,can-r8a77995", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c30000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A77995_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 916>; - status = "disabled"; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a77995"; + reg = <0 0xe6060000 0 0x508>; }; - can1: can@e6c38000 { - compatible = "renesas,can-r8a77995", - "renesas,rcar-gen3-can"; - reg = <0 0xe6c38000 0 0x1000>; - interrupts = ; - clocks = <&cpg CPG_MOD 915>, - <&cpg CPG_CORE R8A77995_CLK_CANFD>, - <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; - assigned-clock-rates = <40000000>; + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a77995-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a77995-rst"; + reg = <0 0xe6160000 0 0x0200>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a77995-sysc"; + reg = <0 0xe6180000 0 0x0400>; + #power-domain-cells = <1>; + }; + + thermal: thermal@e6190000 { + compatible = "renesas,thermal-r8a77995"; + reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 522>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 915>; + resets = <&cpg 522>; + #thermal-sensor-cells = <0>; + }; + + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a77995", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a77995", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE R8A77995_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 520>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a77995", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A77995_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 517>; + status = "disabled"; + }; + + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77995", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77995", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77995", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a77995", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 928>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -470,6 +369,159 @@ }; }; + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a77995", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <8>; + }; + + dmac1: dma-controller@e7300000 { + compatible = "renesas,dmac-r8a77995", + "renesas,rcar-dmac"; + reg = <0 0xe7300000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <8>; + }; + + dmac2: dma-controller@e7310000 { + compatible = "renesas,dmac-r8a77995", + "renesas,rcar-dmac"; + reg = <0 0xe7310000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7"; + clocks = <&cpg CPG_MOD 217>; + clock-names = "fck"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 217>; + #dma-cells = <1>; + dma-channels = <8>; + }; + + ipmmu_ds0: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xe6740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ds1: mmu@e7740000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 1>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_hc: mmu@e6570000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xe6570000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 2>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mm: mmu@e67b0000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = , + ; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mp: mmu@ec670000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xec670000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 4>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv0: mmu@fd800000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xfd800000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 6>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_rt: mmu@ffc80000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xffc80000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 10>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vc0: mmu@fe6b0000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xfe6b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 12>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vi0: mmu@febd0000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 14>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vp0: mmu@fe990000 { + compatible = "renesas,ipmmu-r8a77995"; + reg = <0 0xfe990000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 16>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + avb: ethernet@e6800000 { compatible = "renesas,etheravb-r8a77995", "renesas,etheravb-rcar-gen3"; @@ -509,94 +561,42 @@ clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 812>; - phy-mode = "rgmii"; - iommus = <&ipmmu_ds0 16>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - scif2: serial@e6e88000 { - compatible = "renesas,scif-r8a77995", - "renesas,rcar-gen3-scif", "renesas,scif"; - reg = <0 0xe6e88000 0 64>; - interrupts = ; - clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A77995_CLK_S3D1C>, - <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - dmas = <&dmac1 0x13>, <&dmac1 0x12>, - <&dmac2 0x13>, <&dmac2 0x12>; - dma-names = "tx", "rx", "tx", "rx"; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 310>; - status = "disabled"; - }; - - i2c0: i2c@e6500000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77995", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6500000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 931>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 931>; - dmas = <&dmac1 0x91>, <&dmac1 0x90>, - <&dmac2 0x91>, <&dmac2 0x90>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; - status = "disabled"; - }; - - i2c1: i2c@e6508000 { + phy-mode = "rgmii"; + iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,i2c-r8a77995", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6508000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 930>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 930>; - dmas = <&dmac1 0x93>, <&dmac1 0x92>, - <&dmac2 0x93>, <&dmac2 0x92>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; - i2c2: i2c@e6510000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77995", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe6510000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 929>; + can0: can@e6c30000 { + compatible = "renesas,can-r8a77995", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c30000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A77995_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; + assigned-clock-rates = <40000000>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 929>; - dmas = <&dmac1 0x95>, <&dmac1 0x94>, - <&dmac2 0x95>, <&dmac2 0x94>; - dma-names = "tx", "rx", "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; + resets = <&cpg 916>; status = "disabled"; }; - i2c3: i2c@e66d0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,i2c-r8a77995", - "renesas,rcar-gen3-i2c"; - reg = <0 0xe66d0000 0 0x40>; - interrupts = ; - clocks = <&cpg CPG_MOD 928>; + can1: can@e6c38000 { + compatible = "renesas,can-r8a77995", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c38000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A77995_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; + assigned-clock-rates = <40000000>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 928>; - dmas = <&dmac0 0x97>, <&dmac0 0x96>; - dma-names = "tx", "rx"; - i2c-scl-internal-delay-ns = <6>; + resets = <&cpg 915>; status = "disabled"; }; @@ -640,38 +640,199 @@ status = "disabled"; }; - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a77995", - "renesas,rcar-gen3-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - max-frequency = <200000000>; + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a77995", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE R8A77995_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 312>; + resets = <&cpg 207>; status = "disabled"; }; - ehci0: usb@ee080100 { - compatible = "generic-ehci"; - reg = <0 0xee080100 0 0x100>; + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a77995", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE R8A77995_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a77995", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e88000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A77995_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x13>, <&dmac1 0x12>, + <&dmac2 0x13>, <&dmac2 0x12>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a77995", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE R8A77995_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a77995", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE R8A77995_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scif5: serial@e6f30000 { + compatible = "renesas,scif-r8a77995", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6f30000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>, + <&cpg CPG_CORE R8A77995_CLK_S3D1C>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, + <&dmac2 0x5b>, <&dmac2 0x5a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a77995", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 211>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a77995", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a77995", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 209>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 209>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a77995", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + vin4: video@e6ef4000 { + compatible = "renesas,vin-r8a77995"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 807>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 807>; + renesas,id = <4>; + status = "disabled"; + }; + + ohci0: usb@ee080000 { + compatible = "generic-ohci"; + reg = <0 0xee080000 0 0x100>; interrupts = ; clocks = <&cpg CPG_MOD 703>; phys = <&usb2_phy0>; phy-names = "usb"; - companion = <&ohci0>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 703>; status = "disabled"; }; - ohci0: usb@ee080000 { - compatible = "generic-ohci"; - reg = <0 0xee080000 0 0x100>; + ehci0: usb@ee080100 { + compatible = "generic-ehci"; + reg = <0 0xee080100 0 0x100>; interrupts = ; clocks = <&cpg CPG_MOD 703>; phys = <&usb2_phy0>; phy-names = "usb"; + companion = <&ohci0>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 703>; status = "disabled"; @@ -689,6 +850,35 @@ status = "disabled"; }; + sdhi2: sd@ee140000 { + compatible = "renesas,sdhi-r8a77995", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + vspbs: vsp@fe960000 { compatible = "renesas,vsp2"; reg = <0 0xfe960000 0 0x8000>; @@ -699,18 +889,9 @@ renesas,fcp = <&fcpvb0>; }; - fcpvb0: fcp@fe96f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe96f000 0 0x200>; - clocks = <&cpg CPG_MOD 607>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 607>; - iommus = <&ipmmu_vp0 5>; - }; - vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; - reg = <0 0xfea20000 0 0x8000>; + reg = <0 0xfea20000 0 0x5000>; interrupts = ; clocks = <&cpg CPG_MOD 623>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; @@ -718,18 +899,9 @@ renesas,fcp = <&fcpvd0>; }; - fcpvd0: fcp@fea27000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea27000 0 0x200>; - clocks = <&cpg CPG_MOD 603>; - power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; - resets = <&cpg 603>; - iommus = <&ipmmu_vi0 8>; - }; - vspd1: vsp@fea28000 { compatible = "renesas,vsp2"; - reg = <0 0xfea28000 0 0x8000>; + reg = <0 0xfea28000 0 0x5000>; interrupts = ; clocks = <&cpg CPG_MOD 622>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; @@ -737,6 +909,24 @@ renesas,fcp = <&fcpvd1>; }; + fcpvb0: fcp@fe96f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe96f000 0 0x200>; + clocks = <&cpg CPG_MOD 607>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 607>; + iommus = <&ipmmu_vp0 5>; + }; + + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 603>; + iommus = <&ipmmu_vi0 8>; + }; + fcpvd1: fcp@fea2f000 { compatible = "renesas,fcpv"; reg = <0 0xfea2f000 0 0x200>; @@ -780,6 +970,30 @@ }; }; }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&thermal>; + + trips { + cpu-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; }; timer { diff --git a/arch/arm/dts/salvator-common.dtsi b/arch/arm/dts/salvator-common.dtsi index 2a7f36abd2..7d3d866a00 100644 --- a/arch/arm/dts/salvator-common.dtsi +++ b/arch/arm/dts/salvator-common.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for common parts of Salvator-X board variants * * Copyright (C) 2015-2016 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ /* @@ -36,7 +33,7 @@ / { aliases { serial0 = &scif2; - serial1 = &scif1; + serial1 = &hscif1; ethernet0 = &avb; }; @@ -66,6 +63,29 @@ enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; }; + cvbs-in { + compatible = "composite-video-connector"; + label = "CVBS IN"; + + port { + cvbs_con: endpoint { + remote-endpoint = <&adv7482_ain7>; + }; + }; + }; + + hdmi-in { + compatible = "hdmi-connector"; + label = "HDMI IN"; + type = "a"; + + port { + hdmi_in_con: endpoint { + remote-endpoint = <&adv7482_hdmi>; + }; + }; + }; + reg_1p8v: regulator0 { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; @@ -93,20 +113,12 @@ regulator-always-on; }; - rsnd_ak4613: sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcpu>; - simple-audio-card,frame-master = <&sndcpu>; + sound_card: sound { + compatible = "audio-graph-card"; - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; + label = "rcar-sound"; - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4613>; - }; + dais = <&rsnd_port0>; }; vbus0_usb2: regulator-vbus0-usb2 { @@ -268,6 +280,37 @@ }; }; +&csi20 { + status = "okay"; + + ports { + port@0 { + reg = <0>; + csi20_in: endpoint { + clock-lanes = <0>; + data-lanes = <1>; + remote-endpoint = <&adv7482_txb>; + }; + }; + }; +}; + +&csi40 { + status = "okay"; + + ports { + port@0 { + reg = <0>; + + csi40_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&adv7482_txa>; + }; + }; + }; +}; + &du { pinctrl-0 = <&du_pins>; pinctrl-names = "default"; @@ -295,6 +338,15 @@ clock-frequency = <32768>; }; +&hscif1 { + pinctrl-0 = <&hscif1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + /* Please only enable hscif1 or scif1 */ + status = "okay"; +}; + &hsusb { dr_mode = "otg"; status = "okay"; @@ -322,6 +374,12 @@ asahi-kasei,out4-single-end; asahi-kasei,out5-single-end; asahi-kasei,out6-single-end; + + port { + ak4613_endpoint: endpoint { + remote-endpoint = <&rsnd_endpoint0>; + }; + }; }; cs2000: clk_multiplier@4f { @@ -359,6 +417,55 @@ shunt-resistor-micro-ohms = <5000>; }; + + video-receiver@70 { + compatible = "adi,adv7482"; + reg = <0x70>; + + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&gpio6>; + interrupt-names = "intrq1", "intrq2"; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>, + <31 IRQ_TYPE_LEVEL_LOW>; + + port@7 { + reg = <7>; + + adv7482_ain7: endpoint { + remote-endpoint = <&cvbs_con>; + }; + }; + + port@8 { + reg = <8>; + + adv7482_hdmi: endpoint { + remote-endpoint = <&hdmi_in_con>; + }; + }; + + port@a { + reg = <10>; + + adv7482_txa: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi40_in>; + }; + }; + + port@b { + reg = <11>; + + adv7482_txb: endpoint { + clock-lanes = <0>; + data-lanes = <1>; + remote-endpoint = <&csi20_in>; + }; + }; + }; }; &i2c_dvfs { @@ -376,6 +483,8 @@ #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; + rohm,ddr-backup-power = <0xf>; + rohm,rstbmode-level; regulators { dvfs: dvfs { @@ -387,6 +496,12 @@ }; }; }; + + eeprom@50 { + compatible = "rohm,br24t01", "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + }; }; &ohci0 { @@ -416,12 +531,12 @@ avb_pins: avb { mux { - groups = "avb_link", "avb_mdc", "avb_mii"; + groups = "avb_link", "avb_mdio", "avb_mii"; function = "avb"; }; - pins_mdc { - groups = "avb_mdc"; + pins_mdio { + groups = "avb_mdio"; drive-strength = <24>; }; @@ -437,6 +552,11 @@ function = "du"; }; + hscif1_pins: hscif1 { + groups = "hscif1_data_a", "hscif1_ctrl_a"; + function = "hscif1"; + }; + i2c2_pins: i2c2 { groups = "i2c2_a"; function = "i2c2"; @@ -480,13 +600,13 @@ }; sdhi2_pins: sd2 { - groups = "sdhi2_data8", "sdhi2_ctrl"; + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; function = "sdhi2"; power-source = <3300>; }; sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data8", "sdhi2_ctrl"; + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; function = "sdhi2"; power-source = <1800>; }; @@ -581,10 +701,18 @@ <&audio_clk_c>, <&cpg CPG_CORE CPG_AUDIO_CLK_I>; - rcar_sound,dai { - dai0 { - playback = <&ssi0 &src0 &dvc0>; - capture = <&ssi1 &src1 &dvc1>; + ports { + rsnd_port0: port@0 { + rsnd_endpoint0: endpoint { + remote-endpoint = <&ak4613_endpoint>; + + dai-format = "left_j"; + bitclock-master = <&rsnd_endpoint0>; + frame-master = <&rsnd_endpoint0>; + + playback = <&ssi0 &src0 &dvc0>; + capture = <&ssi1 &src1 &dvc1>; + }; }; }; }; @@ -594,7 +722,8 @@ pinctrl-names = "default"; uart-has-rtscts; - status = "okay"; + /* Please only enable hscif1 or scif1 */ + /* status = "okay"; */ }; &scif2 { @@ -689,7 +818,39 @@ clock-frequency = <100000000>; }; -&wdt0 { +&vin0 { + status = "okay"; +}; + +&vin1 { + status = "okay"; +}; + +&vin2 { + status = "okay"; +}; + +&vin3 { + status = "okay"; +}; + +&vin4 { + status = "okay"; +}; + +&vin5 { + status = "okay"; +}; + +&vin6 { + status = "okay"; +}; + +&vin7 { + status = "okay"; +}; + +&rwdt { timeout-sec = <60>; status = "okay"; }; diff --git a/arch/arm/dts/salvator-x.dtsi b/arch/arm/dts/salvator-x.dtsi index 468868c8ed..ddee50e646 100644 --- a/arch/arm/dts/salvator-x.dtsi +++ b/arch/arm/dts/salvator-x.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the Salvator-X board * * Copyright (C) 2015-2016 Renesas Electronics Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include "salvator-common.dtsi" @@ -20,6 +17,8 @@ }; &i2c4 { + clock-frequency = <400000>; + versaclock5: clock-generator@6a { compatible = "idt,5p49v5923"; reg = <0x6a>; diff --git a/arch/arm/dts/ulcb.dtsi b/arch/arm/dts/ulcb.dtsi index 6f814845f8..0ead552d7e 100644 --- a/arch/arm/dts/ulcb.dtsi +++ b/arch/arm/dts/ulcb.dtsi @@ -1,12 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the R-Car Gen3 ULCB board * * Copyright (C) 2016 Renesas Electronics Corp. * Copyright (C) 2016 Cogent Embedded, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. */ #include @@ -243,6 +240,32 @@ &i2c_dvfs { status = "okay"; + + pmic: pmic@30 { + pinctrl-0 = <&irq0_pins>; + pinctrl-names = "default"; + + compatible = "rohm,bd9571mwv"; + reg = <0x30>; + interrupt-parent = <&intc_ex>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + rohm,ddr-backup-power = <0xf>; + rohm,rstbmode-pulse; + + regulators { + dvfs: dvfs { + regulator-name = "dvfs"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1030000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; }; &ohci1 { @@ -255,12 +278,12 @@ avb_pins: avb { mux { - groups = "avb_link", "avb_mdc", "avb_mii"; + groups = "avb_link", "avb_mdio", "avb_mii"; function = "avb"; }; - pins_mdc { - groups = "avb_mdc"; + pins_mdio { + groups = "avb_mdio"; drive-strength = <24>; }; @@ -276,6 +299,11 @@ function = "i2c2"; }; + irq0_pins: irq0 { + groups = "intc_ex_irq0"; + function = "intc_ex"; + }; + scif2_pins: scif2 { groups = "scif2_data_a"; function = "scif2"; @@ -299,13 +327,13 @@ }; sdhi2_pins: sd2 { - groups = "sdhi2_data8", "sdhi2_ctrl"; + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; function = "sdhi2"; power-source = <3300>; }; sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data8", "sdhi2_ctrl"; + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; function = "sdhi2"; power-source = <1800>; }; @@ -416,7 +444,7 @@ status = "okay"; }; -&wdt0 { +&rwdt { timeout-sec = <60>; status = "okay"; }; -- cgit From 66582cf6da21fe8db0ad186c5613db83fc1879d0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 3 Dec 2018 23:46:11 +0100 Subject: ARM: rmobile: Enable MMC extensions Enable extended MMC commands and GPT partition table support. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- V2: Rebase on u-boot/master --- arch/arm/mach-rmobile/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig index d82023acf3..c6e5f75daf 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-rmobile/Kconfig @@ -13,6 +13,11 @@ config RCAR_GEN3 select ARM64 select PHY select CMD_CACHE + imply CMD_FS_UUID + imply CMD_GPT + imply CMD_UUID + imply CMD_MMC_SWRITE if MMC + imply SUPPORT_EMMC_RPMB if MMC endchoice -- cgit From 00e4b57e9e71c30da9bd6ef6edf6ef035d70924b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 3 Dec 2018 13:28:25 +0100 Subject: ARM: rmobile: Set environment variable containing CPU type Set environment variable 'platform' containing the CPU type. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- arch/arm/Kconfig | 1 + arch/arm/mach-rmobile/cpu_info.c | 41 +++++++++++++++++++++++++++++++--------- 2 files changed, 33 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index eb6ce299f0..13ba774a48 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -784,6 +784,7 @@ config ARCH_RMOBILE imply CMD_DM imply FAT_WRITE imply SYS_THUMB_BUILD + imply ARCH_MISC_INIT if DISPLAY_CPUINFO config TARGET_S32V234EVB bool "Support s32v234evb" diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index c9ebc9f40e..65a9ca8c01 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -5,6 +5,7 @@ */ #include #include +#include /* R-Car Gen3 caches are enabled in memmap-gen3.c */ #ifndef CONFIG_RCAR_GEN3 @@ -67,19 +68,41 @@ static const struct { { 0x0, "CPU" }, }; -int print_cpuinfo(void) +static int rmobile_cpuinfo_idx(void) { int i = 0; u32 cpu_type = rmobile_get_cpu_type(); - for (; i < ARRAY_SIZE(rmobile_cpuinfo); i++) { - if (rmobile_cpuinfo[i].cpu_type == cpu_type) { - printf("CPU: Renesas Electronics %s rev %d.%d\n", - rmobile_cpuinfo[i].cpu_name, - rmobile_get_cpu_rev_integer(), - rmobile_get_cpu_rev_fraction()); + + for (; i < ARRAY_SIZE(rmobile_cpuinfo); i++) + if (rmobile_cpuinfo[i].cpu_type == cpu_type) break; - } - } + + return i; +} + +#ifdef CONFIG_ARCH_MISC_INIT +int arch_misc_init(void) +{ + int i, idx = rmobile_cpuinfo_idx(); + char cpu[10] = { 0 }; + + for (i = 0; i < sizeof(cpu); i++) + cpu[i] = tolower(rmobile_cpuinfo[idx].cpu_name[i]); + + env_set("platform", cpu); + + return 0; +} +#endif + +int print_cpuinfo(void) +{ + int i = rmobile_cpuinfo_idx(); + + printf("CPU: Renesas Electronics %s rev %d.%d\n", + rmobile_cpuinfo[i].cpu_name, rmobile_get_cpu_rev_integer(), + rmobile_get_cpu_rev_fraction()); + return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ -- cgit