From c218f85ea18d57beecc36a3460f08e929d81fcd6 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 30 Mar 2015 17:01:04 -0500 Subject: arm: socfpga: add functions to bring sdram, timer, and uart out of reset These functions will be needed for use by the SPL for enabling the console and sdram initialization. Signed-off-by: Dinh Nguyen Acked-by: Marek Vasut Acked-by: Pavel Machek --- arch/arm/cpu/armv7/socfpga/reset_manager.c | 24 +++++++++++++++++++++++ arch/arm/include/asm/arch-socfpga/reset_manager.h | 6 ++++++ 2 files changed, 30 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c index 25921e76c4..45b352bdfc 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -113,3 +113,27 @@ void socfpga_spim_enable(void) clrbits_le32(reset, (1 << RSTMGR_PERMODRST_SPIM0_LSB) | (1 << RSTMGR_PERMODRST_SPIM1_LSB)); } + +/* Bring UART0 out of reset. */ +void socfpga_uart0_enable(void) +{ + const void *reset = &reset_manager_base->per_mod_reset; + + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_UART0_LSB); +} + +/* Bring SDRAM controller out of reset. */ +void socfpga_sdram_enable(void) +{ + const void *reset = &reset_manager_base->per_mod_reset; + + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SDR_LSB); +} + +/* Bring OSC1 timer out of reset. */ +void socfpga_osc1timer_enable(void) +{ + const void *reset = &reset_manager_base->per_mod_reset; + + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_OSC1TIMER0_LSB); +} diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h index 034135bff4..d63a285091 100644 --- a/arch/arm/include/asm/arch-socfpga/reset_manager.h +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -15,6 +15,9 @@ void socfpga_bridges_reset(int enable); void socfpga_emac_reset(int enable); void socfpga_watchdog_reset(void); void socfpga_spim_enable(void); +void socfpga_uart0_enable(void); +void socfpga_sdram_enable(void); +void socfpga_osc1timer_enable(void); struct socfpga_reset_manager { u32 status; @@ -36,7 +39,10 @@ struct socfpga_reset_manager { #define RSTMGR_PERMODRST_EMAC0_LSB 0 #define RSTMGR_PERMODRST_EMAC1_LSB 1 #define RSTMGR_PERMODRST_L4WD0_LSB 6 +#define RSTMGR_PERMODRST_OSC1TIMER0_LSB 8 +#define RSTMGR_PERMODRST_UART0_LSB 16 #define RSTMGR_PERMODRST_SPIM0_LSB 18 #define RSTMGR_PERMODRST_SPIM1_LSB 19 +#define RSTMGR_PERMODRST_SDR_LSB 29 #endif /* _RESET_MANAGER_H_ */ -- cgit From 0812a1d3e5d056b012d6a9b4b2e83469440f7018 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 30 Mar 2015 17:01:05 -0500 Subject: arm: socfpga: spl: enable sdram, timer and uart Add the calls in the spl_board_init to enable SDRAM, timer, and UART. Signed-off-by: Dinh Nguyen Acked-by: Marek Vasut --- arch/arm/cpu/armv7/socfpga/spl.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 6a8c15d91f..a4dbe4ffe6 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -144,6 +144,10 @@ void spl_board_init(void) /* freeze all IO banks */ sys_mgr_frzctrl_freeze_req(); + socfpga_sdram_enable(); + socfpga_uart0_enable(); + socfpga_osc1timer_enable(); + debug("Reconfigure Clock Manager\n"); /* reconfigure the PLLs */ cm_basic_init(&cm_default_cfg); -- cgit From 9fd565dbe7eadc9736c496bc67f2a0414b50069f Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 30 Mar 2015 17:01:06 -0500 Subject: arm: socfpga: spl: Add call to timer_init Signed-off-by: Dinh Nguyen --- arch/arm/cpu/armv7/socfpga/spl.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index a4dbe4ffe6..95992f0d79 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -148,6 +148,8 @@ void spl_board_init(void) socfpga_uart0_enable(); socfpga_osc1timer_enable(); + timer_init(); + debug("Reconfigure Clock Manager\n"); /* reconfigure the PLLs */ cm_basic_init(&cm_default_cfg); -- cgit From 08e463ee8a7a5641e191be2a8e934d8284d1ca55 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 30 Mar 2015 17:01:07 -0500 Subject: arm: socfpga: spl: allow bootrom to enable IOs after warm reset Signed-off-by: Dinh Nguyen Acked-by: Marek Vasut --- arch/arm/cpu/armv7/socfpga/spl.c | 3 +++ arch/arm/cpu/armv7/socfpga/system_manager.c | 9 +++++++++ arch/arm/include/asm/arch-socfpga/system_manager.h | 1 + 3 files changed, 13 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 95992f0d79..787ad7fb0d 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -154,6 +154,9 @@ void spl_board_init(void) /* reconfigure the PLLs */ cm_basic_init(&cm_default_cfg); + /* Enable bootrom to configure IOs. */ + sysmgr_enable_warmrstcfgio(); + /* configure the IOCSR / IO buffer settings */ if (scan_mgr_configure_iocsr()) hang(); diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c b/arch/arm/cpu/armv7/socfpga/system_manager.c index 11f7badbf2..8126e0d43c 100644 --- a/arch/arm/cpu/armv7/socfpga/system_manager.c +++ b/arch/arm/cpu/armv7/socfpga/system_manager.c @@ -66,3 +66,12 @@ void sysmgr_pinmux_init(void) populate_sysmgr_fpgaintf_module(); } + +/* + * This bit allows the bootrom to configure the IOs after a warm reset. + */ +void sysmgr_enable_warmrstcfgio(void) +{ + setbits_le32(&sysmgr_regs->romcodegrp_ctrl, + SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO); +} diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h b/arch/arm/include/asm/arch-socfpga/system_manager.h index 071ec4f266..51d9815778 100644 --- a/arch/arm/include/asm/arch-socfpga/system_manager.h +++ b/arch/arm/include/asm/arch-socfpga/system_manager.h @@ -10,6 +10,7 @@ #ifndef __ASSEMBLY__ void sysmgr_pinmux_init(void); +void sysmgr_enable_warmrstcfgio(void); /* declaration for handoff table type */ extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM]; -- cgit From 37ef0c70d32c8115bbbb508680fcb65004849126 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 30 Mar 2015 17:01:08 -0500 Subject: arm: socfpga: spl: add sdram init and calibration Add a call to checkboard along with sdram intilialization and calibration. Signed-off-by: Dinh Nguyen --- arch/arm/cpu/armv7/socfpga/spl.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 787ad7fb0d..756c55af91 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -15,6 +15,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -174,4 +175,16 @@ void spl_board_init(void) /* enable console uart printing */ preloader_console_init(); + + if (sdram_mmr_init_full(0xffffffff) != 0) { + puts("SDRAM init failed.\n"); + hang(); + } + + debug("SDRAM: Calibrating PHY\n"); + /* SDRAM calibration */ + if (sdram_calibration_full() == 0) { + puts("SDRAM calibration failed.\n"); + hang(); + } } -- cgit From 89ba82479e7854c5cf42d01cccd1afa81332b717 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 30 Mar 2015 17:01:09 -0500 Subject: arm: socfpga: spl: printout sdram size Signed-off-by: Dinh Nguyen Reviewed-by: Marek Vasut --- arch/arm/cpu/armv7/socfpga/spl.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 756c55af91..e7b4d299b9 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -54,6 +54,7 @@ u32 spl_boot_device(void) */ void spl_board_init(void) { + unsigned long sdram_size; #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET cm_config_t cm_default_cfg = { /* main group */ @@ -187,4 +188,7 @@ void spl_board_init(void) puts("SDRAM calibration failed.\n"); hang(); } + + sdram_size = sdram_calculate_size(); + debug("SDRAM: %ld MiB\n", sdram_size >> 20); } -- cgit From 9cfafc7551ff280fbbac50754c6941ca79675e7b Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 30 Mar 2015 17:01:10 -0500 Subject: arm: socfpga: spl: Use common lowlevel_init For SoCFGPA, use the common ARMv7 lowlevel_init. Thus, we can delete the SoCFPGA lowlevel_init.S file. Signed-off-by: Dinh Nguyen --- arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/socfpga/Makefile | 1 - arch/arm/cpu/armv7/socfpga/lowlevel_init.S | 45 ------------------------------ 3 files changed, 1 insertion(+), 47 deletions(-) delete mode 100644 arch/arm/cpu/armv7/socfpga/lowlevel_init.S (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 21fc03b97e..e6249f13c8 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -12,7 +12,7 @@ obj-y += cache_v7.o obj-y += cpu.o cp15.o obj-y += syslib.o -ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI),) +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_SOCFPGA),) ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y) obj-y += lowlevel_init.o endif diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile index 8b6e108c42..7524ef90e4 100644 --- a/arch/arm/cpu/armv7/socfpga/Makefile +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -7,7 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := lowlevel_init.o obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ fpga_manager.o obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S deleted file mode 100644 index b4d0627871..0000000000 --- a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (C) 2012 Altera Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -/* Set up the platform, once the cpu has been initialized */ -.globl lowlevel_init -lowlevel_init: - - /* Remap */ -#ifdef CONFIG_SPL_BUILD - /* - * SPL : configure the remap (L3 NIC-301 GPV) - * so the on-chip RAM at lower memory instead ROM. - */ - ldr r0, =SOCFPGA_L3REGS_ADDRESS - mov r1, #0x19 - str r1, [r0] -#else - /* - * U-Boot : configure the remap (L3 NIC-301 GPV) - * so the SDRAM at lower memory instead on-chip RAM. - */ - ldr r0, =SOCFPGA_L3REGS_ADDRESS - mov r1, #0x2 - str r1, [r0] - - /* Private components security */ - - /* - * U-Boot : configure private timer, global timer and cpu - * component access as non secure for kernel stage (as required - * by kernel) - */ - mrc p15,4,r0,c15,c0,0 - add r1, r0, #0x54 - ldr r2, [r1] - orr r2, r2, #0xff - orr r2, r2, #0xf00 - str r2, [r1] -#endif /* #ifdef CONFIG_SPL_BUILD */ - mov pc, lr -- cgit From 9ad3a4ace27fc4bd345214e4cb3788710b428db0 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 30 Mar 2015 17:01:15 -0500 Subject: arm: socfpga: spl: Add SDRAM check Signed-off-by: Dinh Nguyen --- arch/arm/cpu/armv7/socfpga/spl.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index e7b4d299b9..d7cedadfc6 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -191,4 +191,10 @@ void spl_board_init(void) sdram_size = sdram_calculate_size(); debug("SDRAM: %ld MiB\n", sdram_size >> 20); + + /* Sanity check ensure correct SDRAM size specified */ + if (get_ram_size(0, sdram_size) != sdram_size) { + puts("SDRAM size check failed!\n"); + hang(); + } } -- cgit From 0ef44d1150cfae5eb5eaea27db129547ac9f1ff7 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 15 Apr 2015 16:44:32 -0500 Subject: arm: socfpga: spl: add board_init_f to SPL Remap SDRAM to 0x0, and clear OCRAM's ECC in board_init_f(). Signed-off-by: Dinh Nguyen Reviewed-by: Marek Vasut --- arch/arm/cpu/armv7/socfpga/spl.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index d7cedadfc6..f994658452 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -19,6 +20,9 @@ DECLARE_GLOBAL_DATA_PTR; +static struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + #define MAIN_VCO_BASE ( \ (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \ CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \ @@ -44,6 +48,31 @@ DECLARE_GLOBAL_DATA_PTR; CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \ ) +void board_init_f(ulong dummy) +{ + struct socfpga_system_manager *sysmgr_regs = + (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; + unsigned long reg; + /* + * First C code to run. Clear fake OCRAM ECC first as SBE + * and DBE might triggered during power on + */ + reg = readl(&sysmgr_regs->eccgrp_ocram); + if (reg & SYSMGR_ECC_OCRAM_SERR) + writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN, + &sysmgr_regs->eccgrp_ocram); + if (reg & SYSMGR_ECC_OCRAM_DERR) + writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN, + &sysmgr_regs->eccgrp_ocram); + + memset(__bss_start, 0, __bss_end - __bss_start); + + /* Remap SDRAM to 0x0 */ + writel(0x1, &pl310->pl310_addr_filter_start); + + board_init_r(NULL, 0); +} + u32 spl_boot_device(void) { return BOOT_DEVICE_RAM; -- cgit From b284d268aff2253b162c636bc63d8fd289159296 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 21 Apr 2015 12:30:09 +0200 Subject: arm: socfpga: spl: Add stub sdram.h Since the SoCFPGA SDRAM support is not yet applied to u-boot, we still need to be able to compile the codebase. Introduce stub functions which temporarily supplement the missing SDRAM setup functions. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Pavel Machek Cc: Stefan Roese Cc: Tom Rini Cc: Vince Bridgers --- arch/arm/include/asm/arch-socfpga/sdram.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 arch/arm/include/asm/arch-socfpga/sdram.h (limited to 'arch/arm') diff --git a/arch/arm/include/asm/arch-socfpga/sdram.h b/arch/arm/include/asm/arch-socfpga/sdram.h new file mode 100644 index 0000000000..4f6489dff6 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/sdram.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2015 Marek Vasut + * + * FIXME: This file contains temporary stub functions and is here + * only until these functions are properly merged into + * mainline. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_SDRAM_H__ +#define __ARCH_SDRAM_H__ + +/* function declaration */ +inline unsigned long sdram_calculate_size(void) { return 0; } +inline unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg) { return 0; } +inline int sdram_calibration_full(void) { return 0; } + +#endif /* __ARCH_SDRAM_H__ */ -- cgit From daa23f5128659929eb139dd5250983770796d068 Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Thu, 23 Apr 2015 09:14:01 +0200 Subject: socfpga: implement socdk SPI flash config in dts SocDK has same QSPI and SPI flash configuration as Socrates. Add support for it. Signed-off-by: Pavel Machek --- arch/arm/dts/socfpga_cyclone5_socdk.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index 8e1f88c2c7..0b300b92be 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -25,6 +25,10 @@ * to be added to the gmac1 device tree blob. */ ethernet0 = &gmac1; + + spi0 = "/spi@ff705000"; /* QSPI */ + spi1 = "/spi@fff00000"; + spi2 = "/spi@fff01000"; }; regulator_3_3v: 3-3-v-regulator { @@ -77,3 +81,23 @@ &usb1 { status = "okay"; }; + +&qspi { + status = "okay"; + + flash0: n25q00@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00"; + reg = <0>; /* chip select */ + spi-max-frequency = <50000000>; + m25p,fast-read; + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + read-delay = <4>; /* delay value in read data capture register */ + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + }; +}; -- cgit From e5c57eea4f4ac8c27343bde137b069ef816e69d7 Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Sat, 25 Apr 2015 21:36:16 +0200 Subject: socfpga: implement arria V socdk SPI flash config in dts Arria V SocDK has same QSPI and SPI flash configuration as Socrates. Add support for it. Signed-off-by: Pavel Machek --- arch/arm/dts/socfpga_arria5_socdk.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts index 4e529a15c3..1b86897872 100644 --- a/arch/arm/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/dts/socfpga_arria5_socdk.dts @@ -25,6 +25,10 @@ * to be added to the gmac1 device tree blob. */ ethernet0 = &gmac1; + + spi0 = "/spi@ff705000"; /* QSPI */ + spi1 = "/spi@fff00000"; + spi2 = "/spi@fff01000"; }; regulator_3_3v: 3-3-v-regulator { @@ -72,3 +76,23 @@ &usb1 { status = "okay"; }; + +&qspi { + status = "okay"; + + flash0: n25q00@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00"; + reg = <0>; /* chip select */ + spi-max-frequency = <50000000>; + m25p,fast-read; + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + read-delay = <4>; /* delay value in read data capture register */ + tshsl-ns = <50>; + tsd2d-ns = <50>; + tchsh-ns = <4>; + tslch-ns = <4>; + }; +}; -- cgit