From 9f2ec3f5431281a480c89107cb952ca5571d78e7 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 23 Apr 2014 21:20:43 +0900 Subject: spl: consolidate arch/arm/include/asm/arch-*/spl.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit arch/arm/include/asm/spl.h requires all SoCs to have arch/arm/include/asm/arch-*/spl.h. But many of them just define BOOT_DEVICE_* macros. Those macros are used in the "switch (boot_device) { ... }" statement in common/spl/spl.c. So they should not be archtecture specific, but be described as a simpile enumeration. This commit merges most of arch/arm/include/asm/arch-*/spl.h into arch/arm/include/asm/spl.h. With a little more effort, arch-zynq/spl.h and arch-socfpga/spl.h will be merged, while I am not sure about OMAP and Exynos. Signed-off-by: Masahiro Yamada Cc: Tom Rini Cc: Michal Simek Cc: Andreas Bießmann Cc: Stephen Warren Cc: Tom Warren CC: Stefano Babic CC: Minkyu Kang Cc: Dinh Nguyen Acked-by: Andreas Bießmann Acked-by: Michal Simek Acked-by: Stefano Babic Acked-by: Stephen Warren Acked-by: Tim Harvey Tested-by: Bo Shen [on sama5d3xek board for at91 part] Acked-by: Stephen Warren Tested-by: Stefano Babic [applying Tim's i.MX6 patches] Acked-by: Tom Rini --- arch/arm/cpu/arm720t/tegra-common/spl.c | 2 +- arch/arm/include/asm/arch-at91/spl.h | 24 ------------------------ arch/arm/include/asm/arch-davinci/spl.h | 16 ---------------- arch/arm/include/asm/arch-mx35/spl.h | 22 ---------------------- arch/arm/include/asm/arch-mx5/spl.h | 13 ------------- arch/arm/include/asm/arch-tegra114/spl.h | 22 ---------------------- arch/arm/include/asm/arch-tegra124/spl.h | 13 ------------- arch/arm/include/asm/arch-tegra20/spl.h | 12 ------------ arch/arm/include/asm/arch-tegra30/spl.h | 12 ------------ arch/arm/include/asm/spl.h | 20 ++++++++++++++++++++ 10 files changed, 21 insertions(+), 135 deletions(-) delete mode 100644 arch/arm/include/asm/arch-at91/spl.h delete mode 100644 arch/arm/include/asm/arch-davinci/spl.h delete mode 100644 arch/arm/include/asm/arch-mx35/spl.h delete mode 100644 arch/arm/include/asm/arch-mx5/spl.h delete mode 100644 arch/arm/include/asm/arch-tegra114/spl.h delete mode 100644 arch/arm/include/asm/arch-tegra124/spl.h delete mode 100644 arch/arm/include/asm/arch-tegra20/spl.h delete mode 100644 arch/arm/include/asm/arch-tegra30/spl.h (limited to 'arch/arm') diff --git a/arch/arm/cpu/arm720t/tegra-common/spl.c b/arch/arm/cpu/arm720t/tegra-common/spl.c index 3479541020..e0f9d5b6b4 100644 --- a/arch/arm/cpu/arm720t/tegra-common/spl.c +++ b/arch/arm/cpu/arm720t/tegra-common/spl.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include "cpu.h" void spl_board_init(void) diff --git a/arch/arm/include/asm/arch-at91/spl.h b/arch/arm/include/asm/arch-at91/spl.h deleted file mode 100644 index d8a87daa4a..0000000000 --- a/arch/arm/include/asm/arch-at91/spl.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (C) 2013 Atmel Corporation - * Bo Shen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -enum { - BOOT_DEVICE_NONE, -#ifdef CONFIG_SYS_USE_MMC - BOOT_DEVICE_MMC1, - BOOT_DEVICE_MMC2, - BOOT_DEVICE_MMC2_2, -#elif CONFIG_SYS_USE_NANDFLASH - BOOT_DEVICE_NAND, -#elif CONFIG_SYS_USE_SERIALFLASH - BOOT_DEVICE_SPI, -#endif -}; - -#endif diff --git a/arch/arm/include/asm/arch-davinci/spl.h b/arch/arm/include/asm/arch-davinci/spl.h deleted file mode 100644 index 5afe0d4ba5..0000000000 --- a/arch/arm/include/asm/arch-davinci/spl.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2012 - * Texas Instruments, - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_NAND 1 -#define BOOT_DEVICE_SPI 2 -#define BOOT_DEVICE_MMC1 3 -#define BOOT_DEVICE_MMC2 4 /* dummy */ -#define BOOT_DEVICE_MMC2_2 5 /* dummy */ - -#endif diff --git a/arch/arm/include/asm/arch-mx35/spl.h b/arch/arm/include/asm/arch-mx35/spl.h deleted file mode 100644 index d0efec21ab..0000000000 --- a/arch/arm/include/asm/arch-mx35/spl.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * (C) Copyright 2012 - * Texas Instruments, - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_NONE 0 -#define BOOT_DEVICE_XIP 1 -#define BOOT_DEVICE_XIPWAIT 2 -#define BOOT_DEVICE_NAND 3 -#define BOOT_DEVICE_ONENAND 4 -#define BOOT_DEVICE_MMC1 5 -#define BOOT_DEVICE_MMC2 6 -#define BOOT_DEVICE_MMC2_2 7 -#define BOOT_DEVICE_NOR 8 -#define BOOT_DEVICE_I2C 9 -#define BOOT_DEVICE_SPI 10 - -#endif diff --git a/arch/arm/include/asm/arch-mx5/spl.h b/arch/arm/include/asm/arch-mx5/spl.h deleted file mode 100644 index 20c6cae938..0000000000 --- a/arch/arm/include/asm/arch-mx5/spl.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (C) 2013 Marek Vasut - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_SPL_H__ -#define __ASM_ARCH_SPL_H__ - -#define BOOT_DEVICE_NONE 0 -#define BOOT_DEVICE_NAND 1 - -#endif /* __ASM_ARCH_SPL_H__ */ diff --git a/arch/arm/include/asm/arch-tegra114/spl.h b/arch/arm/include/asm/arch-tegra114/spl.h deleted file mode 100644 index ebb16fe1dd..0000000000 --- a/arch/arm/include/asm/arch-tegra114/spl.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_RAM 1 - -#endif diff --git a/arch/arm/include/asm/arch-tegra124/spl.h b/arch/arm/include/asm/arch-tegra124/spl.h deleted file mode 100644 index e2663954bf..0000000000 --- a/arch/arm/include/asm/arch-tegra124/spl.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * (C) Copyright 2010-2013 - * NVIDIA Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_RAM 1 - -#endif /* _ASM_ARCH_SPL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/spl.h b/arch/arm/include/asm/arch-tegra20/spl.h deleted file mode 100644 index 8953b00a9f..0000000000 --- a/arch/arm/include/asm/arch-tegra20/spl.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * (C) Copyright 2012 - * NVIDIA Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_RAM 1 - -#endif diff --git a/arch/arm/include/asm/arch-tegra30/spl.h b/arch/arm/include/asm/arch-tegra30/spl.h deleted file mode 100644 index 8953b00a9f..0000000000 --- a/arch/arm/include/asm/arch-tegra30/spl.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * (C) Copyright 2012 - * NVIDIA Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_RAM 1 - -#endif diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index 90e5a9dde1..18a319de2f 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -7,9 +7,29 @@ #ifndef _ASM_SPL_H_ #define _ASM_SPL_H_ +#if defined(CONFIG_OMAP) || defined(CONFIG_SOCFPGA) || defined(CONFIG_ZYNQ) \ + || defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) \ + || defined(CONFIG_EXYNOS4210) /* Platform-specific defines */ #include +#else +enum { + BOOT_DEVICE_RAM, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_MMC2_2, + BOOT_DEVICE_NAND, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_NOR, + BOOT_DEVICE_UART, + BOOT_DEVICE_SPI, + BOOT_DEVICE_SATA, + BOOT_DEVICE_I2C, + BOOT_DEVICE_NONE +}; +#endif + /* Linker symbols. */ extern char __bss_start[], __bss_end[]; -- cgit From 887717dbb91bccfe82aa397b355aa5be4b1cb16a Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 2 Jun 2014 16:13:20 -0700 Subject: mx6: add boot device support for SPL Add a common spl.c file to support boot device functions needed for SPL such as detecting the boot device. Cc: Stefan Roese Cc: Otavio Salvador Cc: Andy Ng Cc: Eric Nelson Cc: Tapani Utriainen Cc: Tom Rini Signed-off-by: Tim Harvey Acked-by: Nikita Kiryanov --- arch/arm/imx-common/Makefile | 1 + arch/arm/imx-common/spl.c | 81 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 82 insertions(+) create mode 100644 arch/arm/imx-common/spl.c (limited to 'arch/arm') diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index 0e713952dc..d4799e7d7b 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o endif ifeq ($(SOC),$(filter $(SOC),mx6 mxs)) obj-y += misc.o +obj-$(CONFIG_SPL_BUILD) += spl.o endif ifeq ($(SOC),$(filter $(SOC),mx6)) obj-$(CONFIG_CMD_SATA) += sata.o diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c new file mode 100644 index 0000000000..9a02a644bc --- /dev/null +++ b/arch/arm/imx-common/spl.c @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. + * + * Author: Tim Harvey + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#if defined(CONFIG_MX6) +/* determine boot device from SRC_SBMR1 register (BOOT_CFG[4:1]) */ +u32 spl_boot_device(void) +{ + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned reg = readl(&psrc->sbmr1); + + /* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */ + switch ((reg & 0x000000FF) >> 4) { + /* EIM: See 8.5.1, Table 8-9 */ + case 0x0: + /* BOOT_CFG1[3]: NOR/OneNAND Selection */ + if ((reg & 0x00000008) >> 3) + return BOOT_DEVICE_ONENAND; + else + return BOOT_DEVICE_NOR; + break; + /* SATA: See 8.5.4, Table 8-20 */ + case 0x2: + return BOOT_DEVICE_SATA; + /* Serial ROM: See 8.5.5.1, Table 8-22 */ + case 0x3: + /* BOOT_CFG4[2:0] */ + switch ((reg & 0x07000000) >> 24) { + case 0x0 ... 0x4: + return BOOT_DEVICE_SPI; + case 0x5 ... 0x7: + return BOOT_DEVICE_I2C; + } + break; + /* SD/eSD: 8.5.3, Table 8-15 */ + case 0x4: + case 0x5: + return BOOT_DEVICE_MMC1; + /* MMC/eMMC: 8.5.3 */ + case 0x6: + case 0x7: + return BOOT_DEVICE_MMC1; + /* NAND Flash: 8.5.2 */ + case 0x8 ... 0xf: + return BOOT_DEVICE_NAND; + } + return BOOT_DEVICE_NONE; +} +#endif + +#if defined(CONFIG_SPL_MMC_SUPPORT) +/* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */ +u32 spl_boot_mode(void) +{ + switch (spl_boot_device()) { + /* for MMC return either RAW or FAT mode */ + case BOOT_DEVICE_MMC1: + case BOOT_DEVICE_MMC2: +#ifdef CONFIG_SPL_FAT_SUPPORT + return MMCSD_MODE_FAT; +#else + return MMCSD_MODE_RAW; +#endif + break; + default: + puts("spl: ERROR: unsupported device\n"); + hang(); + } +} +#endif -- cgit From b07161c321d9bc4ca5c610087b5d4e0566402d20 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 2 Jun 2014 16:13:21 -0700 Subject: imx: add comments and remove unused struct fields Add comment block for the imx_ddr_size function and remove the extra unused fields from struct esd_mmdc_regs which are also not common between IMX53 and IMX6. Cc: Stefan Roese Cc: Otavio Salvador Cc: Andy Ng Cc: Eric Nelson Cc: Tapani Utriainen Cc: Tom Rini Signed-off-by: Tim Harvey Acked-by: Stefano Babic Acked-by: Nikita Kiryanov --- arch/arm/imx-common/cpu.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index a77c4decc9..5a09107c5a 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -58,6 +58,7 @@ char *get_reset_cause(void) static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9}; static const unsigned char bank_lookup[] = {3, 2}; +/* these MMDC registers are common to the IMX53 and IMX6 */ struct esd_mmdc_regs { uint32_t ctl; uint32_t pdc; @@ -66,15 +67,6 @@ struct esd_mmdc_regs { uint32_t cfg1; uint32_t cfg2; uint32_t misc; - uint32_t scr; - uint32_t ref; - uint32_t rsvd1; - uint32_t rsvd2; - uint32_t rwd; - uint32_t or; - uint32_t mrr; - uint32_t cfg3lp; - uint32_t mr4; }; #define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7) @@ -83,6 +75,12 @@ struct esd_mmdc_regs { #define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1) #define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1) +/* + * imx_ddr_size - return size in bytes of DRAM according MMDC config + * The MMDC MDCTL register holds the number of bits for row, col, and data + * width and the MMDC MDMISC register holds the number of banks. Combine + * all these bits to determine the meme size the MMDC has been configured for + */ unsigned imx_ddr_size(void) { struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE; -- cgit From 8d05b161fc4633788bcad133efdf8d76fc40237f Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 2 Jun 2014 16:13:22 -0700 Subject: mx6: add structs for mmdc and ddr iomux registers Add memory-mapped structures for MMDC iomux and configuration. Note that whi the MMDC configuration registers are common between the IMX6DQ (IMX6DUAL/IMX6QUAD) and IMX6SDL (IMX6SOLO/IMX6DUALLITE) types the iomux registers differ. This requires two sets of structures. Add structures to describe DDR3 device information, system information (memory layout, etc), and MMDC calibration registers that can be used to configure the MMDC dynamically. We define these structures for SPL builds instead of including mx6q-ddr.h an mx6dl-ddr.h which use the same namespace and are only useful for imximage cf files. Cc: Stefan Roese Cc: Otavio Salvador Cc: Andy Ng Cc: Eric Nelson Cc: Tapani Utriainen Cc: Tom Rini Signed-off-by: Tim Harvey Acked-by: Nikita Kiryanov --- arch/arm/include/asm/arch-mx6/mx6-ddr.h | 159 ++++++++++++++++++++++++++++++++ 1 file changed, 159 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h index 43d377af35..c2a31d2e2e 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h @@ -6,6 +6,7 @@ #ifndef __ASM_ARCH_MX6_DDR_H__ #define __ASM_ARCH_MX6_DDR_H__ +#ifndef CONFIG_SPL_BUILD #ifdef CONFIG_MX6Q #include "mx6q-ddr.h" #else @@ -15,6 +16,164 @@ #error "Please select cpu" #endif /* CONFIG_MX6DL or CONFIG_MX6S */ #endif /* CONFIG_MX6Q */ +#else + +/* MMDC P0/P1 Registers */ +struct mmdc_p_regs { + u32 mdctl; + u32 mdpdc; + u32 mdotc; + u32 mdcfg0; + u32 mdcfg1; + u32 mdcfg2; + u32 mdmisc; + u32 mdscr; + u32 mdref; + u32 res1[2]; + u32 mdrwd; + u32 mdor; + u32 res2[3]; + u32 mdasp; + u32 res3[240]; + u32 mapsr; + u32 res4[254]; + u32 mpzqhwctrl; + u32 res5[2]; + u32 mpwldectrl0; + u32 mpwldectrl1; + u32 res6; + u32 mpodtctrl; + u32 mprddqby0dl; + u32 mprddqby1dl; + u32 mprddqby2dl; + u32 mprddqby3dl; + u32 res7[4]; + u32 mpdgctrl0; + u32 mpdgctrl1; + u32 res8; + u32 mprddlctl; + u32 res9; + u32 mpwrdlctl; + u32 res10[25]; + u32 mpmur0; +}; + +/* + * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL) + */ +#define MX6DQ_IOM_DDR_BASE 0x020e0500 +struct mx6dq_iomux_ddr_regs { + u32 res1[3]; + u32 dram_sdqs5; + u32 dram_dqm5; + u32 dram_dqm4; + u32 dram_sdqs4; + u32 dram_sdqs3; + u32 dram_dqm3; + u32 dram_sdqs2; + u32 dram_dqm2; + u32 res2[16]; + u32 dram_cas; + u32 res3[2]; + u32 dram_ras; + u32 dram_reset; + u32 res4[2]; + u32 dram_sdclk_0; + u32 dram_sdba2; + u32 dram_sdcke0; + u32 dram_sdclk_1; + u32 dram_sdcke1; + u32 dram_sdodt0; + u32 dram_sdodt1; + u32 res5; + u32 dram_sdqs0; + u32 dram_dqm0; + u32 dram_sdqs1; + u32 dram_dqm1; + u32 dram_sdqs6; + u32 dram_dqm6; + u32 dram_sdqs7; + u32 dram_dqm7; +}; + +#define MX6DQ_IOM_GRP_BASE 0x020e0700 +struct mx6dq_iomux_grp_regs { + u32 res1[18]; + u32 grp_b7ds; + u32 grp_addds; + u32 grp_ddrmode_ctl; + u32 res2; + u32 grp_ddrpke; + u32 res3[6]; + u32 grp_ddrmode; + u32 res4[3]; + u32 grp_b0ds; + u32 grp_b1ds; + u32 grp_ctlds; + u32 res5; + u32 grp_b2ds; + u32 grp_ddr_type; + u32 grp_b3ds; + u32 grp_b4ds; + u32 grp_b5ds; + u32 grp_b6ds; +}; + +#define MX6SDL_IOM_DDR_BASE 0x020e0400 +struct mx6sdl_iomux_ddr_regs { + u32 res1[25]; + u32 dram_cas; + u32 res2[2]; + u32 dram_dqm0; + u32 dram_dqm1; + u32 dram_dqm2; + u32 dram_dqm3; + u32 dram_dqm4; + u32 dram_dqm5; + u32 dram_dqm6; + u32 dram_dqm7; + u32 dram_ras; + u32 dram_reset; + u32 res3[2]; + u32 dram_sdba2; + u32 dram_sdcke0; + u32 dram_sdcke1; + u32 dram_sdclk_0; + u32 dram_sdclk_1; + u32 dram_sdodt0; + u32 dram_sdodt1; + u32 dram_sdqs0; + u32 dram_sdqs1; + u32 dram_sdqs2; + u32 dram_sdqs3; + u32 dram_sdqs4; + u32 dram_sdqs5; + u32 dram_sdqs6; + u32 dram_sdqs7; +}; + +#define MX6SDL_IOM_GRP_BASE 0x020e0700 +struct mx6sdl_iomux_grp_regs { + u32 res1[18]; + u32 grp_b7ds; + u32 grp_addds; + u32 grp_ddrmode_ctl; + u32 grp_ddrpke; + u32 res2[2]; + u32 grp_ddrmode; + u32 grp_b0ds; + u32 res3; + u32 grp_ctlds; + u32 grp_b1ds; + u32 grp_ddr_type; + u32 grp_b2ds; + u32 grp_b3ds; + u32 grp_b4ds; + u32 grp_b5ds; + u32 res4; + u32 grp_b6ds; +}; +#endif /* CONFIG_SPL_BUILD */ #define MX6_MMDC_P0_MDCTL 0x021b0000 #define MX6_MMDC_P0_MDPDC 0x021b0004 -- cgit From fe0f7f7842e109b9e04e455787d35bf3b21027c2 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 2 Jun 2014 16:13:23 -0700 Subject: mx6: add mmdc configuration for MX6Q/MX6DL - add function for configuring iomux based on board-specific regs - add function for configuring mmdc based on board-specific and chip-specific data Cc: Stefan Roese Cc: Otavio Salvador Cc: Andy Ng Cc: Eric Nelson Cc: Tapani Utriainen Cc: Tom Rini Signed-off-by: Tim Harvey --- arch/arm/cpu/armv7/mx6/Makefile | 1 + arch/arm/cpu/armv7/mx6/ddr.c | 490 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/mx6-ddr.h | 72 +++++ 3 files changed, 563 insertions(+) create mode 100644 arch/arm/cpu/armv7/mx6/ddr.c (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/mx6/Makefile b/arch/arm/cpu/armv7/mx6/Makefile index d7285fc2cc..6dc9f8ec21 100644 --- a/arch/arm/cpu/armv7/mx6/Makefile +++ b/arch/arm/cpu/armv7/mx6/Makefile @@ -8,4 +8,5 @@ # obj-y := soc.o clock.o +obj-$(CONFIG_SPL_BUILD) += ddr.o obj-$(CONFIG_SECURE_BOOT) += hab.o diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c new file mode 100644 index 0000000000..0434211110 --- /dev/null +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -0,0 +1,490 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Author: Tim Harvey + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) +/* Configure MX6DQ mmdc iomux */ +void mx6dq_dram_iocfg(unsigned width, + const struct mx6dq_iomux_ddr_regs *ddr, + const struct mx6dq_iomux_grp_regs *grp) +{ + volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux; + volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux; + + mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE; + mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE; + + /* DDR IO Type */ + mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type; + mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke; + + /* Clock */ + mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0; + mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1; + + /* Address */ + mx6_ddr_iomux->dram_cas = ddr->dram_cas; + mx6_ddr_iomux->dram_ras = ddr->dram_ras; + mx6_grp_iomux->grp_addds = grp->grp_addds; + + /* Control */ + mx6_ddr_iomux->dram_reset = ddr->dram_reset; + mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0; + mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1; + mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2; + mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0; + mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1; + mx6_grp_iomux->grp_ctlds = grp->grp_ctlds; + + /* Data Strobes */ + mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl; + mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0; + mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1; + if (width >= 32) { + mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2; + mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3; + } + if (width >= 64) { + mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4; + mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5; + mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6; + mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7; + } + + /* Data */ + mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode; + mx6_grp_iomux->grp_b0ds = grp->grp_b0ds; + mx6_grp_iomux->grp_b1ds = grp->grp_b1ds; + if (width >= 32) { + mx6_grp_iomux->grp_b2ds = grp->grp_b2ds; + mx6_grp_iomux->grp_b3ds = grp->grp_b3ds; + } + if (width >= 64) { + mx6_grp_iomux->grp_b4ds = grp->grp_b4ds; + mx6_grp_iomux->grp_b5ds = grp->grp_b5ds; + mx6_grp_iomux->grp_b6ds = grp->grp_b6ds; + mx6_grp_iomux->grp_b7ds = grp->grp_b7ds; + } + mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0; + mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1; + if (width >= 32) { + mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2; + mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3; + } + if (width >= 64) { + mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4; + mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5; + mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6; + mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7; + } +} +#endif + +#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) +/* Configure MX6SDL mmdc iomux */ +void mx6sdl_dram_iocfg(unsigned width, + const struct mx6sdl_iomux_ddr_regs *ddr, + const struct mx6sdl_iomux_grp_regs *grp) +{ + volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux; + volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux; + + mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE; + mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE; + + /* DDR IO Type */ + mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type; + mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke; + + /* Clock */ + mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0; + mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1; + + /* Address */ + mx6_ddr_iomux->dram_cas = ddr->dram_cas; + mx6_ddr_iomux->dram_ras = ddr->dram_ras; + mx6_grp_iomux->grp_addds = grp->grp_addds; + + /* Control */ + mx6_ddr_iomux->dram_reset = ddr->dram_reset; + mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0; + mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1; + mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2; + mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0; + mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1; + mx6_grp_iomux->grp_ctlds = grp->grp_ctlds; + + /* Data Strobes */ + mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl; + mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0; + mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1; + if (width >= 32) { + mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2; + mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3; + } + if (width >= 64) { + mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4; + mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5; + mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6; + mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7; + } + + /* Data */ + mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode; + mx6_grp_iomux->grp_b0ds = grp->grp_b0ds; + mx6_grp_iomux->grp_b1ds = grp->grp_b1ds; + if (width >= 32) { + mx6_grp_iomux->grp_b2ds = grp->grp_b2ds; + mx6_grp_iomux->grp_b3ds = grp->grp_b3ds; + } + if (width >= 64) { + mx6_grp_iomux->grp_b4ds = grp->grp_b4ds; + mx6_grp_iomux->grp_b5ds = grp->grp_b5ds; + mx6_grp_iomux->grp_b6ds = grp->grp_b6ds; + mx6_grp_iomux->grp_b7ds = grp->grp_b7ds; + } + mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0; + mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1; + if (width >= 32) { + mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2; + mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3; + } + if (width >= 64) { + mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4; + mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5; + mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6; + mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7; + } +} +#endif + +/* + * Configure mx6 mmdc registers based on: + * - board-specific memory configuration + * - board-specific calibration data + * - ddr3 chip details + * + * The various calculations here are derived from the Freescale + * i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate MMDC + * configuration registers based on memory system and memory chip parameters. + * + * The defaults here are those which were specified in the spreadsheet. + * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM + * section titled MMDC initialization + */ +#define MR(val, ba, cmd, cs1) \ + ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba) +void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i, + const struct mx6_mmdc_calibration *c, + const struct mx6_ddr3_cfg *m) +{ + volatile struct mmdc_p_regs *mmdc0; + volatile struct mmdc_p_regs *mmdc1; + u32 reg; + u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd; + u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl; + u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */ + u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr; + u16 CS0_END; + u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */ + int clkper; /* clock period in picoseconds */ + int clock; /* clock freq in mHz */ + int cs; + + mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; + mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR; + + /* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */ + if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) { + clock = 528; + tcwl = 4; + } + /* MX6S/MX6DL: 800 MHz memory clock, clkper = 2.5ns = 2500ps */ + else { + clock = 400; + tcwl = 3; + } + clkper = (1000*1000)/clock; /* ps */ + todtlon = tcwl; + taxpd = tcwl; + tanpd = tcwl; + tcwl = tcwl; + + switch (m->density) { + case 1: /* 1Gb per chip */ + trfc = DIV_ROUND_UP(110000, clkper) - 1; + txs = DIV_ROUND_UP(120000, clkper) - 1; + break; + case 2: /* 2Gb per chip */ + trfc = DIV_ROUND_UP(160000, clkper) - 1; + txs = DIV_ROUND_UP(170000, clkper) - 1; + break; + case 4: /* 4Gb per chip */ + trfc = DIV_ROUND_UP(260000, clkper) - 1; + txs = DIV_ROUND_UP(270000, clkper) - 1; + break; + case 8: /* 8Gb per chip */ + trfc = DIV_ROUND_UP(350000, clkper) - 1; + txs = DIV_ROUND_UP(360000, clkper) - 1; + break; + default: + /* invalid density */ + printf("invalid chip density\n"); + hang(); + break; + } + txpr = txs; + + switch (m->mem_speed) { + case 800: + txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1; + tcke = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1; + if (m->pagesz == 1) { + tfaw = DIV_ROUND_UP(40000, clkper) - 1; + trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1; + } else { + tfaw = DIV_ROUND_UP(50000, clkper) - 1; + trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1; + } + break; + case 1066: + txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1; + tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1; + if (m->pagesz == 1) { + tfaw = DIV_ROUND_UP(37500, clkper) - 1; + trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1; + } else { + tfaw = DIV_ROUND_UP(50000, clkper) - 1; + trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1; + } + break; + case 1333: + txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1; + tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1; + if (m->pagesz == 1) { + tfaw = DIV_ROUND_UP(30000, clkper) - 1; + trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1; + } else { + tfaw = DIV_ROUND_UP(45000, clkper) - 1; + trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1; + } + break; + case 1600: + txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1; + tcke = DIV_ROUND_UP(MAX(3*clkper, 5000), clkper) - 1; + if (m->pagesz == 1) { + tfaw = DIV_ROUND_UP(30000, clkper) - 1; + trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1; + } else { + tfaw = DIV_ROUND_UP(40000, clkper) - 1; + trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1; + } + break; + default: + printf("invalid memory speed\n"); + hang(); + break; + } + txpdll = DIV_ROUND_UP(MAX(10*clkper, 24000), clkper) - 1; + tcl = DIV_ROUND_UP(m->trcd, clkper/10) - 3; + tcksre = DIV_ROUND_UP(MAX(5*clkper, 10000), clkper); + tcksrx = tcksre; + taonpd = DIV_ROUND_UP(2000, clkper) - 1; + taofpd = taonpd; + trp = DIV_ROUND_UP(m->trcd, clkper/10) - 1; + trcd = trp; + trc = DIV_ROUND_UP(m->trcmin, clkper/10) - 1; + tras = DIV_ROUND_UP(m->trasmin, clkper/10) - 1; + twr = DIV_ROUND_UP(15000, clkper) - 1; + tmrd = DIV_ROUND_UP(MAX(12*clkper, 15000), clkper) - 1; + twtr = ROUND(MAX(4*clkper, 7500)/clkper, 1) - 1; + trtp = twtr; + CS0_END = ((4*i->cs_density) <= 120) ? (4*i->cs_density)+7 : 127; + debug("density:%d Gb (%d Gb per chip)\n", i->cs_density, m->density); + debug("clock: %dMHz (%d ps)\n", clock, clkper); + debug("memspd:%d\n", m->mem_speed); + debug("tcke=%d\n", tcke); + debug("tcksrx=%d\n", tcksrx); + debug("tcksre=%d\n", tcksre); + debug("taofpd=%d\n", taofpd); + debug("taonpd=%d\n", taonpd); + debug("todtlon=%d\n", todtlon); + debug("tanpd=%d\n", tanpd); + debug("taxpd=%d\n", taxpd); + debug("trfc=%d\n", trfc); + debug("txs=%d\n", txs); + debug("txp=%d\n", txp); + debug("txpdll=%d\n", txpdll); + debug("tfaw=%d\n", tfaw); + debug("tcl=%d\n", tcl); + debug("trcd=%d\n", trcd); + debug("trp=%d\n", trp); + debug("trc=%d\n", trc); + debug("tras=%d\n", tras); + debug("twr=%d\n", twr); + debug("tmrd=%d\n", tmrd); + debug("tcwl=%d\n", tcwl); + debug("tdllk=%d\n", tdllk); + debug("trtp=%d\n", trtp); + debug("twtr=%d\n", twtr); + debug("trrd=%d\n", trrd); + debug("txpr=%d\n", txpr); + debug("CS0_END=%d\n", CS0_END); + debug("ncs=%d\n", i->ncs); + debug("Rtt_wr=%d\n", i->rtt_wr); + debug("Rtt_nom=%d\n", i->rtt_nom); + debug("SRT=%d\n", m->SRT); + debug("tcl=%d\n", tcl); + debug("twr=%d\n", twr); + + /* + * board-specific configuration: + * These values are determined empirically and vary per board layout + * see: + * appnote, ddr3 spreadsheet + */ + mmdc0->mpwldectrl0 = c->p0_mpwldectrl0; + mmdc0->mpwldectrl1 = c->p0_mpwldectrl1; + mmdc0->mpdgctrl0 = c->p0_mpdgctrl0; + mmdc0->mpdgctrl1 = c->p0_mpdgctrl1; + mmdc0->mprddlctl = c->p0_mprddlctl; + mmdc0->mpwrdlctl = c->p0_mpwrdlctl; + if (i->dsize > 1) { + mmdc1->mpwldectrl0 = c->p1_mpwldectrl0; + mmdc1->mpwldectrl1 = c->p1_mpwldectrl1; + mmdc1->mpdgctrl0 = c->p1_mpdgctrl0; + mmdc1->mpdgctrl1 = c->p1_mpdgctrl1; + mmdc1->mprddlctl = c->p1_mprddlctl; + mmdc1->mpwrdlctl = c->p1_mpwrdlctl; + } + + /* Read data DQ Byte0-3 delay */ + mmdc0->mprddqby0dl = (u32)0x33333333; + mmdc0->mprddqby1dl = (u32)0x33333333; + if (i->dsize > 0) { + mmdc0->mprddqby2dl = (u32)0x33333333; + mmdc0->mprddqby3dl = (u32)0x33333333; + } + if (i->dsize > 1) { + mmdc1->mprddqby0dl = (u32)0x33333333; + mmdc1->mprddqby1dl = (u32)0x33333333; + mmdc1->mprddqby2dl = (u32)0x33333333; + mmdc1->mprddqby3dl = (u32)0x33333333; + } + + /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */ + reg = (i->rtt_nom == 2) ? 0x00011117 : 0x00022227; + mmdc0->mpodtctrl = reg; + if (i->dsize > 1) + mmdc1->mpodtctrl = reg; + + /* complete calibration */ + reg = (1 << 11); /* Force measurement on delay-lines */ + mmdc0->mpmur0 = reg; + if (i->dsize > 1) + mmdc1->mpmur0 = reg; + + /* Step 1: configuration request */ + mmdc0->mdscr = (u32)(1 << 15); /* config request */ + + /* Step 2: Timing configuration */ + reg = (trfc << 24) | (txs << 16) | (txp << 13) | (txpdll << 9) | + (tfaw << 4) | tcl; + mmdc0->mdcfg0 = reg; + reg = (trcd << 29) | (trp << 26) | (trc << 21) | (tras << 16) | + (1 << 15) | /* trpa */ + (twr << 9) | (tmrd << 5) | tcwl; + mmdc0->mdcfg1 = reg; + reg = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd; + mmdc0->mdcfg2 = reg; + reg = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) | (taxpd << 16) | + (todtlon << 12) | (todt_idle_off << 4); + mmdc0->mdotc = reg; + mmdc0->mdasp = CS0_END; /* CS addressing */ + + /* Step 3: Configure DDR type */ + reg = (i->cs1_mirror << 19) | (i->walat << 16) | (i->bi_on << 12) | + (i->mif3_mode << 9) | (i->ralat << 6); + mmdc0->mdmisc = reg; + + /* Step 4: Configure delay while leaving reset */ + reg = (txpr << 16) | (i->sde_to_rst << 8) | (i->rst_to_cke << 0); + mmdc0->mdor = reg; + + /* Step 5: Configure DDR physical parameters (density and burst len) */ + reg = (m->rowaddr - 11) << 24 | /* ROW */ + (m->coladdr - 9) << 20 | /* COL */ + (1 << 19) | /* Burst Length = 8 for DDR3 */ + (i->dsize << 16); /* DDR data bus size */ + mmdc0->mdctl = reg; + + /* Step 6: Perform ZQ calibration */ + reg = (u32)0xa1390001; /* one-time HW ZQ calib */ + mmdc0->mpzqhwctrl = reg; + if (i->dsize > 1) + mmdc1->mpzqhwctrl = reg; + + /* Step 7: Enable MMDC with desired chip select */ + reg = mmdc0->mdctl | + (1 << 31) | /* SDE_0 for CS0 */ + ((i->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */ + mmdc0->mdctl = reg; + + /* Step 8: Write Mode Registers to Init DDR3 devices */ + for (cs = 0; cs < i->ncs; cs++) { + /* MR2 */ + reg = (i->rtt_wr & 3) << 9 | (m->SRT & 1) << 7 | + ((tcwl - 3) & 3) << 3; + mmdc0->mdscr = (u32)MR(reg, 2, 3, cs); + /* MR3 */ + mmdc0->mdscr = (u32)MR(0, 3, 3, cs); + /* MR1 */ + reg = ((i->rtt_nom & 1) ? 1 : 0) << 2 | + ((i->rtt_nom & 2) ? 1 : 0) << 6; + mmdc0->mdscr = (u32)MR(reg, 1, 3, cs); + reg = ((tcl - 1) << 4) | /* CAS */ + (1 << 8) | /* DLL Reset */ + ((twr - 3) << 9); /* Write Recovery */ + /* MR0 */ + mmdc0->mdscr = (u32)MR(reg, 0, 3, cs); + /* ZQ calibration */ + reg = (1 << 10); + mmdc0->mdscr = (u32)MR(reg, 0, 4, cs); + } + + /* Step 10: Power down control and self-refresh */ + reg = (tcke & 0x7) << 16 | + 5 << 12 | /* PWDT_1: 256 cycles */ + 5 << 8 | /* PWDT_0: 256 cycles */ + 1 << 6 | /* BOTH_CS_PD */ + (tcksrx & 0x7) << 3 | + (tcksre & 0x7); + mmdc0->mdpdc = reg; + mmdc0->mapsr = (u32)0x00011006; /* ADOPT power down enabled */ + + /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */ + mmdc0->mpzqhwctrl = (u32)0xa1390003; + if (i->dsize > 1) + mmdc1->mpzqhwctrl = (u32)0xa1390003; + + /* Step 12: Configure and activate periodic refresh */ + reg = (1 << 14) | /* REF_SEL: Periodic refresh cycles of 32kHz */ + (7 << 11); /* REFR: Refresh Rate - 8 refreshes */ + mmdc0->mdref = reg; + + /* Step 13: Deassert config request - init complete */ + mmdc0->mdscr = (u32)0x00000000; + + /* wait for auto-ZQ calibration to complete */ + mdelay(1); +} diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h index c2a31d2e2e..d544d2e708 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h @@ -173,6 +173,78 @@ struct mx6sdl_iomux_grp_regs { u32 res4; u32 grp_b6ds; }; + +/* Device Information: Varies per DDR3 part number and speed grade */ +struct mx6_ddr3_cfg { + u16 mem_speed; /* ie 1600 for DDR3-1600 (800,1066,1333,1600) */ + u8 density; /* chip density (Gb) (1,2,4,8) */ + u8 width; /* bus width (bits) (4,8,16) */ + u8 banks; /* number of banks */ + u8 rowaddr; /* row address bits (11-16)*/ + u8 coladdr; /* col address bits (9-12) */ + u8 pagesz; /* page size (K) (1-2) */ + u16 trcd; /* tRCD=tRP=CL (ns*100) */ + u16 trcmin; /* tRC min (ns*100) */ + u16 trasmin; /* tRAS min (ns*100) */ + u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */ +}; + +/* System Information: Varies per board design, layout, and term choices */ +struct mx6_ddr_sysinfo { + u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */ + u8 cs_density; /* density per chip select (Gb) */ + u8 ncs; /* number chip selects used (1|2) */ + char cs1_mirror;/* enable address mirror (0|1) */ + char bi_on; /* Bank interleaving enable */ + u8 rtt_nom; /* Rtt_Nom (DDR3_RTT_*) */ + u8 rtt_wr; /* Rtt_Wr (DDR3_RTT_*) */ + u8 ralat; /* Read Additional Latency (0-7) */ + u8 walat; /* Write Additional Latency (0-3) */ + u8 mif3_mode; /* Command prediction working mode */ + u8 rst_to_cke; /* Time from SDE enable to CKE rise */ + u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */ +}; + +/* + * Board specific calibration: + * This includes write leveling calibration values as well as DQS gating + * and read/write delays. These values are board/layout/device specific. + * Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2 + * (DOC-96412) to determine these values over a range of boards and + * temperatures. + */ +struct mx6_mmdc_calibration { + /* write leveling calibration */ + u32 p0_mpwldectrl0; + u32 p0_mpwldectrl1; + u32 p1_mpwldectrl0; + u32 p1_mpwldectrl1; + /* read DQS gating */ + u32 p0_mpdgctrl0; + u32 p0_mpdgctrl1; + u32 p1_mpdgctrl0; + u32 p1_mpdgctrl1; + /* read delay */ + u32 p0_mprddlctl; + u32 p1_mprddlctl; + /* write delay */ + u32 p0_mpwrdlctl; + u32 p1_mpwrdlctl; +}; + +/* configure iomux (pinctl/padctl) */ +void mx6dq_dram_iocfg(unsigned width, + const struct mx6dq_iomux_ddr_regs *, + const struct mx6dq_iomux_grp_regs *); +void mx6sdl_dram_iocfg(unsigned width, + const struct mx6sdl_iomux_ddr_regs *, + const struct mx6sdl_iomux_grp_regs *); + +/* configure mx6 mmdc registers */ +void mx6_dram_cfg(const struct mx6_ddr_sysinfo *, + const struct mx6_mmdc_calibration *, + const struct mx6_ddr3_cfg *); + #endif /* CONFIG_SPL_BUILD */ #define MX6_MMDC_P0_MDCTL 0x021b0000 -- cgit From 5bf497e3fdba14cb39f8752ae7646d77dc49d519 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 2 Jun 2014 16:13:24 -0700 Subject: imx: iomux: add macros to setup iomux for multiple SoC types Allow imx_iomux_v3_setup_multiple_pads to take a multi-cpu pad_list and add macros for declaring the pad_list that take into account the SoC types supported using CONFIG_MX6QDL (supports both the MX6Q and MX6DL iomux). Cc: Stefan Roese Cc: Otavio Salvador Cc: Andy Ng Cc: Eric Nelson Cc: Tapani Utriainen Cc: Tom Rini Signed-off-by: Tim Harvey --- arch/arm/imx-common/iomux-v3.c | 16 ++++++++++++++-- arch/arm/include/asm/imx-common/iomux-v3.h | 25 +++++++++++++++++++++++++ 2 files changed, 39 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index 6e46ea8dcd..306183a70e 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -11,6 +11,7 @@ #include #include #include +#include #include static void *base = (void *)IOMUXC_BASE_ADDR; @@ -54,12 +55,23 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) #endif } +/* configures a list of pads within declared with IOMUX_PADS macro */ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, unsigned count) { iomux_v3_cfg_t const *p = pad_list; + int stride; int i; - for (i = 0; i < count; i++) - imx_iomux_v3_setup_pad(*p++); +#if defined(CONFIG_MX6QDL) + stride = 2; + if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D)) + p += 1; +#else + stride = 1; +#endif + for (i = 0; i < count; i++) { + imx_iomux_v3_setup_pad(*p); + p += stride; + } } diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index cca920b28e..dfe1ebfa92 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -175,4 +175,29 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad); void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, unsigned count); +/* macros for declaring and using pinmux array */ +#if defined(CONFIG_MX6QDL) +#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x) +#define SETUP_IOMUX_PAD(def) \ +if (is_cpu_type(MXC_CPU_MX6Q)) { \ + imx_iomux_v3_setup_pad(MX6Q_##def); \ +} else { \ + imx_iomux_v3_setup_pad(MX6DL_##def); \ +} +#define SETUP_IOMUX_PADS(x) \ + imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2) +#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) +#define IOMUX_PADS(x) MX6Q_##x +#define SETUP_IOMUX_PAD(def) \ + imx_iomux_v3_setup_pad(MX6Q_##def); +#define SETUP_IOMUX_PADS(x) \ + imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)) +#else +#define IOMUX_PADS(x) MX6DL_##x +#define SETUP_IOMUX_PAD(def) \ + imx_iomux_v3_setup_pad(MX6DL_##def); +#define SETUP_IOMUX_PADS(x) \ + imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)) +#endif + #endif /* __MACH_IOMUX_V3_H__*/ -- cgit From 22452fd821300ef715c2c9d62ea466767e5eafd3 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Wed, 7 May 2014 22:24:47 -0700 Subject: imx: sata: return failure if not IMX6Q/IMX6D The IMX6QUAD/DUAL have SATA, but the IMX6SOLO/DL do not. Return instead of configuring the SATA clock and GPR13 registers. Signed-off-by: Tim Harvey --- arch/arm/imx-common/sata.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c index 2e694866e0..c10dd28f61 100644 --- a/arch/arm/imx-common/sata.c +++ b/arch/arm/imx-common/sata.c @@ -8,13 +8,18 @@ #include #include #include +#include int setup_sata(void) { struct iomuxc_base_regs *const iomuxc_regs = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR; + int ret; - int ret = enable_sata_clock(); + if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D)) + return 1; + + ret = enable_sata_clock(); if (ret) return ret; -- cgit From 67a04ab3ab8522a3a34491853e46105317580df5 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 6 Jun 2014 10:58:47 +0200 Subject: MX25: fix build due to missing sys_proto.h THe mx25 arch does not have a sys_proto.h file. Instead of creating a dummy file, the file is not included for this SOC. Signed-off-by: Stefano Babic --- arch/arm/imx-common/iomux-v3.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index 306183a70e..c090b308b2 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -11,7 +11,9 @@ #include #include #include +#ifndef CONFIG_MX25 #include +#endif #include static void *base = (void *)IOMUXC_BASE_ADDR; -- cgit From 9d2ca0984bda37bb58bf7f58f1626450e28a6595 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 6 May 2014 09:13:02 +0800 Subject: arm: imx: Add two macros for VF610 in IOMUX_PAD structure Add PAD_CTL_DSE_150ohm and PAD_CTL_PUS_22K_UP for VF610 in IOMUX_PAD structure. Signed-off-by: Alison Wang --- arch/arm/include/asm/imx-common/iomux-v3.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index cca920b28e..ff45618e45 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -123,12 +123,14 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_SPEED_MED (1 << 12) #define PAD_CTL_SPEED_HIGH (3 << 12) +#define PAD_CTL_DSE_150ohm (1 << 6) #define PAD_CTL_DSE_50ohm (3 << 6) #define PAD_CTL_DSE_25ohm (6 << 6) #define PAD_CTL_DSE_20ohm (7 << 6) #define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) #define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE) #define PAD_CTL_PKE (1 << 3) #define PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE) -- cgit From cb6d04d60664210d2e198192e164b6cfc8bade83 Mon Sep 17 00:00:00 2001 From: Chao Fu Date: Tue, 6 May 2014 09:13:03 +0800 Subject: arm: vf610: Add QSPI support for VF610TWR Add QSPI support for VF610TWR, such as clock and iomux. Signed-off-by: Alison Wang Signed-off-by: Chao Fu --- arch/arm/include/asm/arch-vf610/crm_regs.h | 11 ++++++++++- arch/arm/include/asm/arch-vf610/imx-regs.h | 4 +++- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 17 ++++++++++++++++- 3 files changed, 29 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index e17c7d1f70..5256624adf 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -1,5 +1,5 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -150,6 +150,9 @@ struct anadig_reg { #define CCM_CACRR_ARM_CLK_DIV_MASK 0x7 #define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7) +#define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET 22 +#define CCM_CSCMR1_QSPI0_CLK_SEL_MASK (0x3 << 22) +#define CCM_CSCMR1_QSPI0_CLK_SEL(v) (((v) & 0x3) << 22) #define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18 #define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18) #define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18) @@ -161,6 +164,11 @@ struct anadig_reg { #define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20) #define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20) +#define CCM_CSCDR3_QSPI0_EN (1 << 4) +#define CCM_CSCDR3_QSPI0_DIV(v) ((v) << 3) +#define CCM_CSCDR3_QSPI0_X2_DIV(v) ((v) << 2) +#define CCM_CSCDR3_QSPI0_X4_DIV(v) ((v) & 0x3) + #define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4 #define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4) #define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4) @@ -170,6 +178,7 @@ struct anadig_reg { #define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16) #define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14) #define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28) +#define CCM_CCGR2_QSPI0_CTRL_MASK (0x3 << 8) #define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16) #define CCM_CCGR2_PORTA_CTRL_MASK (0x3 << 18) #define CCM_CCGR2_PORTB_CTRL_MASK (0x3 << 20) diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 0c28e1b840..bd6f680b63 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -1,5 +1,5 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -87,6 +87,8 @@ #define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000) #define ENET1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00051000) +#define QSPI0_AMBA_BASE 0x20000000 + /* MUX mode and PAD ctrl are in one register */ #define CONFIG_IOMUX_SHARE_CONF_REG diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h index 88807d8db4..a965641681 100644 --- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h +++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h @@ -1,5 +1,5 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -20,6 +20,9 @@ #define VF610_I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \ PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE) +#define VF610_QSPI_PAD_CTRL (PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_150ohm | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE) + enum { VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL), VF610_PAD_PTA6__RMII0_CLKOUT = IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL), @@ -53,6 +56,18 @@ enum { VF610_PAD_PTA29__ESDHC1_DAT3 = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL), VF610_PAD_PTB14__I2C0_SCL = IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL), VF610_PAD_PTB15__I2C0_SDA = IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL), + VF610_PAD_PTD0__QSPI0_A_QSCK = IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD1__QSPI0_A_CS0 = IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD2__QSPI0_A_DATA3 = IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD3__QSPI0_A_DATA2 = IOMUX_PAD(0x0148, 0x0148, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD4__QSPI0_A_DATA1 = IOMUX_PAD(0x014c, 0x014c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD5__QSPI0_A_DATA0 = IOMUX_PAD(0x0150, 0x0150, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD7__QSPI0_B_QSCK = IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD8__QSPI0_B_CS0 = IOMUX_PAD(0x015c, 0x015c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD9__QSPI0_B_DATA3 = IOMUX_PAD(0x0160, 0x0160, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD10__QSPI0_B_DATA2 = IOMUX_PAD(0x0164, 0x0164, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD11__QSPI0_B_DATA1 = IOMUX_PAD(0x0168, 0x0168, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), + VF610_PAD_PTD12__QSPI0_B_DATA0 = IOMUX_PAD(0x016c, 0x016c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL), VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL), VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL), -- cgit From b924d586d70bd52c3648870d3313b2ea7081c83d Mon Sep 17 00:00:00 2001 From: Mark Rutland Date: Wed, 21 May 2014 14:29:23 +0100 Subject: arm64: zero cntvoff_el2 Currently cntvoff_el2 is initialised with an arbitrary bag of bits derived from the initial value of cnthctl_el2 on the current CPU. This is somewhat odd and problematic as some of these bits are UNKNOWN at reset and may differ across CPUs (which may cause an OS at EL1 to observe time going backwards across CPUs). This patch instead initialises cntvoff_el2 with xzr, giving the register a consistent value of zero on all CPUs. Signed-off-by: Mark Rutland Acked-by: Marc Zyngier Acked-by: Catalin Marinas Cc: Scott Wood Cc: David Feng Cc: Tom Rini Acked-by: David.Feng --- arch/arm/cpu/armv8/transition.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S index e0a5946009..38dea5c518 100644 --- a/arch/arm/cpu/armv8/transition.S +++ b/arch/arm/cpu/armv8/transition.S @@ -43,7 +43,7 @@ ENTRY(armv8_switch_to_el1) mrs x0, cnthctl_el2 orr x0, x0, #0x3 /* Enable EL1 access to timers */ msr cnthctl_el2, x0 - msr cntvoff_el2, x0 + msr cntvoff_el2, xzr mrs x0, cntkctl_el1 orr x0, x0, #0x3 /* Enable EL0 access to timers */ msr cntkctl_el1, x0 -- cgit From 0a26e1d6c394aacbf1153977b7348d1dff85db3f Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 27 May 2014 11:16:29 +0900 Subject: arm: fix a double-definition error of _start symbol The symbol "_start" is defined twice in arch/arm/lib/vectors.S: around line 48 and line 54. If CONFIG_SYS_DV_NOR_BOOT_CFG is defined (as on calimain board), build fails: arch/arm/lib/vectors.S: Assembler messages: arch/arm/lib/vectors.S:54: Error: symbol `_start' is already defined make[1]: *** [arch/arm/lib/vectors.o] Error 1 make: *** [arch/arm/lib] Error 2 Signed-off-by: Masahiro Yamada Cc: Albert ARIBAUD --- arch/arm/lib/vectors.S | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index d68cc477dc..e6538eff43 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -43,8 +43,6 @@ ************************************************************************* */ -_start: - #ifdef CONFIG_SYS_DV_NOR_BOOT_CFG .word CONFIG_SYS_DV_NOR_BOOT_CFG #endif -- cgit From 7922a2d479b6cdce853b853b80d94675b955a66a Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Fri, 13 Jun 2014 17:00:56 +0900 Subject: Revert "exynos: Enable PSHOLD in SPL" This reverts commit eb0dd9986c3883820ff888c3738b013c0a7d918c. --- arch/arm/cpu/armv7/exynos/lowlevel_init.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c b/arch/arm/cpu/armv7/exynos/lowlevel_init.c index dcc270ffe4..83e1dcfc1e 100644 --- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c +++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c @@ -49,8 +49,6 @@ int do_lowlevel_init(void) arch_cpu_init(); - set_ps_hold_ctrl(); - reset_status = get_reset_status(); switch (reset_status) { -- cgit From cfde7588d8ad22560e2328574a4f415642170b92 Mon Sep 17 00:00:00 2001 From: Akshay Saraswat Date: Mon, 26 May 2014 19:17:03 +0530 Subject: Exynos5: DMC: Modify the definition of ddr3_mem_ctrl_init Passing fewer arguments is better and mem_iv_size is never used. Let's keep only one argument and make it cleaner. Signed-off-by: Hatim Ali Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/cpu/armv7/exynos/dmc_common.c | 2 +- arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 7 ++----- arch/arm/cpu/armv7/exynos/exynos5_setup.h | 9 ++------- 3 files changed, 5 insertions(+), 13 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/exynos/dmc_common.c b/arch/arm/cpu/armv7/exynos/dmc_common.c index cca925e42c..9b6ee69f46 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_common.c +++ b/arch/arm/cpu/armv7/exynos/dmc_common.c @@ -162,7 +162,7 @@ void mem_ctrl_init(int reset) /* If there are any other memory variant, add their init call below */ if (param->mem_type == DDR_MODE_DDR3) { - ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size, reset); + ret = ddr3_mem_ctrl_init(mem, reset); if (ret) { /* will hang if failed to init memory control */ while (1) diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c index 487e6f423f..4481ab46bf 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c +++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c @@ -28,8 +28,7 @@ static void reset_phy_ctrl(void) writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl); } -int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, - int reset) +int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) { unsigned int val; struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl; @@ -221,8 +220,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, #endif #ifdef CONFIG_EXYNOS5420 -int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, - int reset) +int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) { struct exynos5420_clock *clk = (struct exynos5420_clock *)samsung_get_base_clock(); @@ -244,7 +242,6 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, tzasc0 = (struct exynos5420_tzasc *)samsung_get_base_dmc_tzasc(); tzasc1 = (struct exynos5420_tzasc *)(samsung_get_base_dmc_tzasc() + DMC_OFFSET); - /* Enable PAUSE for DREX */ setbits_le32(&clk->pause, ENABLE_BIT); diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h index 53b0ace6e3..314d6f4e57 100644 --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h @@ -890,16 +890,11 @@ enum { /* * Memory variant specific initialization code for DDR3 * - * @param mem Memory timings for this memory type. - * @param mem_iv_size Memory interleaving size is a configurable parameter - * which the DMC uses to decide how to split a memory - * chunk into smaller chunks to support concurrent - * accesses; may vary across boards. + * @param mem Memory timings for this memory type. * @param reset Reset DDR PHY during initialization. * @return 0 if ok, SETUP_ERR_... if there is a problem */ -int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, - int reset); +int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset); /* Memory variant specific initialization code for LPDDR3 */ void lpddr3_mem_ctrl_init(void); -- cgit From aacdd79095b0a7c258a76e4fdfc133af16b07dc0 Mon Sep 17 00:00:00 2001 From: Akshay Saraswat Date: Mon, 26 May 2014 19:18:06 +0530 Subject: Exynos5420: Remove code for enabling read leveling This patch intends to remove all code which enables hardware read leveling. All characterization environments may not cope up with h/w read leveling enabled, so we must disable this. Also, disabling h/w read leveling improves the MIF LVcc value (LVcc value is the value at which DDR will fail to work properly). Improving LVcc means we have enough voltage margin for MIF. When h/w leveling is enabled, we have almost zero volatge margin. Signed-off-by: Alim Akhtar Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 71 ------------------------------- 1 file changed, 71 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c index 4481ab46bf..1d6048cbfc 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c +++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c @@ -519,77 +519,6 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) &drex1->directcmd); } - if (mem->read_leveling_enable) { - /* Set Read DQ Calibration */ - val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4; - for (chip = 0; chip < mem->chips_to_configure; chip++) { - writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), - &drex0->directcmd); - writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), - &drex1->directcmd); - } - - val = readl(&phy0_ctrl->phy_con1); - val |= READ_LEVELLING_DDR3; - writel(val, &phy0_ctrl->phy_con1); - val = readl(&phy1_ctrl->phy_con1); - val |= READ_LEVELLING_DDR3; - writel(val, &phy1_ctrl->phy_con1); - - val = readl(&phy0_ctrl->phy_con2); - val |= (RDLVL_EN | RDLVL_INCR_ADJ); - writel(val, &phy0_ctrl->phy_con2); - val = readl(&phy1_ctrl->phy_con2); - val |= (RDLVL_EN | RDLVL_INCR_ADJ); - writel(val, &phy1_ctrl->phy_con2); - - setbits_le32(&drex0->rdlvl_config, - CTRL_RDLVL_DATA_ENABLE); - i = TIMEOUT; - while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) - != RDLVL_COMPLETE_CHO) && (i > 0)) { - /* - * TODO(waihong): Comment on how long this take - * to timeout - */ - sdelay(100); - i--; - } - if (!i) - return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; - - clrbits_le32(&drex0->rdlvl_config, - CTRL_RDLVL_DATA_ENABLE); - setbits_le32(&drex1->rdlvl_config, - CTRL_RDLVL_DATA_ENABLE); - i = TIMEOUT; - while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) - != RDLVL_COMPLETE_CHO) && (i > 0)) { - /* - * TODO(waihong): Comment on how long this take - * to timeout - */ - sdelay(100); - i--; - } - if (!i) - return SETUP_ERR_RDLV_COMPLETE_TIMEOUT; - - clrbits_le32(&drex1->rdlvl_config, - CTRL_RDLVL_DATA_ENABLE); - - val = (0x3 << DIRECT_CMD_BANK_SHIFT); - for (chip = 0; chip < mem->chips_to_configure; chip++) { - writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), - &drex0->directcmd); - writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), - &drex1->directcmd); - } - - update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3); - update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3); - } - /* Common Settings for Leveling */ val = PHY_CON12_RESET_VAL; writel((val + n_lock_w_phy0), &phy0_ctrl->phy_con12); -- cgit From c9334fcda90652e2f8c49f4517b728ebc6f5f623 Mon Sep 17 00:00:00 2001 From: Doug Anderson Date: Mon, 26 May 2014 19:19:05 +0530 Subject: DMC: exynos5420: Gate CLKM to when reading PHY_CON13 when CLKM is running. If we stop CLKM when sampling it the glitches all go away, so we'll do that as per Samsung suggestion. We also check the "is it locked" bits of PHY_CON13 and loop until they show the the value sampled actually represents a locked value. It doesn't appear that the glitching and "is it locked" are related, but it seems wise to wait until the PHY tells us the value is good before we use it. In practice we will not loop more than a couple times (and usually won't loop at all). Signed-off-by: Doug Anderson Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 43 +++++++++++++++++++++++++++---- arch/arm/cpu/armv7/exynos/exynos5_setup.h | 1 + 2 files changed, 39 insertions(+), 5 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c index 1d6048cbfc..13003b86d5 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c +++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c @@ -230,6 +230,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) struct exynos5420_dmc *drex0, *drex1; struct exynos5420_tzasc *tzasc0, *tzasc1; uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1; + uint32_t lock0_info, lock1_info; int chip; int i; @@ -391,7 +392,41 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) */ dmc_config_mrs(mem, &drex0->directcmd); dmc_config_mrs(mem, &drex1->directcmd); - } else { + } + + /* + * Get PHY_CON13 from both phys. Gate CLKM around reading since + * PHY_CON13 is glitchy when CLKM is running. We're paranoid and + * wait until we get a "fine lock", though a coarse lock is probably + * OK (we only use the coarse numbers below). We try to gate the + * clock for as short a time as possible in case SDRAM is somehow + * sensitive. sdelay(10) in the loop is arbitrary to make sure + * there is some time for PHY_CON13 to get updated. In practice + * no delay appears to be needed. + */ + val = readl(&clk->gate_bus_cdrex); + while (true) { + writel(val & ~0x1, &clk->gate_bus_cdrex); + lock0_info = readl(&phy0_ctrl->phy_con13); + writel(val, &clk->gate_bus_cdrex); + + if ((lock0_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED) + break; + + sdelay(10); + } + while (true) { + writel(val & ~0x2, &clk->gate_bus_cdrex); + lock1_info = readl(&phy1_ctrl->phy_con13); + writel(val, &clk->gate_bus_cdrex); + + if ((lock1_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED) + break; + + sdelay(10); + } + + if (!reset) { /* * During Suspend-Resume & S/W-Reset, as soon as PMU releases * pad retention, CKE goes high. This causes memory contents @@ -442,15 +477,13 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET); writel(val, &phy1_ctrl->phy_con1); - n_lock_r = readl(&phy0_ctrl->phy_con13); - n_lock_w_phy0 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2; + n_lock_w_phy0 = (lock0_info & CTRL_LOCK_COARSE_MASK) >> 2; n_lock_r = readl(&phy0_ctrl->phy_con12); n_lock_r &= ~CTRL_DLL_ON; n_lock_r |= n_lock_w_phy0; writel(n_lock_r, &phy0_ctrl->phy_con12); - n_lock_r = readl(&phy1_ctrl->phy_con13); - n_lock_w_phy1 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2; + n_lock_w_phy1 = (lock1_info & CTRL_LOCK_COARSE_MASK) >> 2; n_lock_r = readl(&phy1_ctrl->phy_con12); n_lock_r &= ~CTRL_DLL_ON; n_lock_r |= n_lock_w_phy1; diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h index 314d6f4e57..d415c91f3a 100644 --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h @@ -284,6 +284,7 @@ #define CTRL_DLL_ON (1 << 5) #define CTRL_FORCE_MASK (0x7F << 8) #define CTRL_LOCK_COARSE_MASK (0x7F << 10) +#define CTRL_FINE_LOCKED 0x7 #define CTRL_OFFSETD_RESET_VAL 0x8 #define CTRL_OFFSETD_VAL 0x7F -- cgit From ed32522fe048f9edcb3269c8d5af79c6e8c6daea Mon Sep 17 00:00:00 2001 From: Akshay Saraswat Date: Mon, 26 May 2014 19:20:08 +0530 Subject: Exynos5420: DMC: Add software read leveling Sometimes Read DQ and DQS are not in phase. Since, this phase shift differs from board to board, we need to calibrate it at DRAM init phase, that's read DQ calibration. This patch adds SW Read DQ calibration routine to compensate this skew. Signed-off-by: Alim Akhtar Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 250 +++++++++++++++++++++++++++++- arch/arm/cpu/armv7/exynos/exynos5_setup.h | 5 +- arch/arm/include/asm/arch-exynos/dmc.h | 3 + arch/arm/include/asm/arch-exynos/power.h | 4 +- 4 files changed, 255 insertions(+), 7 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c index 13003b86d5..b86dd2d650 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c +++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c @@ -6,6 +6,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include #include @@ -16,7 +17,11 @@ #include "exynos5_setup.h" #include "clock_init.h" -#define TIMEOUT 10000 +#define TIMEOUT_US 10000 +#define NUM_BYTE_LANES 4 +#define DEFAULT_DQS 8 +#define DEFAULT_DQS_X4 (DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \ + || (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0) #ifdef CONFIG_EXYNOS5250 static void reset_phy_ctrl(void) @@ -176,7 +181,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) writel(val, &phy1_ctrl->phy_con1); writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config); - i = TIMEOUT; + i = TIMEOUT_US; while ((readl(&dmc->phystatus) & (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) != (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) { @@ -220,6 +225,219 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) #endif #ifdef CONFIG_EXYNOS5420 +/** + * RAM address to use in the test. + * + * We'll use 4 words at this address and 4 at this address + 0x80 (Ares + * interleaves channels every 128 bytes). This will allow us to evaluate all of + * the chips in a 1 chip per channel (2GB) system and half the chips in a 2 + * chip per channel (4GB) system. We can't test the 2nd chip since we need to + * do tests before the 2nd chip is enabled. Looking at the 2nd chip isn't + * critical because the 1st and 2nd chip have very similar timings (they'd + * better have similar timings, since there's only a single adjustment that is + * shared by both chips). + */ +const unsigned int test_addr = CONFIG_SYS_SDRAM_BASE; + +/* Test pattern with which RAM will be tested */ +static const unsigned int test_pattern[] = { + 0x5a5a5a5a, + 0xa5a5a5a5, + 0xf0f0f0f0, + 0x0f0f0f0f, +}; + +/** + * This function is a test vector for sw read leveling, + * it compares the read data with the written data. + * + * @param ch DMC channel number + * @param byte_lane which DQS byte offset, + * possible values are 0,1,2,3 + * @return TRUE if memory was good, FALSE if not. + */ +static bool dmc_valid_window_test_vector(int ch, int byte_lane) +{ + unsigned int read_data; + unsigned int mask; + int i; + + mask = 0xFF << (8 * byte_lane); + + for (i = 0; i < ARRAY_SIZE(test_pattern); i++) { + read_data = readl(test_addr + i * 4 + ch * 0x80); + if ((read_data & mask) != (test_pattern[i] & mask)) + return false; + } + + return true; +} + +/** + * This function returns current read offset value. + * + * @param phy_ctrl pointer to the current phy controller + */ +static unsigned int dmc_get_read_offset_value(struct exynos5420_phy_control + *phy_ctrl) +{ + return readl(&phy_ctrl->phy_con4); +} + +/** + * This function performs resync, so that slave DLL is updated. + * + * @param phy_ctrl pointer to the current phy controller + */ +static void ddr_phy_set_do_resync(struct exynos5420_phy_control *phy_ctrl) +{ + setbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3); + clrbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3); +} + +/** + * This function sets read offset value register with 'offset'. + * + * ...we also call call ddr_phy_set_do_resync(). + * + * @param phy_ctrl pointer to the current phy controller + * @param offset offset to read DQS + */ +static void dmc_set_read_offset_value(struct exynos5420_phy_control *phy_ctrl, + unsigned int offset) +{ + writel(offset, &phy_ctrl->phy_con4); + ddr_phy_set_do_resync(phy_ctrl); +} + +/** + * Convert a 2s complement byte to a byte with a sign bit. + * + * NOTE: you shouldn't use normal math on the number returned by this function. + * As an example, -10 = 0xf6. After this function -10 = 0x8a. If you wanted + * to do math and get the average of 10 and -10 (should be 0): + * 0x8a + 0xa = 0x94 (-108) + * 0x94 / 2 = 0xca (-54) + * ...and 0xca = sign bit plus 0x4a, or -74 + * + * Also note that you lose the ability to represent -128 since there are two + * representations of 0. + * + * @param b The byte to convert in two's complement. + * @return The 7-bit value + sign bit. + */ + +unsigned char make_signed_byte(signed char b) +{ + if (b < 0) + return 0x80 | -b; + else + return b; +} + +/** + * Test various shifts starting at 'start' and going to 'end'. + * + * For each byte lane, we'll walk through shift starting at 'start' and going + * to 'end' (inclusive). When we are finally able to read the test pattern + * we'll store the value in the results array. + * + * @param phy_ctrl pointer to the current phy controller + * @param ch channel number + * @param start the start shift. -127 to 127 + * @param end the end shift. -127 to 127 + * @param results we'll store results for each byte lane. + */ + +void test_shifts(struct exynos5420_phy_control *phy_ctrl, int ch, + int start, int end, int results[NUM_BYTE_LANES]) +{ + int incr = (start < end) ? 1 : -1; + int byte_lane; + + for (byte_lane = 0; byte_lane < NUM_BYTE_LANES; byte_lane++) { + int shift; + + dmc_set_read_offset_value(phy_ctrl, DEFAULT_DQS_X4); + results[byte_lane] = DEFAULT_DQS; + + for (shift = start; shift != (end + incr); shift += incr) { + unsigned int byte_offsetr; + unsigned int offsetr; + + byte_offsetr = make_signed_byte(shift); + + offsetr = dmc_get_read_offset_value(phy_ctrl); + offsetr &= ~(0xFF << (8 * byte_lane)); + offsetr |= (byte_offsetr << (8 * byte_lane)); + dmc_set_read_offset_value(phy_ctrl, offsetr); + + if (dmc_valid_window_test_vector(ch, byte_lane)) { + results[byte_lane] = shift; + break; + } + } + } +} + +/** + * This function performs SW read leveling to compensate DQ-DQS skew at + * receiver it first finds the optimal read offset value on each DQS + * then applies the value to PHY. + * + * Read offset value has its min margin and max margin. If read offset + * value exceeds its min or max margin, read data will have corruption. + * To avoid this we are doing sw read leveling. + * + * SW read leveling is: + * 1> Finding offset value's left_limit and right_limit + * 2> and calculate its center value + * 3> finally programs that center value to PHY + * 4> then PHY gets its optimal offset value. + * + * @param phy_ctrl pointer to the current phy controller + * @param ch channel number + * @param coarse_lock_val The coarse lock value read from PHY_CON13. + * (0 - 0x7f) + */ +static void software_find_read_offset(struct exynos5420_phy_control *phy_ctrl, + int ch, unsigned int coarse_lock_val) +{ + unsigned int offsetr_cent; + int byte_lane; + int left_limit; + int right_limit; + int left[NUM_BYTE_LANES]; + int right[NUM_BYTE_LANES]; + int i; + + /* Fill the memory with test patterns */ + for (i = 0; i < ARRAY_SIZE(test_pattern); i++) + writel(test_pattern[i], test_addr + i * 4 + ch * 0x80); + + /* Figure out the limits we'll test with; keep -127 < limit < 127 */ + left_limit = DEFAULT_DQS - coarse_lock_val; + right_limit = DEFAULT_DQS + coarse_lock_val; + if (right_limit > 127) + right_limit = 127; + + /* Fill in the location where reads were OK from left and right */ + test_shifts(phy_ctrl, ch, left_limit, right_limit, left); + test_shifts(phy_ctrl, ch, right_limit, left_limit, right); + + /* Make a final value by taking the center between the left and right */ + offsetr_cent = 0; + for (byte_lane = 0; byte_lane < NUM_BYTE_LANES; byte_lane++) { + int temp_center; + unsigned int vmwc; + + temp_center = (left[byte_lane] + right[byte_lane]) / 2; + vmwc = make_signed_byte(temp_center); + offsetr_cent |= vmwc << (8 * byte_lane); + } + dmc_set_read_offset_value(phy_ctrl, offsetr_cent); +} + int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) { struct exynos5420_clock *clk = @@ -229,6 +447,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) struct exynos5420_phy_control *phy0_ctrl, *phy1_ctrl; struct exynos5420_dmc *drex0, *drex1; struct exynos5420_tzasc *tzasc0, *tzasc1; + struct exynos5_power *pmu; uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1; uint32_t lock0_info, lock1_info; int chip; @@ -243,6 +462,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) tzasc0 = (struct exynos5420_tzasc *)samsung_get_base_dmc_tzasc(); tzasc1 = (struct exynos5420_tzasc *)(samsung_get_base_dmc_tzasc() + DMC_OFFSET); + pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE; + /* Enable PAUSE for DREX */ setbits_le32(&clk->pause, ENABLE_BIT); @@ -512,7 +733,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) writel(val, &phy1_ctrl->phy_con1); writel(CTRL_RDLVL_GATE_ENABLE, &drex0->rdlvl_config); - i = TIMEOUT; + i = TIMEOUT_US; while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) != RDLVL_COMPLETE_CHO) && (i > 0)) { /* @@ -527,7 +748,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) writel(CTRL_RDLVL_GATE_DISABLE, &drex0->rdlvl_config); writel(CTRL_RDLVL_GATE_ENABLE, &drex1->rdlvl_config); - i = TIMEOUT; + i = TIMEOUT_US; while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) != RDLVL_COMPLETE_CHO) && (i > 0)) { /* @@ -561,6 +782,27 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) setbits_le32(&phy1_ctrl->phy_con2, DLL_DESKEW_EN); } + /* + * Do software read leveling + * + * Do this before we turn on auto refresh since the auto refresh can + * be in conflict with the resync operation that's part of setting + * read leveling. + */ + if (!reset) { + /* restore calibrated value after resume */ + dmc_set_read_offset_value(phy0_ctrl, readl(&pmu->pmu_spare1)); + dmc_set_read_offset_value(phy1_ctrl, readl(&pmu->pmu_spare2)); + } else { + software_find_read_offset(phy0_ctrl, 0, + CTRL_LOCK_COARSE(lock0_info)); + software_find_read_offset(phy1_ctrl, 1, + CTRL_LOCK_COARSE(lock1_info)); + /* save calibrated value to restore after resume */ + writel(dmc_get_read_offset_value(phy0_ctrl), &pmu->pmu_spare1); + writel(dmc_get_read_offset_value(phy1_ctrl), &pmu->pmu_spare2); + } + /* Send PALL command */ dmc_config_prech(mem, &drex0->directcmd); dmc_config_prech(mem, &drex1->directcmd); diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h index d415c91f3a..d91e585ea6 100644 --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h @@ -282,8 +282,11 @@ #define PHY_CON12_VAL 0x10107F50 #define CTRL_START (1 << 6) #define CTRL_DLL_ON (1 << 5) +#define CTRL_LOCK_COARSE_OFFSET 10 +#define CTRL_LOCK_COARSE_MASK (0x7F << CTRL_LOCK_COARSE_OFFSET) +#define CTRL_LOCK_COARSE(x) (((x) & CTRL_LOCK_COARSE_MASK) >> \ + CTRL_LOCK_COARSE_OFFSET) #define CTRL_FORCE_MASK (0x7F << 8) -#define CTRL_LOCK_COARSE_MASK (0x7F << 10) #define CTRL_FINE_LOCKED 0x7 #define CTRL_OFFSETD_RESET_VAL 0x8 diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h index d78536d2df..ec3f9b6ee1 100644 --- a/arch/arm/include/asm/arch-exynos/dmc.h +++ b/arch/arm/include/asm/arch-exynos/dmc.h @@ -467,6 +467,9 @@ enum mem_manuf { /* PHY_CON1 register fields */ #define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0 +/* PHY_CON4 rgister fields */ +#define PHY_CON10_CTRL_OFFSETR3 (1 << 24) + /* PHY_CON12 register fields */ #define PHY_CON12_CTRL_START_POINT_SHIFT 24 #define PHY_CON12_CTRL_INC_SHIFT 16 diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h index a4b41adca9..4f2447b3f8 100644 --- a/arch/arm/include/asm/arch-exynos/power.h +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -906,8 +906,8 @@ struct exynos5420_power { unsigned int sysip_dat3; unsigned char res11[0xe0]; unsigned int pmu_spare0; - unsigned int pmu_spare1; - unsigned int pmu_spare2; + unsigned int pmu_spare1; /* Store PHY0_CON4 for read leveling */ + unsigned int pmu_spare2; /* Store PHY1_CON4 for read leveling */ unsigned int pmu_spare3; unsigned char res12[0x4]; unsigned int cg_status0; -- cgit From d337a09c30a04d14e2c35b7517105c6b2e3e48dd Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Mon, 19 May 2014 19:51:28 +0800 Subject: ARMv7: at91: enable ICache and DCache. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For at91 armv7 SoC (SAMA5D3x), only LCD and macb used DMA. Now as the lcd and macb driver already support dcache. So we can enable dcache now. Also we can enable icache without any problem. Signed-off-by: Josh Wu Signed-off-by: Andreas Bießmann --- arch/arm/cpu/armv7/at91/cpu.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/at91/cpu.c b/arch/arm/cpu/armv7/at91/cpu.c index 2fbf60d542..8d86f97e3d 100644 --- a/arch/arm/cpu/armv7/at91/cpu.c +++ b/arch/arm/cpu/armv7/at91/cpu.c @@ -61,6 +61,8 @@ int print_cpuinfo(void) void enable_caches(void) { + icache_enable(); + dcache_enable(); } unsigned int get_chip_id(void) -- cgit From a811db5a8c557138e4d22000aca4ce7f6c3b25b5 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 5 Jun 2014 19:47:45 +0900 Subject: arm: zynq: fix a bug in Zynq linker script Commit 41623c91 moved exception handlers to ".vectores" section but it missed to adjust Zynq linker script. Zynq boards hang up after relocation because "_start" symbol does not point to the correct address and gd->relocaddr gets insane. Signed-off-by: Masahiro Yamada Cc: Albert ARIBAUD Cc: Michal Simek Tested-by: Michal Simek Signed-off-by: Michal Simek --- arch/arm/cpu/armv7/zynq/u-boot.lds | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/zynq/u-boot.lds b/arch/arm/cpu/armv7/zynq/u-boot.lds index 69500a64e2..4dc9bb0102 100644 --- a/arch/arm/cpu/armv7/zynq/u-boot.lds +++ b/arch/arm/cpu/armv7/zynq/u-boot.lds @@ -18,6 +18,7 @@ SECTIONS .text : { *(.__image_copy_start) + *(.vectors) CPUDIR/start.o (.text*) *(.text*) } -- cgit From bad40e089f2c1a0e42fa659611f85028c872cb96 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 5 Jun 2014 19:31:30 -0300 Subject: mx6: Fix definition of IOMUXC_GPR12_DEVICE_TYPE_RC mx6 reference manual incorrectly states that the DEVICE_TYPE field of IOMUXC_GPR12 register should be configured as '0010' for setting the PCI controller in RC mode. The correct value should be '0100' instead. This also aligns with the same value used in the mx6 pci kernel driver. Signed-off-by: Fabio Estevam Acked-by: Marek Vasut Acked-by: Stefano Babic --- arch/arm/include/asm/arch-mx6/iomux.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h index f9ee0d9839..6a4a632199 100644 --- a/arch/arm/include/asm/arch-mx6/iomux.h +++ b/arch/arm/include/asm/arch-mx6/iomux.h @@ -39,7 +39,7 @@ #define IOMUXC_GPR12_LOS_LEVEL_MASK (0x1f << 4) #define IOMUXC_GPR12_APPS_LTSSM_ENABLE (1 << 10) #define IOMUXC_GPR12_DEVICE_TYPE_EP (0x0 << 12) -#define IOMUXC_GPR12_DEVICE_TYPE_RC (0x2 << 12) +#define IOMUXC_GPR12_DEVICE_TYPE_RC (0x4 << 12) #define IOMUXC_GPR12_DEVICE_TYPE_MASK (0xf << 12) /* -- cgit From f2f07e8553185022b16adb91581700c86dc3a09a Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 10 Jun 2014 10:26:22 +0200 Subject: imx: correct HAB status for new chip TO According to: http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/log/?h=imx_v2009.08_3.0.35_4.1.0 ENGR00287268 mx6: fix the secure boot issue on the new tapout chip commit 424cb1a79e9f5ae4ede9350dfb5e10dc9680e90b newer i.MX6 silicon revisions have an updated ROM and HAB API table. Please see also: i.MX Applications Processors Documentation Engineering Bulletins EB803, i.MX 6Dual/6Quad Applications Processor Silicon Revsion 1.2 to 1.3 Comparison With this change the secure boot status is correctly displayed Signed-off-by: Stefano Babic --- arch/arm/cpu/armv7/mx6/hab.c | 73 ++++++++++++++++++++++++++++--- arch/arm/include/asm/arch-mx6/hab.h | 17 ++++--- arch/arm/include/asm/arch-mx6/imx-regs.h | 2 + arch/arm/include/asm/arch-mx6/sys_proto.h | 4 +- 4 files changed, 82 insertions(+), 14 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/mx6/hab.c b/arch/arm/cpu/armv7/mx6/hab.c index 5187775365..f6810a680d 100644 --- a/arch/arm/cpu/armv7/mx6/hab.c +++ b/arch/arm/cpu/armv7/mx6/hab.c @@ -7,15 +7,69 @@ #include #include #include +#include /* -------- start of HAB API updates ------------*/ -#define hab_rvt_report_event ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT) -#define hab_rvt_report_status ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS) -#define hab_rvt_authenticate_image \ - ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE) -#define hab_rvt_entry ((hab_rvt_entry_t *)HAB_RVT_ENTRY) -#define hab_rvt_exit ((hab_rvt_exit_t *)HAB_RVT_EXIT) -#define hab_rvt_clock_init HAB_RVT_CLOCK_INIT + +#define hab_rvt_report_event_p \ +( \ + ((is_cpu_type(MXC_CPU_MX6Q) || \ + is_cpu_type(MXC_CPU_MX6D)) && \ + (soc_rev() >= CHIP_REV_1_5)) ? \ + ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \ + (is_cpu_type(MXC_CPU_MX6DL) && \ + (soc_rev() >= CHIP_REV_1_2)) ? \ + ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \ + ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT) \ +) + +#define hab_rvt_report_status_p \ +( \ + ((is_cpu_type(MXC_CPU_MX6Q) || \ + is_cpu_type(MXC_CPU_MX6D)) && \ + (soc_rev() >= CHIP_REV_1_5)) ? \ + ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\ + (is_cpu_type(MXC_CPU_MX6DL) && \ + (soc_rev() >= CHIP_REV_1_2)) ? \ + ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\ + ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS) \ +) + +#define hab_rvt_authenticate_image_p \ +( \ + ((is_cpu_type(MXC_CPU_MX6Q) || \ + is_cpu_type(MXC_CPU_MX6D)) && \ + (soc_rev() >= CHIP_REV_1_5)) ? \ + ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \ + (is_cpu_type(MXC_CPU_MX6DL) && \ + (soc_rev() >= CHIP_REV_1_2)) ? \ + ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \ + ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE) \ +) + +#define hab_rvt_entry_p \ +( \ + ((is_cpu_type(MXC_CPU_MX6Q) || \ + is_cpu_type(MXC_CPU_MX6D)) && \ + (soc_rev() >= CHIP_REV_1_5)) ? \ + ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \ + (is_cpu_type(MXC_CPU_MX6DL) && \ + (soc_rev() >= CHIP_REV_1_2)) ? \ + ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \ + ((hab_rvt_entry_t *)HAB_RVT_ENTRY) \ +) + +#define hab_rvt_exit_p \ +( \ + ((is_cpu_type(MXC_CPU_MX6Q) || \ + is_cpu_type(MXC_CPU_MX6D)) && \ + (soc_rev() >= CHIP_REV_1_5)) ? \ + ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \ + (is_cpu_type(MXC_CPU_MX6DL) && \ + (soc_rev() >= CHIP_REV_1_2)) ? \ + ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \ + ((hab_rvt_exit_t *)HAB_RVT_EXIT) \ +) bool is_hab_enabled(void) { @@ -52,6 +106,11 @@ int get_hab_status(void) size_t bytes = sizeof(event_data); /* Event size in bytes */ enum hab_config config = 0; enum hab_state state = 0; + hab_rvt_report_event_t *hab_rvt_report_event; + hab_rvt_report_status_t *hab_rvt_report_status; + + hab_rvt_report_event = hab_rvt_report_event_p; + hab_rvt_report_status = hab_rvt_report_status_p; if (is_hab_enabled()) puts("\nSecure boot enabled\n"); diff --git a/arch/arm/include/asm/arch-mx6/hab.h b/arch/arm/include/asm/arch-mx6/hab.h index d724f206f0..1f12695f67 100644 --- a/arch/arm/include/asm/arch-mx6/hab.h +++ b/arch/arm/include/asm/arch-mx6/hab.h @@ -53,12 +53,17 @@ typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t, void **, size_t *, hab_loader_callback_f_t); typedef void hapi_clock_init_t(void); -#define HAB_RVT_REPORT_EVENT (*(uint32_t *)0x000000B4) -#define HAB_RVT_REPORT_STATUS (*(uint32_t *)0x000000B8) -#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x000000A4) -#define HAB_RVT_ENTRY (*(uint32_t *)0x00000098) -#define HAB_RVT_EXIT (*(uint32_t *)0x0000009C) -#define HAB_RVT_CLOCK_INIT ((hapi_clock_init_t *)0x0000024D) +#define HAB_RVT_REPORT_EVENT (*(uint32_t *)0x000000B4) +#define HAB_RVT_REPORT_STATUS (*(uint32_t *)0x000000B8) +#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x000000A4) +#define HAB_RVT_ENTRY (*(uint32_t *)0x00000098) +#define HAB_RVT_EXIT (*(uint32_t *)0x0000009C) + +#define HAB_RVT_REPORT_EVENT_NEW (*(uint32_t *)0x000000B8) +#define HAB_RVT_REPORT_STATUS_NEW (*(uint32_t *)0x000000BC) +#define HAB_RVT_AUTHENTICATE_IMAGE_NEW (*(uint32_t *)0x000000A8) +#define HAB_RVT_ENTRY_NEW (*(uint32_t *)0x0000009C) +#define HAB_RVT_EXIT_NEW (*(uint32_t *)0x000000A0) #define HAB_CID_ROM 0 /**< ROM Caller ID */ #define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 1f19727b58..a69a7530c3 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -217,6 +217,8 @@ #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) #define CHIP_REV_1_0 0x10 +#define CHIP_REV_1_2 0x12 +#define CHIP_REV_1_5 0x15 #define IRAM_SIZE 0x00040000 #define FEC_QUIRK_ENET_MAC diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index 38851a135c..42d30f5021 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -11,7 +11,9 @@ #include #include "../arch-imx/cpu.h" -#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) +#define soc_rev() (get_cpu_rev() & 0xFF) +#define is_soc_rev(rev) (soc_rev() - rev) + u32 get_cpu_rev(void); /* returns MXC_CPU_ value */ -- cgit From c42ff090e41d4b9e50faa727bac490ee790f82f4 Mon Sep 17 00:00:00 2001 From: Jeroen Hofstee Date: Wed, 11 Jun 2014 23:12:28 +0200 Subject: tegra20: display: fix checking of return value The calling code seems a bit in doubt about the return value of fdtdec_lookup_phandle. Since it returns a negative value on error (and fdt_node_offset_by_phandle as well), check for that. cc: Wei Ni Signed-off-by: Jeroen Hofstee Tested-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/cpu/armv7/tegra20/display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/tegra20/display.c b/arch/arm/cpu/armv7/tegra20/display.c index 488f0c639d..fd77f3f0ef 100644 --- a/arch/arm/cpu/armv7/tegra20/display.c +++ b/arch/arm/cpu/armv7/tegra20/display.c @@ -328,7 +328,7 @@ static int tegra_display_decode_config(const void *blob, rgb = fdt_subnode_offset(blob, node, "rgb"); config->panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel"); - if (!config->panel_node < 0) { + if (config->panel_node < 0) { debug("%s: Cannot find panel information\n", __func__); return -1; } -- cgit From 2868a5dff373f6d173ba2d060bbe910c38254cbf Mon Sep 17 00:00:00 2001 From: Ash Charles Date: Fri, 6 Jun 2014 11:27:28 -0700 Subject: omap: Don't enable GPMC CS0 with nothing attached If CONFIG_(NAND|NOR|ONENAND) is not defined, no configuration is set for GPMC on chip select #0---size is 0. In this case, the GPMC configuration should be reset but not enabled. Enabling causes the Gumstix DuoVero board to hang when entering Linux. Signed-off-by: Ash Charles [trini: Switch to testing base as GPMC_SIZE_256M is 0x0] Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/omap-common/mem-common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c index 944ef840a1..11be480abd 100644 --- a/arch/arm/cpu/armv7/omap-common/mem-common.c +++ b/arch/arm/cpu/armv7/omap-common/mem-common.c @@ -133,5 +133,6 @@ void gpmc_init(void) writel(0, &gpmc_cfg->cs[0].config7); sdelay(1000); /* enable chip-select specific configurations */ - enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size); + if (base != 0) + enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size); } -- cgit From 3e01ed00da98a29fe2b71c6d60309d5b09adc0de Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Sat, 7 Jun 2014 04:22:52 +0300 Subject: mtd: nand: davinci: add header file for driver definitions The definitions inside emif_defs.h concern davinci nand driver and should be in it's header. So create header file for davinci nand driver and move definitions from emif_defs.h and nand_defs.h to it. Acked-by: Vitaly Andrianov Signed-off-by: Ivan Khoronzhuk [trini: Fixup more davinci breakage] Signed-off-by: Tom Rini --- arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c | 2 +- arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c | 1 + arch/arm/cpu/armv7/keystone/aemif.c | 2 +- arch/arm/include/asm/arch-davinci/emif_defs.h | 72 ------------------ arch/arm/include/asm/arch-davinci/hardware.h | 1 - arch/arm/include/asm/arch-davinci/nand_defs.h | 38 ---------- arch/arm/include/asm/arch-keystone/emif_defs.h | 73 ------------------ arch/arm/include/asm/arch-keystone/nand_defs.h | 23 ------ arch/arm/include/asm/arch-tnetv107x/emif_defs.h | 1 - arch/arm/include/asm/arch-tnetv107x/hardware.h | 2 + arch/arm/include/asm/arch-tnetv107x/nand_defs.h | 23 ------ arch/arm/include/asm/ti-common/davinci_nand.h | 98 +++++++++++++++++++++++++ 12 files changed, 103 insertions(+), 233 deletions(-) delete mode 100644 arch/arm/include/asm/arch-davinci/emif_defs.h delete mode 100644 arch/arm/include/asm/arch-davinci/nand_defs.h delete mode 100644 arch/arm/include/asm/arch-keystone/emif_defs.h delete mode 100644 arch/arm/include/asm/arch-keystone/nand_defs.h delete mode 100644 arch/arm/include/asm/arch-tnetv107x/emif_defs.h delete mode 100644 arch/arm/include/asm/arch-tnetv107x/nand_defs.h create mode 100644 arch/arm/include/asm/ti-common/davinci_nand.h (limited to 'arch/arm') diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c index b91e948ce3..19730cef8c 100644 --- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c +++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include void davinci_enable_uart0(void) diff --git a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c index ee096fe721..c8b44988d3 100644 --- a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c +++ b/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/cpu/armv7/keystone/aemif.c b/arch/arm/cpu/armv7/keystone/aemif.c index 9b26886dba..bcbb95aa44 100644 --- a/arch/arm/cpu/armv7/keystone/aemif.c +++ b/arch/arm/cpu/armv7/keystone/aemif.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #define AEMIF_CFG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0) #define AEMIF_CFG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0) diff --git a/arch/arm/include/asm/arch-davinci/emif_defs.h b/arch/arm/include/asm/arch-davinci/emif_defs.h deleted file mode 100644 index 7e19cfeed4..0000000000 --- a/arch/arm/include/asm/arch-davinci/emif_defs.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _EMIF_DEFS_H_ -#define _EMIF_DEFS_H_ - -#include - -struct davinci_emif_regs { - u_int32_t ercsr; - u_int32_t awccr; - u_int32_t sdbcr; - u_int32_t sdrcr; - u_int32_t ab1cr; - u_int32_t ab2cr; - u_int32_t ab3cr; - u_int32_t ab4cr; - u_int32_t sdtimr; - u_int32_t ddrsr; - u_int32_t ddrphycr; - u_int32_t ddrphysr; - u_int32_t totar; - u_int32_t totactr; - u_int32_t ddrphyid_rev; - u_int32_t sdsretr; - u_int32_t eirr; - u_int32_t eimr; - u_int32_t eimsr; - u_int32_t eimcr; - u_int32_t ioctrlr; - u_int32_t iostatr; - u_int8_t rsvd0[8]; - u_int32_t nandfcr; - u_int32_t nandfsr; - u_int8_t rsvd1[8]; - u_int32_t nandfecc[4]; - u_int8_t rsvd2[60]; - u_int32_t nand4biteccload; - u_int32_t nand4bitecc[4]; - u_int32_t nanderradd1; - u_int32_t nanderradd2; - u_int32_t nanderrval1; - u_int32_t nanderrval2; -}; - -#define davinci_emif_regs \ - ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE) - -#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << (n-2)) -#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) -#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) ((n-2) << 4) -#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2))) -#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) -#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) -#define DAVINCI_NANDFCR_CS2NAND (1 << 0) - -/* Chip Select setup */ -#define DAVINCI_ABCR_STROBE_SELECT (1 << 31) -#define DAVINCI_ABCR_EXT_WAIT (1 << 30) -#define DAVINCI_ABCR_WSETUP(n) (n << 26) -#define DAVINCI_ABCR_WSTROBE(n) (n << 20) -#define DAVINCI_ABCR_WHOLD(n) (n << 17) -#define DAVINCI_ABCR_RSETUP(n) (n << 13) -#define DAVINCI_ABCR_RSTROBE(n) (n << 7) -#define DAVINCI_ABCR_RHOLD(n) (n << 4) -#define DAVINCI_ABCR_TA(n) (n << 2) -#define DAVINCI_ABCR_ASIZE_16BIT 1 -#define DAVINCI_ABCR_ASIZE_8BIT 0 - -#endif diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 98fe56e686..a4eb0bd89b 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -597,7 +597,6 @@ static inline enum davinci_clk_ids get_async3_src(void) #if defined(CONFIG_SOC_DM365) #include #include -#include #include #include #include diff --git a/arch/arm/include/asm/arch-davinci/nand_defs.h b/arch/arm/include/asm/arch-davinci/nand_defs.h deleted file mode 100644 index dee1c6f814..0000000000 --- a/arch/arm/include/asm/arch-davinci/nand_defs.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (C) 2007 Sergey Kubushyn - * - * Parts shamelesly stolen from Linux Kernel source tree. - * - * ------------------------------------------------------------ - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _NAND_DEFS_H_ -#define _NAND_DEFS_H_ - -#include - -#ifdef CONFIG_SOC_DM646X -#define MASK_CLE 0x80000 -#define MASK_ALE 0x40000 -#else -#define MASK_CLE 0x10 -#define MASK_ALE 0x08 -#endif - -#ifdef CONFIG_SYS_NAND_MASK_CLE -#undef MASK_CLE -#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE -#endif -#ifdef CONFIG_SYS_NAND_MASK_ALE -#undef MASK_ALE -#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE -#endif - -#define NAND_READ_START 0x00 -#define NAND_READ_END 0x30 -#define NAND_STATUS 0x70 - -extern void davinci_nand_init(struct nand_chip *nand); - -#endif diff --git a/arch/arm/include/asm/arch-keystone/emif_defs.h b/arch/arm/include/asm/arch-keystone/emif_defs.h deleted file mode 100644 index a3378aa30e..0000000000 --- a/arch/arm/include/asm/arch-keystone/emif_defs.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * emif definitions to re-use davinci emif driver on Keystone2 - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - * (C) Copyright 2007 Sergey Kubushyn - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _EMIF_DEFS_H_ -#define _EMIF_DEFS_H_ - -#include - -struct davinci_emif_regs { - uint32_t ercsr; - uint32_t awccr; - uint32_t sdbcr; - uint32_t sdrcr; - uint32_t abncr[4]; - uint32_t sdtimr; - uint32_t ddrsr; - uint32_t ddrphycr; - uint32_t ddrphysr; - uint32_t totar; - uint32_t totactr; - uint32_t ddrphyid_rev; - uint32_t sdsretr; - uint32_t eirr; - uint32_t eimr; - uint32_t eimsr; - uint32_t eimcr; - uint32_t ioctrlr; - uint32_t iostatr; - uint32_t rsvd0; - uint32_t one_nand_cr; - uint32_t nandfcr; - uint32_t nandfsr; - uint32_t rsvd1[2]; - uint32_t nandfecc[4]; - uint32_t rsvd2[15]; - uint32_t nand4biteccload; - uint32_t nand4bitecc[4]; - uint32_t nanderradd1; - uint32_t nanderradd2; - uint32_t nanderrval1; - uint32_t nanderrval2; -}; - -#define davinci_emif_regs \ - ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE) - -#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << ((n) - 2)) -#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) -#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) (((n) - 2) << 4) -#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2))) -#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) -#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) - -/* Chip Select setup */ -#define DAVINCI_ABCR_STROBE_SELECT (1 << 31) -#define DAVINCI_ABCR_EXT_WAIT (1 << 30) -#define DAVINCI_ABCR_WSETUP(n) ((n) << 26) -#define DAVINCI_ABCR_WSTROBE(n) ((n) << 20) -#define DAVINCI_ABCR_WHOLD(n) ((n) << 17) -#define DAVINCI_ABCR_RSETUP(n) ((n) << 13) -#define DAVINCI_ABCR_RSTROBE(n) ((n) << 7) -#define DAVINCI_ABCR_RHOLD(n) ((n) << 4) -#define DAVINCI_ABCR_TA(n) ((n) << 2) -#define DAVINCI_ABCR_ASIZE_16BIT 1 -#define DAVINCI_ABCR_ASIZE_8BIT 0 - -#endif diff --git a/arch/arm/include/asm/arch-keystone/nand_defs.h b/arch/arm/include/asm/arch-keystone/nand_defs.h deleted file mode 100644 index 58417dbc0b..0000000000 --- a/arch/arm/include/asm/arch-keystone/nand_defs.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * nand driver definitions to re-use davinci nand driver on Keystone2 - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - * (C) Copyright 2007 Sergey Kubushyn - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _NAND_DEFS_H_ -#define _NAND_DEFS_H_ - -#include -#include - -#define MASK_CLE 0x4000 -#define MASK_ALE 0x2000 - -#define NAND_READ_START 0x00 -#define NAND_READ_END 0x30 -#define NAND_STATUS 0x70 - -#endif diff --git a/arch/arm/include/asm/arch-tnetv107x/emif_defs.h b/arch/arm/include/asm/arch-tnetv107x/emif_defs.h deleted file mode 100644 index 9969a018e7..0000000000 --- a/arch/arm/include/asm/arch-tnetv107x/emif_defs.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/arm/include/asm/arch-tnetv107x/hardware.h b/arch/arm/include/asm/arch-tnetv107x/hardware.h index 2a7ca4e00c..d458e0bdf0 100644 --- a/arch/arm/include/asm/arch-tnetv107x/hardware.h +++ b/arch/arm/include/asm/arch-tnetv107x/hardware.h @@ -155,4 +155,6 @@ int wdt_kick(void); #define INTC_HINT_EN (TNETV107X_INTC_BASE + 0x1500) #define INTC_EN_CLR0 (TNETV107X_INTC_BASE + 0x380) +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE + #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-tnetv107x/nand_defs.h b/arch/arm/include/asm/arch-tnetv107x/nand_defs.h deleted file mode 100644 index b298fba905..0000000000 --- a/arch/arm/include/asm/arch-tnetv107x/nand_defs.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * TNETV107X: NAND definitions - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _NAND_DEFS_H_ -#define _NAND_DEFS_H_ - -#include -#include - -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE - -#define MASK_CLE 0x4000 -#define MASK_ALE 0x2000 - -#define NAND_READ_START 0x00 -#define NAND_READ_END 0x30 -#define NAND_STATUS 0x70 - -extern void davinci_nand_init(struct nand_chip *nand); - -#endif diff --git a/arch/arm/include/asm/ti-common/davinci_nand.h b/arch/arm/include/asm/ti-common/davinci_nand.h new file mode 100644 index 0000000000..11407be144 --- /dev/null +++ b/arch/arm/include/asm/ti-common/davinci_nand.h @@ -0,0 +1,98 @@ +/* + * NAND Flash Driver + * + * Copyright (C) 2006-2014 Texas Instruments. + * + * Based on Linux DaVinci NAND driver by TI. + */ + +#ifndef _DAVINCI_NAND_H_ +#define _DAVINCI_NAND_H_ + +#include +#include + +#define NAND_READ_START 0x00 +#define NAND_READ_END 0x30 +#define NAND_STATUS 0x70 + +#define MASK_CLE 0x10 +#define MASK_ALE 0x08 + +#ifdef CONFIG_SYS_NAND_MASK_CLE +#undef MASK_CLE +#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE +#endif +#ifdef CONFIG_SYS_NAND_MASK_ALE +#undef MASK_ALE +#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE +#endif + +struct davinci_emif_regs { + uint32_t ercsr; + uint32_t awccr; + uint32_t sdbcr; + uint32_t sdrcr; + union { + uint32_t abncr[4]; + uint32_t ab1cr; + uint32_t ab2cr; + uint32_t ab3cr; + uint32_t ab4cr; + }; + uint32_t sdtimr; + uint32_t ddrsr; + uint32_t ddrphycr; + uint32_t ddrphysr; + uint32_t totar; + uint32_t totactr; + uint32_t ddrphyid_rev; + uint32_t sdsretr; + uint32_t eirr; + uint32_t eimr; + uint32_t eimsr; + uint32_t eimcr; + uint32_t ioctrlr; + uint32_t iostatr; + uint32_t rsvd0; + uint32_t one_nand_cr; + uint32_t nandfcr; + uint32_t nandfsr; + uint32_t rsvd1[2]; + uint32_t nandfecc[4]; + uint32_t rsvd2[15]; + uint32_t nand4biteccload; + uint32_t nand4bitecc[4]; + uint32_t nanderradd1; + uint32_t nanderradd2; + uint32_t nanderrval1; + uint32_t nanderrval2; +}; + +#define davinci_emif_regs \ + ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE) + +#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << ((n) - 2)) +#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) +#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) (((n) - 2) << 4) +#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2))) +#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) +#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) +#define DAVINCI_NANDFCR_CS2NAND (1 << 0) + +/* Chip Select setup */ +#define DAVINCI_ABCR_STROBE_SELECT (1 << 31) +#define DAVINCI_ABCR_EXT_WAIT (1 << 30) +#define DAVINCI_ABCR_WSETUP(n) (n << 26) +#define DAVINCI_ABCR_WSTROBE(n) (n << 20) +#define DAVINCI_ABCR_WHOLD(n) (n << 17) +#define DAVINCI_ABCR_RSETUP(n) (n << 13) +#define DAVINCI_ABCR_RSTROBE(n) (n << 7) +#define DAVINCI_ABCR_RHOLD(n) (n << 4) +#define DAVINCI_ABCR_TA(n) (n << 2) +#define DAVINCI_ABCR_ASIZE_16BIT 1 +#define DAVINCI_ABCR_ASIZE_8BIT 0 + +void davinci_nand_init(struct nand_chip *nand); + +#endif -- cgit From 909ea9aa264423c99cd3039475c98f4a069cb7a4 Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Sat, 7 Jun 2014 05:10:49 +0300 Subject: ARM: keystone: aemif: move aemif driver to drivers/memory/ti-aemif.c Move AEMIF driver to drivers/memory/ti-aemif.c along with AEMIF definitions collected in arch/arm/include/asm/ti-common/ti-aemif.h Acked-by: Vitaly Andrianov Signed-off-by: Ivan Khoronzhuk --- arch/arm/cpu/armv7/keystone/Makefile | 1 - arch/arm/cpu/armv7/keystone/aemif.c | 71 ---------------------- arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 7 --- arch/arm/include/asm/arch-keystone/hardware.h | 30 ++------- arch/arm/include/asm/ti-common/ti-aemif.h | 39 ++++++++++++ 5 files changed, 43 insertions(+), 105 deletions(-) delete mode 100644 arch/arm/cpu/armv7/keystone/aemif.c create mode 100644 arch/arm/include/asm/ti-common/ti-aemif.h (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile index b1bd0224ea..c4af252110 100644 --- a/arch/arm/cpu/armv7/keystone/Makefile +++ b/arch/arm/cpu/armv7/keystone/Makefile @@ -5,7 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += aemif.o obj-y += init.o obj-y += psc.o obj-y += clock.o diff --git a/arch/arm/cpu/armv7/keystone/aemif.c b/arch/arm/cpu/armv7/keystone/aemif.c deleted file mode 100644 index bcbb95aa44..0000000000 --- a/arch/arm/cpu/armv7/keystone/aemif.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Keystone2: Asynchronous EMIF Configuration - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#define AEMIF_CFG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0) -#define AEMIF_CFG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0) -#define AEMIF_CFG_WR_SETUP(v) (((v) & 0x0f) << 26) -#define AEMIF_CFG_WR_STROBE(v) (((v) & 0x3f) << 20) -#define AEMIF_CFG_WR_HOLD(v) (((v) & 0x07) << 17) -#define AEMIF_CFG_RD_SETUP(v) (((v) & 0x0f) << 13) -#define AEMIF_CFG_RD_STROBE(v) (((v) & 0x3f) << 7) -#define AEMIF_CFG_RD_HOLD(v) (((v) & 0x07) << 4) -#define AEMIF_CFG_TURN_AROUND(v) (((v) & 0x03) << 2) -#define AEMIF_CFG_WIDTH(v) (((v) & 0x03) << 0) - -#define set_config_field(reg, field, val) \ - do { \ - if (val != -1) { \ - reg &= ~AEMIF_CFG_##field(0xffffffff); \ - reg |= AEMIF_CFG_##field(val); \ - } \ - } while (0) - -void configure_async_emif(int cs, struct async_emif_config *cfg) -{ - unsigned long tmp; - - if (cfg->mode == ASYNC_EMIF_MODE_NAND) { - tmp = __raw_readl(&davinci_emif_regs->nandfcr); - tmp |= (1 << cs); - __raw_writel(tmp, &davinci_emif_regs->nandfcr); - - } else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) { - tmp = __raw_readl(&davinci_emif_regs->one_nand_cr); - tmp |= (1 << cs); - __raw_writel(tmp, &davinci_emif_regs->one_nand_cr); - } - - tmp = __raw_readl(&davinci_emif_regs->abncr[cs]); - - set_config_field(tmp, SELECT_STROBE, cfg->select_strobe); - set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait); - set_config_field(tmp, WR_SETUP, cfg->wr_setup); - set_config_field(tmp, WR_STROBE, cfg->wr_strobe); - set_config_field(tmp, WR_HOLD, cfg->wr_hold); - set_config_field(tmp, RD_SETUP, cfg->rd_setup); - set_config_field(tmp, RD_STROBE, cfg->rd_strobe); - set_config_field(tmp, RD_HOLD, cfg->rd_hold); - set_config_field(tmp, TURN_AROUND, cfg->turn_around); - set_config_field(tmp, WIDTH, cfg->width); - - __raw_writel(tmp, &davinci_emif_regs->abncr[cs]); -} - -void init_async_emif(int num_cs, struct async_emif_config *config) -{ - int cs; - - for (cs = 0; cs < num_cs; cs++) - configure_async_emif(cs, config + cs); -} diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h index 7ac2662f1f..50ce649d4c 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h @@ -9,13 +9,6 @@ #ifndef __ASM_ARCH_HARDWARE_K2HK_H #define __ASM_ARCH_HARDWARE_K2HK_H -#define K2HK_ASYNC_EMIF_CNTRL_BASE 0x21000a00 -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE K2HK_ASYNC_EMIF_CNTRL_BASE -#define K2HK_ASYNC_EMIF_DATA_CE0_BASE 0x30000000 -#define K2HK_ASYNC_EMIF_DATA_CE1_BASE 0x34000000 -#define K2HK_ASYNC_EMIF_DATA_CE2_BASE 0x38000000 -#define K2HK_ASYNC_EMIF_DATA_CE3_BASE 0x3c000000 - #define K2HK_PLL_CNTRL_BASE 0x02310000 #define CLOCK_BASE K2HK_PLL_CNTRL_BASE #define KS2_RSTCTRL (K2HK_PLL_CNTRL_BASE + 0xe8) diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index 6c532ca870..ffdecbfcd6 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -22,32 +22,6 @@ typedef volatile unsigned int dv_reg; typedef volatile unsigned int *dv_reg_p; -#define ASYNC_EMIF_NUM_CS 4 -#define ASYNC_EMIF_MODE_NOR 0 -#define ASYNC_EMIF_MODE_NAND 1 -#define ASYNC_EMIF_MODE_ONENAND 2 -#define ASYNC_EMIF_PRESERVE -1 - -struct async_emif_config { - unsigned mode; - unsigned select_strobe; - unsigned extend_wait; - unsigned wr_setup; - unsigned wr_strobe; - unsigned wr_hold; - unsigned rd_setup; - unsigned rd_strobe; - unsigned rd_hold; - unsigned turn_around; - enum { - ASYNC_EMIF_8 = 0, - ASYNC_EMIF_16 = 1, - ASYNC_EMIF_32 = 2, - } width; -}; - -void init_async_emif(int num_cs, struct async_emif_config *config); - struct ddr3_phy_config { unsigned int pllcr; unsigned int pgcr1_mask; @@ -145,6 +119,10 @@ struct ddr3_emif_config { #define KS2_UART0_BASE 0x02530c00 #define KS2_UART1_BASE 0x02531000 +/* AEMIF */ +#define KS2_AEMIF_CNTRL_BASE 0x21000a00 +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE + #ifdef CONFIG_SOC_K2HK #include #endif diff --git a/arch/arm/include/asm/ti-common/ti-aemif.h b/arch/arm/include/asm/ti-common/ti-aemif.h new file mode 100644 index 0000000000..4a311d4a2f --- /dev/null +++ b/arch/arm/include/asm/ti-common/ti-aemif.h @@ -0,0 +1,39 @@ +/* + * AEMIF definitions + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _AEMIF_H_ +#define _AEMIF_H_ + +#define AEMIF_NUM_CS 4 +#define AEMIF_MODE_NOR 0 +#define AEMIF_MODE_NAND 1 +#define AEMIF_MODE_ONENAND 2 +#define AEMIF_PRESERVE -1 + +struct aemif_config { + unsigned mode; + unsigned select_strobe; + unsigned extend_wait; + unsigned wr_setup; + unsigned wr_strobe; + unsigned wr_hold; + unsigned rd_setup; + unsigned rd_strobe; + unsigned rd_hold; + unsigned turn_around; + enum { + AEMIF_WIDTH_8 = 0, + AEMIF_WIDTH_16 = 1, + AEMIF_WIDTH_32 = 2, + } width; +}; + +void aemif_init(int num_cs, struct aemif_config *config); + +#endif -- cgit From 9f1220a9ca9f583fbb6e85cf43674c4258c85d24 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Tue, 10 Jun 2014 15:01:19 -0500 Subject: cpu: armv7: am33x: ddr: write emif ref_ctrl_shadow register Signed-off-by: Felipe Balbi --- arch/arm/cpu/armv7/am33xx/ddr.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index 9a625c4661..bbe9d1a8de 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -95,6 +95,7 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr) &emif_reg[nr]->emif_rd_wr_exec_thresh); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); writel(regs->sdram_config, &cstat->secure_emif_sdram_config); -- cgit From fd3f401bc14340db38f98a99824367e2287aa01a Mon Sep 17 00:00:00 2001 From: Jeroen Hofstee Date: Mon, 16 Jun 2014 23:22:23 +0200 Subject: omap3: board: trivial: add void for no args Signed-off-by: Jeroen Hofstee --- arch/arm/cpu/armv7/omap3/board.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 9bb1a1c8f9..2f9c93951e 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -147,7 +147,7 @@ void secure_unlock_mem(void) * configure secure registers and exit secure world * general use. *****************************************************************************/ -void secureworld_exit() +void secureworld_exit(void) { unsigned long i; @@ -178,7 +178,7 @@ void secureworld_exit() * Description: If chip is GP/EMU(special) type, unlock the SRAM for * general use. *****************************************************************************/ -void try_unlock_memory() +void try_unlock_memory(void) { int mode; int in_sdram = is_running_in_sdram(); -- cgit From 734af242c20b10b6fc690836123c5d0389b7e2a0 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Tue, 17 Jun 2014 16:47:40 +0200 Subject: OMAP: disable gpmc timeout safely for reenabling gpmc timeout is disabled and the reset counter is set to 0. However, if later a driver activates the timeout setting the reset to a valid value, the old reset value with zero is still valid for the first access. In fact, the timeout block loads the reset counter after a successful access. Found on a am335x board with a FPGA connected to the GPMC bus together with the NAND. When the FPGA driver in kernel activates the timeout, the system hangs at the first access by the NAND driver. Signed-off-by: Stefano Babic --- arch/arm/cpu/armv7/omap-common/mem-common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c index 11be480abd..5bc7e1f19b 100644 --- a/arch/arm/cpu/armv7/omap-common/mem-common.c +++ b/arch/arm/cpu/armv7/omap-common/mem-common.c @@ -121,7 +121,8 @@ void gpmc_init(void) writel(0x00000008, &gpmc_cfg->sysconfig); writel(0x00000000, &gpmc_cfg->irqstatus); writel(0x00000000, &gpmc_cfg->irqenable); - writel(0x00000000, &gpmc_cfg->timeout_control); + /* disable timeout, set a safe reset value */ + writel(0x00001ff0, &gpmc_cfg->timeout_control); #ifdef CONFIG_NOR writel(0x00000200, &gpmc_cfg->config); #else -- cgit From eacf46d340db182a4068772ec43e2586e9eaf80b Mon Sep 17 00:00:00 2001 From: Akshay Saraswat Date: Wed, 18 Jun 2014 17:53:57 +0530 Subject: Exynos5420: Let macros be used for exynos5420 Macros defined in exynos5_setup.h specific to SMDK5420 are required for Peach-Pit too. Hence, replacing CONFIG_SMDK5420 with CONFIG_EXYNOS5420 to enable these macros for all the boards based on Exynos5420. Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/cpu/armv7/exynos/exynos5_setup.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h index d91e585ea6..3242093855 100644 --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h @@ -435,10 +435,10 @@ /* * Definitions that differ with SoC's. - * Below is the part defining macros for smdk5250. - * Else part introduces macros for smdk5420. + * Below is the part defining macros for Exynos5250. + * Else part introduces macros for Exynos5420. */ -#ifndef CONFIG_SMDK5420 +#ifndef CONFIG_EXYNOS5420 /* APLL_CON1 */ #define APLL_CON1_VAL (0x00203800) -- cgit From 8e4ab1d58265884bbc9da6c6720d7a635f00fb2b Mon Sep 17 00:00:00 2001 From: Akshay Saraswat Date: Wed, 18 Jun 2014 17:53:58 +0530 Subject: Exynos5420: Introduce support for the Peach-Pit board While the Exynos5420 chip is used in both Smdk5420 and in the Peach-Pit line of devices, there could be other boards using the same chip, so a common configuration file is being added (exynos5420.h) as well as two common device tree files (exynos54xx.dtsi & exynos5420.dtsi). The peach board as declared in boards.cfg is a copy of smdk5420 declaration. The configuration files are similar, but define different default device trees, console serial ports and prompts. The device tree files for smdk5420 and peach-pit inherit from the same common file. Signed-off-by: Vadim Bendebury Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Tested-by: Simon Glass Signed-off-by: Minkyu Kang --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/exynos5420-peach-pit.dts | 127 ++++++++++++++++++++++++++++ arch/arm/dts/exynos5420-smdk5420.dts | 23 +----- arch/arm/dts/exynos5420.dtsi | 70 ---------------- arch/arm/dts/exynos54xx.dtsi | 151 ++++++++++++++++++++++++++++++++++ 5 files changed, 281 insertions(+), 93 deletions(-) create mode 100644 arch/arm/dts/exynos5420-peach-pit.dts delete mode 100644 arch/arm/dts/exynos5420.dtsi create mode 100644 arch/arm/dts/exynos54xx.dtsi (limited to 'arch/arm') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 55546152b9..933a4640e0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -6,7 +6,8 @@ dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5250-snow.dtb \ exynos5250-smdk5250.dtb \ - exynos5420-smdk5420.dtb + exynos5420-smdk5420.dtb \ + exynos5420-peach-pit.dtb dtb-$(CONFIG_MX6) += imx6q-sabreauto.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts new file mode 100644 index 0000000000..8d148afb44 --- /dev/null +++ b/arch/arm/dts/exynos5420-peach-pit.dts @@ -0,0 +1,127 @@ +/* + * SAMSUNG/GOOGLE Peach-Pit board device tree source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "exynos54xx.dtsi" + +/ { + model = "Samsung/Google Peach Pit board based on Exynos5420"; + + compatible = "google,pit-rev#", "google,pit", + "google,peach", "samsung,exynos5420", "samsung,exynos5"; + + config { + google,bad-wake-gpios = <&gpio 0x56 0>; /* gpx0-6 */ + hwid = "PIT TEST A-A 7848"; + lazy-init = <1>; + }; + + aliases { + serial0 = "/serial@12C30000"; + console = "/serial@12C30000"; + pmic = "/i2c@12ca0000"; + }; + + dmc { + mem-manuf = "samsung"; + mem-type = "ddr3"; + clock-frequency = <800000000>; + arm-frequency = <1700000000>; + }; + + tmu@10060000 { + samsung,min-temp = <25>; + samsung,max-temp = <125>; + samsung,start-warning = <95>; + samsung,start-tripping = <105>; + samsung,hw-tripping = <110>; + samsung,efuse-min-value = <40>; + samsung,efuse-value = <55>; + samsung,efuse-max-value = <100>; + samsung,slope = <274761730>; + samsung,dc-value = <25>; + }; + + /* MAX77802 is on i2c bus 4 */ + i2c@12ca0000 { + clock-frequency = <400000>; + power-regulator@9 { + compatible = "maxim,max77802-pmic"; + reg = <0x9>; + }; + }; + + i2c@12cd0000 { /* i2c7 */ + clock-frequency = <100000>; + soundcodec@20 { + reg = <0x20>; + compatible = "maxim,max98090-codec"; + }; + }; + + sound@3830000 { + samsung,codec-type = "max98090"; + }; + + i2c@12e10000 { /* i2c9 */ + clock-frequency = <400000>; + tpm@20 { + compatible = "infineon,slb9645-tpm"; + reg = <0x20>; + }; + }; + + spi@12d30000 { /* spi1 */ + spi-max-frequency = <50000000>; + firmware_storage_spi: flash@0 { + reg = <0>; + + /* + * A region for the kernel to store a panic event + * which the firmware will add to the log. + */ + elog-panic-event-offset = <0x01e00000 0x100000>; + + elog-shrink-size = <0x400>; + elog-full-threshold = <0xc00>; + }; + }; + + spi@12d40000 { /* spi2 */ + spi-max-frequency = <4000000>; + spi-deactivate-delay = <200>; + cros-ec@0 { + reg = <0>; + compatible = "google,cros-ec"; + spi-half-duplex; + spi-max-timeout-ms = <1100>; + spi-frame-header = <0xec>; + ec-interrupt = <&gpio 93 1>; /* GPX1_5 */ + + /* + * This describes the flash memory within the EC. Note + * that the STM32L flash erases to 0, not 0xff. + */ + #address-cells = <1>; + #size-cells = <1>; + flash@8000000 { + reg = <0x08000000 0x20000>; + erase-value = <0>; + }; + }; + }; + + xhci@12000000 { + samsung,vbus-gpio = <&gpio 0x40 0>; /* H00 */ + }; + + xhci@12400000 { + samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */ + }; +}; diff --git a/arch/arm/dts/exynos5420-smdk5420.dts b/arch/arm/dts/exynos5420-smdk5420.dts index d73976356d..1bc6256283 100644 --- a/arch/arm/dts/exynos5420-smdk5420.dts +++ b/arch/arm/dts/exynos5420-smdk5420.dts @@ -8,7 +8,7 @@ */ /dts-v1/; -/include/ "exynos5420.dtsi" +/include/ "exynos54xx.dtsi" / { model = "SAMSUNG SMDK5420 board based on EXYNOS5420"; @@ -19,27 +19,6 @@ }; aliases { - i2c0 = "/i2c@12c60000"; - i2c1 = "/i2c@12c70000"; - i2c2 = "/i2c@12c80000"; - i2c3 = "/i2c@12c90000"; - i2c4 = "/i2c@12ca0000"; - i2c5 = "/i2c@12cb0000"; - i2c6 = "/i2c@12cc0000"; - i2c7 = "/i2c@12cd0000"; - i2c8 = "/i2c@12e00000"; - i2c9 = "/i2c@12e10000"; - i2c10 = "/i2c@12e20000"; - spi0 = "/spi@12d20000"; - spi1 = "/spi@12d30000"; - spi2 = "/spi@12d40000"; - spi3 = "/spi@131a0000"; - spi4 = "/spi@131b0000"; - mmc0 = "/mmc@12200000"; - mmc1 = "/mmc@12210000"; - mmc2 = "/mmc@12220000"; - xhci0 = "/xhci@12000000"; - xhci1 = "/xhci@12400000"; serial0 = "/serial@12C30000"; console = "/serial@12C30000"; }; diff --git a/arch/arm/dts/exynos5420.dtsi b/arch/arm/dts/exynos5420.dtsi deleted file mode 100644 index 02ead61a49..0000000000 --- a/arch/arm/dts/exynos5420.dtsi +++ /dev/null @@ -1,70 +0,0 @@ -/* - * (C) Copyright 2013 SAMSUNG Electronics - * SAMSUNG EXYNOS5420 SoC device tree source - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/include/ "exynos5.dtsi" - -/ { - config { - machine-arch-id = <4151>; - }; - - i2c@12ca0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos5-hsi2c"; - reg = <0x12CA0000 0x100>; - interrupts = <0 60 0>; - }; - - i2c@12cb0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos5-hsi2c"; - reg = <0x12CB0000 0x100>; - interrupts = <0 61 0>; - }; - - i2c@12cc0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos5-hsi2c"; - reg = <0x12CC0000 0x100>; - interrupts = <0 62 0>; - }; - - i2c@12cd0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos5-hsi2c"; - reg = <0x12CD0000 0x100>; - interrupts = <0 63 0>; - }; - - i2c@12e00000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos5-hsi2c"; - reg = <0x12E00000 0x100>; - interrupts = <0 87 0>; - }; - - i2c@12e10000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos5-hsi2c"; - reg = <0x12E10000 0x100>; - interrupts = <0 88 0>; - }; - - i2c@12e20000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "samsung,exynos5-hsi2c"; - reg = <0x12E20000 0x100>; - interrupts = <0 203 0>; - }; -}; diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi new file mode 100644 index 0000000000..b9f8e0bd3d --- /dev/null +++ b/arch/arm/dts/exynos54xx.dtsi @@ -0,0 +1,151 @@ +/* + * (C) Copyright 2013 SAMSUNG Electronics + * SAMSUNG EXYNOS5420 SoC device tree source + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/include/ "exynos5.dtsi" + +/ { + config { + machine-arch-id = <4151>; + }; + + aliases { + i2c0 = "/i2c@12c60000"; + i2c1 = "/i2c@12c70000"; + i2c2 = "/i2c@12c80000"; + i2c3 = "/i2c@12c90000"; + i2c4 = "/i2c@12ca0000"; + i2c5 = "/i2c@12cb0000"; + i2c6 = "/i2c@12cc0000"; + i2c7 = "/i2c@12cd0000"; + i2c8 = "/i2c@12e00000"; + i2c9 = "/i2c@12e10000"; + i2c10 = "/i2c@12e20000"; + spi0 = "/spi@12d20000"; + spi1 = "/spi@12d30000"; + spi2 = "/spi@12d40000"; + spi3 = "/spi@131a0000"; + spi4 = "/spi@131b0000"; + mmc0 = "/mmc@12200000"; + mmc1 = "/mmc@12210000"; + mmc2 = "/mmc@12220000"; + xhci0 = "/xhci@12000000"; + xhci1 = "/xhci@12400000"; + }; + + i2c@12ca0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CA0000 0x100>; + interrupts = <0 60 0>; + }; + + i2c@12cb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CB0000 0x100>; + interrupts = <0 61 0>; + }; + + i2c@12cc0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CC0000 0x100>; + interrupts = <0 62 0>; + }; + + i2c@12cd0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12CD0000 0x100>; + interrupts = <0 63 0>; + }; + + i2c@12e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12E00000 0x100>; + interrupts = <0 87 0>; + }; + + i2c@12e10000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12E10000 0x100>; + interrupts = <0 88 0>; + }; + + i2c@12e20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,exynos5-hsi2c"; + reg = <0x12E20000 0x100>; + interrupts = <0 203 0>; + }; + + mmc@12200000 { + samsung,bus-width = <8>; + samsung,timing = <1 3 3>; + samsung,removable = <0>; + samsung,pre-init; + }; + + mmc@12210000 { + status = "disabled"; + }; + + mmc@12220000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + samsung,removable = <1>; + }; + + mmc@12230000 { + status = "disabled"; + }; + + fimd@14400000 { + /* sysmmu is not used in U-Boot */ + samsung,disable-sysmmu; + }; + + dp@145b0000 { + samsung,lt-status = <0>; + + samsung,master-mode = <0>; + samsung,bist-mode = <0>; + samsung,bist-pattern = <0>; + samsung,h-sync-polarity = <0>; + samsung,v-sync-polarity = <0>; + samsung,interlaced = <0>; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + }; + + dmc { + mem-type = "ddr3"; + }; + + xhci1: xhci@12400000 { + compatible = "samsung,exynos5250-xhci"; + reg = <0x12400000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + phy { + compatible = "samsung,exynos5250-usb3-phy"; + reg = <0x12500000 0x100>; + }; + }; +}; -- cgit From 5d2ad2bc33e3a568409ebae8afba50a2b782d1be Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 25 Jun 2014 12:48:06 +0200 Subject: vf610: fix build due to missing sys_proto.h commit 67a04ab3ab8522a3a34491853e46105317580df5 fix the build for MX25. The same error happens for VF610 SOC. Signed-off-by: Stefano Babic --- arch/arm/imx-common/iomux-v3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index c090b308b2..22cd11aa04 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -11,7 +11,7 @@ #include #include #include -#ifndef CONFIG_MX25 +#if !defined(CONFIG_MX25) && !defined(CONFIG_VF610) #include #endif #include -- cgit