From 00057eea66e6110898162cc72554c5fd8201cdef Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Fri, 13 Jul 2018 13:40:23 +0800 Subject: arm: socfpga: Fixes: Rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESET Commit bfc6bae8fa1f2d8a9c51548767b02f1a1e0ffe52 This commit rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESET. Update with new CONFIG name and enable CONFIG_SPL_DM_RESET when CONFIG_DM_RESET is enabled. Signed-off-by: Ley Foon Tan Acked-by: Marek Vasut --- arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 376851ef7a..692f4db600 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -766,6 +766,7 @@ config ARCH_SOCFPGA select DM_SERIAL select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select OF_CONTROL + select SPL_DM_RESET if DM_RESET select SPL_LIBCOMMON_SUPPORT select SPL_LIBDISK_SUPPORT select SPL_LIBGENERIC_SUPPORT @@ -774,7 +775,6 @@ config ARCH_SOCFPGA select SPL_OF_CONTROL select SPL_SERIAL_SUPPORT select SPL_DM_SERIAL - select SPL_RESET_SUPPORT select SPL_SPI_FLASH_SUPPORT if SPL_SPI_SUPPORT select SPL_SPI_SUPPORT if DM_SPI select SPL_WATCHDOG_SUPPORT -- cgit From 937db7188e3a5ab8f802eff9b57854189379667a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 12 Jul 2018 15:07:46 +0200 Subject: ARM: socfpga: Assure correct CPACR configuration Make sure the ARM CPACR register is zeroed out, this is mandatory on Arria10. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen --- arch/arm/mach-socfpga/board.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 26d84be6e9..e8c7503fba 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -21,12 +21,14 @@ DECLARE_GLOBAL_DATA_PTR; void s_init(void) { #ifndef CONFIG_ARM64 /* - * Preconfigure ACTLR, make sure Write Full Line of Zeroes is disabled. + * Preconfigure ACTLR and CPACR, make sure Write Full Line of Zeroes + * is disabled in ACTLR. * This is optional on CycloneV / ArriaV. * This is mandatory on Arria10, otherwise Linux refuses to boot. */ asm volatile( "mcr p15, 0, %0, c1, c0, 1\n" + "mcr p15, 0, %0, c1, c0, 2\n" "isb\n" "dsb\n" ::"r"(0x0)); -- cgit From 42f4b83b52735d698bf3f3de2665bf6d42db9f1c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 12 Jul 2018 15:34:23 +0200 Subject: ARM: socfpga: Init missing security policies on A10 The Arria10 requires proper configuration of the NOC firewall, otherwise the access to certain areas of the LWHPS bridge fails in Linux. Add the missing setup. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen --- arch/arm/mach-socfpga/misc_arria10.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index a75cbc4ce6..80bf2f036f 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -93,6 +93,19 @@ static void initialize_security_policies(void) /* Put OCRAM in non-secure */ writel(0x003f0000, &noc_fw_ocram_base->region0); writel(0x1, &noc_fw_ocram_base->enable); + + /* Put DDR in non-secure */ + writel(0xffff0000, SOCFPGA_SDR_FIREWALL_L3_ADDRESS + 0xc); + writel(0x1, SOCFPGA_SDR_FIREWALL_L3_ADDRESS); + + /* Enable priviledged and non-priviledged access to L4 peripherals */ + writel(~0, SOCFPGA_NOC_L4_PRIV_FLT_OFST); + + /* Enable secure and non-secure transactions to bridges */ + writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST); + writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST + 4); + + writel(0x0007FFFF, &sysmgr_regs->ecc_intmask_set); } int arch_early_init_r(void) -- cgit From 64eeb1585428b71e29022e22d1aae86b65b9e052 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 7 May 2018 22:22:26 +0200 Subject: ARM: dts: socfpga: Adjust NAND register layout on Arria10 Adjust the NAND register size on Arria10 to reflect reality. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen --- arch/arm/dts/socfpga_arria10.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi index b51febda9c..2f935a21e9 100644 --- a/arch/arm/dts/socfpga_arria10.dtsi +++ b/arch/arm/dts/socfpga_arria10.dtsi @@ -637,8 +637,8 @@ #address-cells = <1>; #size-cells = <1>; compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand"; - reg = <0xffb90000 0x72000>, - <0xffb80000 0x10000>; + reg = <0xffb90000 0x20>, + <0xffb80000 0x1000>; reg-names = "nand_data", "denali_reg"; interrupts = <0 99 4>; dma-mask = <0xffffffff>; -- cgit