From 1a4596601fd395f3afb8f82f3f840c5e00bdd57a Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 8 Jul 2013 09:37:19 +0200 Subject: Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini --- arch/mips/cpu/mips32/cache.S | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) (limited to 'arch/mips/cpu/mips32/cache.S') diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index 64dfad0263..117fc56df7 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -3,23 +3,7 @@ * * Copyright (c) 2003 Wolfgang Denk * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #include -- cgit From da84f33b046fe99c5fbb6f7d8f8b03c7333b260d Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Wed, 12 Jun 2013 18:02:46 +0200 Subject: MIPS: mips32/cache.S: remove superfluous register assignment The t4 register already holds the cache line size, and the value of the register is not changed in mips_init_icache. Get the cache line size value from t4 for mips_init_dcache as well and remove the superfluous assignment of t5 register. Signed-off-by: Gabor Juhos --- arch/mips/cpu/mips32/cache.S | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/mips/cpu/mips32/cache.S') diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index 117fc56df7..40bb46e5b6 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -129,7 +129,6 @@ NESTED(mips_cache_reset, 0, ra) li t2, CONFIG_SYS_ICACHE_SIZE li t3, CONFIG_SYS_DCACHE_SIZE li t4, CONFIG_SYS_CACHELINE_SIZE - move t5, t4 li v0, MIPS_MAX_CACHE_SIZE @@ -164,7 +163,7 @@ NESTED(mips_cache_reset, 0, ra) * then initialize D-cache. */ move a1, t3 - move a2, t5 + move a2, t4 PTR_LA t7, mips_init_dcache jalr t7 -- cgit From c325916563ac67ec5f86748060c2909a9b960bee Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Thu, 13 Jun 2013 12:59:34 +0200 Subject: MIPS: mips32/cache.S: save return address in t9 register Synchronize the code with mips64/cache.S, in order to allow further unifications. Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck --- arch/mips/cpu/mips32/cache.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips/cpu/mips32/cache.S') diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index 40bb46e5b6..fc13d3faab 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -18,7 +18,7 @@ #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT #endif -#define RA t8 +#define RA t9 /* * 16kB is the maximum size of instruction and data caches on MIPS 4K, -- cgit From ee8b1e29597bcf18bfebd6fd8eccc8e245046352 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Thu, 13 Jun 2013 12:59:35 +0200 Subject: MIPS: mips32/cache.S: store cache line size in t8 register Synchronize the code with mips64/cache.S, in order to allow further unifications. Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck --- arch/mips/cpu/mips32/cache.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/mips/cpu/mips32/cache.S') diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index fc13d3faab..d3f156e482 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -128,7 +128,7 @@ NESTED(mips_cache_reset, 0, ra) move RA, ra li t2, CONFIG_SYS_ICACHE_SIZE li t3, CONFIG_SYS_DCACHE_SIZE - li t4, CONFIG_SYS_CACHELINE_SIZE + li t8, CONFIG_SYS_CACHELINE_SIZE li v0, MIPS_MAX_CACHE_SIZE @@ -155,7 +155,7 @@ NESTED(mips_cache_reset, 0, ra) * Initialize the I-cache first, */ move a1, t2 - move a2, t4 + move a2, t8 PTR_LA t7, mips_init_icache jalr t7 @@ -163,7 +163,7 @@ NESTED(mips_cache_reset, 0, ra) * then initialize D-cache. */ move a1, t3 - move a2, t4 + move a2, t8 PTR_LA t7, mips_init_dcache jalr t7 -- cgit From db2c86d7d71d1be0ac0fe702493faf9302639235 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Thu, 13 Jun 2013 12:59:36 +0200 Subject: MIPS: mips32/cache.S: use v1 register for indirect function calls Synchronize the code with mips64/cache.S, in order to allow further unifications. Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck --- arch/mips/cpu/mips32/cache.S | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/mips/cpu/mips32/cache.S') diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index d3f156e482..12f656cad0 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -156,16 +156,16 @@ NESTED(mips_cache_reset, 0, ra) */ move a1, t2 move a2, t8 - PTR_LA t7, mips_init_icache - jalr t7 + PTR_LA v1, mips_init_icache + jalr v1 /* * then initialize D-cache. */ move a1, t3 move a2, t8 - PTR_LA t7, mips_init_dcache - jalr t7 + PTR_LA v1, mips_init_dcache + jalr v1 jr RA END(mips_cache_reset) -- cgit