From a02bc1f99275a17e1d29886c8c69398e9313842d Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 14 May 2020 11:59:06 +0200 Subject: mips: traps: Set WG bit in EBase register on Octeon WG (bit 11) needs to be set on Octeon to enable writing bits 63:30 of the exception base register. Signed-off-by: Stefan Roese --- arch/mips/include/asm/mipsregs.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/mips/include/asm/mipsregs.h') diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 7538e6b2e0..17381301ec 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -366,6 +366,7 @@ * Bits in the coprocessor 0 EBase register. */ #define EBASE_CPUNUM 0x3ff +#define EBASE_WG (_ULCAST_(1) << 11) /* * Bits in the coprocessor 0 config register. -- cgit