From 320d53da605d67b9d95622c5c6bfd5ac2c17ed58 Mon Sep 17 00:00:00 2001 From: Mark Marshall Date: Sun, 9 Sep 2012 23:06:03 +0000 Subject: powerpc mpc85xx: Only clear TSR:WIS in watchdog_reset. We should only write TSR_WIS to the SPRN_TSR register in reset_85xx_watchdog. The old code would cause the timer interrupt to be acknowledged when the watchdog was reset, and we would then get no more timer interrupts. This bug would affect all mpc85xx boards that have the watchdog enabled. Signed-off-by: Mark Marshall Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cpu.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'arch/powerpc/cpu/mpc85xx/cpu.c') diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 5ddb29435c..a5048a1306 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -270,10 +270,7 @@ reset_85xx_watchdog(void) /* * Clear TSR(WIS) bit by writing 1 */ - unsigned long val; - val = mfspr(SPRN_TSR); - val |= TSR_WIS; - mtspr(SPRN_TSR, val); + mtspr(SPRN_TSR, TSR_WIS); } #endif /* CONFIG_WATCHDOG */ -- cgit From 800c73c410732e1c9f852a935151c834f3b31c4d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 8 Oct 2012 07:44:06 +0000 Subject: powerpc/85xx: Add determining and report IFC frequency Signed-off-by: Kumar Gala Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/powerpc/cpu/mpc85xx/cpu.c') diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index a5048a1306..26fc84c9aa 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -181,6 +181,10 @@ int checkcpu (void) } #endif +#if defined(CONFIG_FSL_IFC) + printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); +#endif + #ifdef CONFIG_CPM2 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); #endif -- cgit From 2f1712b275af3ed960b92cd1ed9b99d23c4919a5 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:10 +0000 Subject: powerpc/mpc85xx: check number of cores Panic if the number of cores is more than CONFIG_MAX_CPUS because it will surely overflow gd structure. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/powerpc/cpu/mpc85xx/cpu.c') diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 26fc84c9aa..40cce1dbda 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -127,6 +127,11 @@ int checkcpu (void) printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); + if (nr_cores > CONFIG_MAX_CPUS) { + panic("\nUnexpected number of cores: %d, max is %d\n", + nr_cores, CONFIG_MAX_CPUS); + } + get_sys_info(&sysinfo); puts("Clock Configuration:"); -- cgit From 379c5145ef8f3adbcfeb0a47503838627959cb67 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:16 +0000 Subject: powerpc/corenet2: fix mismatch DDR sync bit from RCW Corenet 2nd generation Chassis doesn't have ddr_sync bit in RCW. Only async mode is supported. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cpu.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'arch/powerpc/cpu/mpc85xx/cpu.c') diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 40cce1dbda..f493483c1e 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -60,7 +60,8 @@ int checkcpu (void) uint major, minor; struct cpu_type *cpu; char buf1[32], buf2[32]; -#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) +#if defined(CONFIG_DDR_CLK_FREQ) || \ + (defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif /* CONFIG_FSL_CORENET */ #ifdef CONFIG_DDR_CLK_FREQ @@ -68,8 +69,13 @@ int checkcpu (void) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else #ifdef CONFIG_FSL_CORENET - u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) + u32 ddr_sync ; +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 + ddr_sync = 0; /* only async mode is supported */ +#else + ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; +#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ #else u32 ddr_ratio = 0; #endif /* CONFIG_FSL_CORENET */ -- cgit From 98ffa19053f2d10578a227de4e441698226fde0a Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:31 +0000 Subject: powerpc/mpc85xx: Add CONFIG_DDR_CLK_FREQ for corenet platform New corenet platforms with chassis2 have separated DDR clock inputs. Use CONFIG_DDR_CLK_FREQ for DDR clock. This patch also cleans up the logic of detecting and displaying synchronous vs asynchronous mode. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cpu.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) (limited to 'arch/powerpc/cpu/mpc85xx/cpu.c') diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index f493483c1e..892bfa4c60 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -60,26 +60,32 @@ int checkcpu (void) uint major, minor; struct cpu_type *cpu; char buf1[32], buf2[32]; -#if defined(CONFIG_DDR_CLK_FREQ) || \ - (defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)) +#if (defined(CONFIG_DDR_CLK_FREQ) || \ + defined(CONFIG_FSL_CORENET)) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif /* CONFIG_FSL_CORENET */ -#ifdef CONFIG_DDR_CLK_FREQ - u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) - >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; -#else + + /* + * Cornet platforms use ddr sync bit in RCW to indicate sync vs async + * mode. Previous platform use ddr ratio to do the same. This + * information is only for display here. + */ #ifdef CONFIG_FSL_CORENET - u32 ddr_sync ; #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 - ddr_sync = 0; /* only async mode is supported */ + u32 ddr_sync = 0; /* only async mode is supported */ #else - ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) + u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ +#else /* CONFIG_FSL_CORENET */ +#ifdef CONFIG_DDR_CLK_FREQ + u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) + >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else u32 ddr_ratio = 0; -#endif /* CONFIG_FSL_CORENET */ #endif /* CONFIG_DDR_CLK_FREQ */ +#endif /* CONFIG_FSL_CORENET */ + unsigned int i, core, nr_cores = cpu_numcores(); u32 mask = cpu_mask(); -- cgit From 990e1a8ce1415b9010faccd1402d499e203ea2fb Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Thu, 11 Oct 2012 07:13:39 +0000 Subject: poweprc/85xx: add QMan frequency info and fdt fixup. Starting from QMan3.0, the QMan clock cycle needs be exposed so that the kernel driver can use it to calculate the shaper prescaler and rate. Signed-off-by: Haiying Wang Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/powerpc/cpu/mpc85xx/cpu.c') diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 892bfa4c60..db232e64f8 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -217,6 +217,10 @@ int checkcpu (void) } #endif +#ifdef CONFIG_SYS_DPAA_QBMAN + printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freqQMAN)); +#endif + #ifdef CONFIG_SYS_DPAA_PME printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); #endif -- cgit