From 06ad970b53a3d6aa122685e6142a04908434a8ef Mon Sep 17 00:00:00 2001 From: Darwin Dingel Date: Tue, 25 Oct 2016 09:48:01 +1300 Subject: powerpc: mpc85xx: Implemente workaround for CPU erratum A-007907 Core hang occurs when using L1 stashes. Workaround is to disable L1 stashes so software uses L2 cache for stashes instead. Reviewed-by: Chris Packham Signed-off-by: Darwin Dingel Cc: York Sun [York S: Move SYS_FSL_ERRATUM_A007907 to Kconfig] Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/powerpc/cpu/mpc85xx/cpu_init.c') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 822844dfa9..f5bf67c990 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -777,6 +777,13 @@ int cpu_init_r(void) sync(); } #endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A007907 + flush_dcache(); + mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID)); + sync(); +#endif + #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 /* * A-005812 workaround sets bit 32 of SPR 976 for SoCs running -- cgit