From c63e137014cf148bc1d234128941dccee3d519ae Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 25 Jun 2013 11:37:48 -0700 Subject: powerpc/mpc8xxx: Add memory reset control JEDEC spec requires the clocks to be stable before deasserting reset signal for RDIMMs. Clocks start when any chip select is enabled and clock control register is set. This patch also adds the interface to toggle memory reset signal if needed by the boards. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc85xx/ddr-gen1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/powerpc/cpu/mpc85xx/ddr-gen1.c') diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen1.c b/arch/powerpc/cpu/mpc85xx/ddr-gen1.c index 8a86819fb5..4dd8c0b5bf 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen1.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen1.c @@ -15,7 +15,7 @@ #endif void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num) + unsigned int ctrl_num, int step) { unsigned int i; volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR; -- cgit