From f1a96ec1a9920854c3308a062caca0b339bd1e3b Mon Sep 17 00:00:00 2001 From: Chunhe Lan Date: Wed, 7 May 2014 10:50:20 +0800 Subject: fsl/pci: Add workaround for erratum A-005434 By default, all PEX inbound windows PEX_PEXIWARn[TRGT] are mapped to 0xF, which is local memory. But for BSC9132, 0xF is CCSR, 0x0 is local memory. Signed-off-by: Minghuan Lian Signed-off-by: Chunhe Lan Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/powerpc/cpu') diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 9d8acd0aa1..3d37a7614f 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -299,6 +299,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 check_erratum_a007212(); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005434 + puts("Work-around for Erratum A-005434 enabled\n"); +#endif return 0; } -- cgit From 9c3fdd883a8c9aa32b52abf8ccc180bd4929826f Mon Sep 17 00:00:00 2001 From: Shaveta Leekha Date: Wed, 7 May 2014 14:43:23 +0530 Subject: powerpc/mpc85xx: Added B4460 support B4460 differs from B4860 only in number of CPU cores, hence used existing support for B4860. B4460 has 2 PPC cores whereas B4860 has 4 PPC cores. Signed-off-by: Shaveta Leekha Signed-off-by: Sandeep Singh Signed-off-by: Poonam Aggrwal Reviewed-by: York Sun --- arch/powerpc/cpu/mpc8xxx/cpu.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/powerpc/cpu') diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 13bd0acdfb..15561a1533 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -67,6 +67,7 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(G4860, G4860, 0), CPU_TYPE_ENTRY(G4060, G4060, 0), CPU_TYPE_ENTRY(B4440, B4440, 0), + CPU_TYPE_ENTRY(B4460, B4460, 0), CPU_TYPE_ENTRY(G4440, G4440, 0), CPU_TYPE_ENTRY(B4420, B4420, 0), CPU_TYPE_ENTRY(B4220, B4220, 0), -- cgit