From 594708dd9dc9f1204ae0ea236d00e57fd25ddf0d Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:04:04 +0000 Subject: P1020: dts: Added PCIe DT nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit P1020 integrated 2 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 1.0a, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- arch/powerpc/dts/p1020rdb-pc.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/powerpc/dts/p1020rdb-pc.dts') diff --git a/arch/powerpc/dts/p1020rdb-pc.dts b/arch/powerpc/dts/p1020rdb-pc.dts index fd68b8b440..7ebaa619df 100644 --- a/arch/powerpc/dts/p1020rdb-pc.dts +++ b/arch/powerpc/dts/p1020rdb-pc.dts @@ -18,6 +18,18 @@ soc: soc@ffe00000 { ranges = <0x0 0x0 0xffe00000 0x100000>; }; + + pci1: pcie@ffe09000 { + reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pci0: pcie@ffe0a000 { + reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; }; /include/ "p1020-post.dtsi" -- cgit