From fb4a2409b46c98672557bb07dec8e873bef1e23c Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Tue, 18 Mar 2014 23:40:26 +0530 Subject: powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS Changes: 1. L2 cache is being invalidated by Boot ROM code for e6500 core. So removing the invalidation from start.S 2. Clear the LAW and corresponding configuration for CPC. Boot ROM code uses it as hosekeeping area. 3. For Secure boot, CPC is configured as SRAM and used as house keeping area. This configuration is to be disabled once in uboot. Earlier this disabling of CPC as SRAM was happening in cpu_init_r. As a result cache invalidation function was getting skipped in case CPC is configured as SRAM.This was causing random crashes. Signed-off-by: Ruchika Gupta Signed-off-by: Aneesh Bansal Reviewed-by: York Sun --- arch/powerpc/include/asm/fsl_secure_boot.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/powerpc/include/asm/fsl_secure_boot.h') diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 3dce1d2bac..c705d5a05b 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -17,5 +17,11 @@ #endif #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 +#if defined(CONFIG_B4860QDS) +#define CONFIG_SYS_CPC_REINIT_F +#undef CONFIG_SYS_INIT_L3_ADDR +#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 +#endif + #endif #endif -- cgit