From 5e7abce99163a00b8d267cc8045f06b498728288 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 11 Sep 2010 09:31:43 +0200 Subject: ppc4xx: Big header cleanup, mostly PPC440 related This patch starts a bit PPC4xx header cleanup. First patch mostly touches PPC440 files. A later patch will touch the PPC405 files as well. This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. Signed-off-by: Stefan Roese --- arch/powerpc/include/asm/ppc405ex.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 arch/powerpc/include/asm/ppc405ex.h (limited to 'arch/powerpc/include/asm/ppc405ex.h') diff --git a/arch/powerpc/include/asm/ppc405ex.h b/arch/powerpc/include/asm/ppc405ex.h new file mode 100644 index 0000000000..f2c860a1ac --- /dev/null +++ b/arch/powerpc/include/asm/ppc405ex.h @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PPC405EX_H_ +#define _PPC405EX_H_ + +#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ + +#define CONFIG_NAND_NDFC + +#define CONFIG_SYS_PPC4xx_PLB4_ARBITER + +#endif /* _PPC405EX_H_ */ -- cgit From afabb498b749b48ca3ee7e833fe1501e2d6993cb Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sun, 12 Sep 2010 06:21:37 +0200 Subject: ppc4xx: Big header cleanup part 2, mostly PPC405 related This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. As a part from this cleanup, the GPIO definitions for PPC405EP are corrected. The high and low parts of the registers (for example CONFIG_SYS_GPIO0_OSRL vs. CONFIG_SYS_GPIO0_OSRH) have been defined in the wrong order. This patch now fixes this issue by switching these xxxH and xxxL values. This brings the GPIO 405EP port in sync with all other PPC4xx ports. Signed-off-by: Stefan Roese --- arch/powerpc/include/asm/ppc405ex.h | 57 ++++++++++++++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) (limited to 'arch/powerpc/include/asm/ppc405ex.h') diff --git a/arch/powerpc/include/asm/ppc405ex.h b/arch/powerpc/include/asm/ppc405ex.h index f2c860a1ac..880d53a161 100644 --- a/arch/powerpc/include/asm/ppc405ex.h +++ b/arch/powerpc/include/asm/ppc405ex.h @@ -25,6 +25,61 @@ #define CONFIG_NAND_NDFC -#define CONFIG_SYS_PPC4xx_PLB4_ARBITER +/* Memory mapped register */ +#define GPIO0_BASE 0xef600800 + +/* SDR */ +#define SDR0_SDCS0 0x0060 +#define SDR0_UART0 0x0120 /* UART0 Config */ +#define SDR0_UART1 0x0121 /* UART1 Config */ +#define SDR0_SRST 0x0200 +#define SDR0_CUST0 0x4000 +#define SDR0_PFC0 0x4100 +#define SDR0_PFC1 0x4101 +#define SDR0_MFR 0x4300 /* SDR0_MFR reg */ + +#define SDR0_SDCS_SDD (0x80000000 >> 31) + +#define SDR0_SRST_DMC (0x80000000 >> 10) + +#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ +#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ +#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ +#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ + +#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ +#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ +#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ + +#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ +#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width= 16 Bit */ +#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width= 8 Bit */ + +#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ +#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((u32)(n)) & 0xF) << 24) +#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((u32)(n)) >> 24) & 0xF) + +#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ +#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((u32)(n)) & 0x3) << 22) +#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((u32)(n)) >> 22) & 0x3) + +#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ + +#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ +#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ +#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ + +#define SDR0_PFC1_U1ME 0x02000000 +#define SDR0_PFC1_U0ME 0x00080000 +#define SDR0_PFC1_U0IM 0x00040000 +#define SDR0_PFC1_SIS 0x00020000 +#define SDR0_PFC1_DMAAEN 0x00010000 +#define SDR0_PFC1_DMADEN 0x00008000 +#define SDR0_PFC1_USBEN 0x00004000 +#define SDR0_PFC1_AHBSWAP 0x00000020 +#define SDR0_PFC1_USBBIGEN 0x00000010 +#define SDR0_PFC1_GPT_FREQ 0x0000000f #endif /* _PPC405EX_H_ */ -- cgit From 550650ddd0fde00f245bc3da72d7272844198394 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 20 Sep 2010 16:05:31 +0200 Subject: ppc4xx: Use common NS16550 driver for PPC4xx UART This patch removes the PPC4xx UART driver. Instead the common NS16550 driver is used, since all PPC4xx SoC's use this peripheral device. The file 4xx_uart.c now only implements the UART clock calculation function which also sets the SoC internal UART divisors. All PPC4xx board config headers are changed to use this common NS16550 driver now. Tested on these boards: acadia, canyonlands, katmai, kilauea, sequoia, zeus Signed-off-by: Stefan Roese --- arch/powerpc/include/asm/ppc405ex.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/powerpc/include/asm/ppc405ex.h') diff --git a/arch/powerpc/include/asm/ppc405ex.h b/arch/powerpc/include/asm/ppc405ex.h index 880d53a161..36d3149b8c 100644 --- a/arch/powerpc/include/asm/ppc405ex.h +++ b/arch/powerpc/include/asm/ppc405ex.h @@ -26,7 +26,12 @@ #define CONFIG_NAND_NDFC /* Memory mapped register */ -#define GPIO0_BASE 0xef600800 +#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */ + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) + +#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0800) /* SDR */ #define SDR0_SDCS0 0x0060 -- cgit