From 63063cc7ae690b418b1dae1cb21004587361369e Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Sun, 14 Aug 2011 23:09:39 -0500 Subject: mpc83xx: fix global timer structure definition The byte address distance between GTCFR2 and GTMDR1 is 11, not 10. Reported-by: Shawn Bai Acked-by: Joe Hershberger Signed-off-by: Kim Phillips --- arch/powerpc/include/asm/immap_83xx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/powerpc') diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 8d4c9cb4f7..2daddebe55 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -113,7 +113,7 @@ typedef struct gtm83xx { u8 cfr1; /* Timer1/2 Configuration */ u8 res0[3]; u8 cfr2; /* Timer3/4 Configuration */ - u8 res1[10]; + u8 res1[11]; u16 mdr1; /* Timer1 Mode Register */ u16 mdr2; /* Timer2 Mode Register */ u16 rfr1; /* Timer1 Reference Register */ -- cgit From 4713db666c1cc2861df8caf7fd8486b6793028ef Mon Sep 17 00:00:00 2001 From: Joe Hershberger Date: Tue, 11 Oct 2011 21:46:04 -0500 Subject: mpc83xx: Fix ipic structure definition Signed-off-by: Joe Hershberger Cc: Joe Hershberger Added siprr_{b,c} and sepcr for completeness. Signed-off-by: Kim Phillips --- arch/powerpc/include/asm/immap_83xx.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'arch/powerpc') diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 2daddebe55..2ba502ad11 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -150,11 +150,12 @@ typedef struct ipic83xx { u32 sipnr_h; /* System Internal Interrupt Pending Register - High */ u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */ u32 siprr_a; /* System Internal Interrupt Group A Priority Register */ - u8 res0[8]; + u32 siprr_b; /* System Internal Interrupt Group B Priority Register */ + u32 siprr_c; /* System Internal Interrupt Group C Priority Register */ u32 siprr_d; /* System Internal Interrupt Group D Priority Register */ u32 simsr_h; /* System Internal Interrupt Mask Register - High */ u32 simsr_l; /* System Internal Interrupt Mask Register - Low */ - u8 res1[4]; + u32 sicnr; /* System Internal Interrupt Control Register */ u32 sepnr; /* System External Interrupt Pending Register */ u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */ u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */ @@ -163,14 +164,14 @@ typedef struct ipic83xx { u32 sersr; /* System Error Status Register */ u32 sermr; /* System Error Mask Register */ u32 sercr; /* System Error Control Register */ - u8 res2[4]; + u32 sepcr; /* System External Interrupt Polarity Control Register */ u32 sifcr_h; /* System Internal Interrupt Force Register - High */ u32 sifcr_l; /* System Internal Interrupt Force Register - Low */ u32 sefcr; /* System External Interrupt Force Register */ u32 serfr; /* System Error Force Register */ u32 scvcr; /* System Critical Interrupt Vector Register */ u32 smvcr; /* System Management Interrupt Vector Register */ - u8 res3[0x98]; + u8 res[0x98]; } ipic83xx_t; /* -- cgit From 2fef402097866b4172d7a966a72397a5ccba5b10 Mon Sep 17 00:00:00 2001 From: Joe Hershberger Date: Tue, 11 Oct 2011 23:57:29 -0500 Subject: mpc83xx: Cleanup usage of DDR constants Signed-off-by: Joe Hershberger Cc: Joe Hershberger Signed-off-by: Kim Phillips --- arch/powerpc/cpu/mpc83xx/spd_sdram.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/powerpc') diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index 9b01f0d8fb..3855bfd457 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -46,10 +46,19 @@ void board_add_ram_info(int use_default) printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1); +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) + if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16) + puts(", 16-bit"); + else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32) + puts(", 32-bit"); + else + puts(", unknown width"); +#else if (ddr->sdram_cfg & SDRAM_CFG_32_BE) puts(", 32-bit"); else puts(", 64-bit"); +#endif if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) puts(", ECC on"); -- cgit From 7d6a098219f8473ca4653cce5f7a49672b967f36 Mon Sep 17 00:00:00 2001 From: Joe Hershberger Date: Tue, 11 Oct 2011 23:57:30 -0500 Subject: mpc83xx: Cleanup usage of LBC constants Signed-off-by: Joe Hershberger Cc: Joe Hershberger Signed-off-by: Kim Phillips --- arch/powerpc/include/asm/fsl_lbc.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'arch/powerpc') diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 8695a6269a..bf572b78e1 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -50,8 +50,10 @@ void lbc_sdram_init(void); #define BR_MSEL 0x000000E0 #define BR_MSEL_SHIFT 5 #define BR_MS_GPCM 0x00000000 /* GPCM */ +#if !defined(CONFIG_MPC834x) && !defined(CONFIG_MPC8360) #define BR_MS_FCM 0x00000020 /* FCM */ -#ifdef CONFIG_MPC83xx +#endif +#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8360) #define BR_MS_SDRAM 0x00000060 /* SDRAM */ #elif defined(CONFIG_MPC85xx) #define BR_MS_SDRAM 0x00000000 /* SDRAM */ @@ -138,8 +140,10 @@ void lbc_sdram_init(void); #define OR_GPCM_EHTR_SHIFT 1 #define OR_GPCM_EHTR_CLEAR 0x00000000 #define OR_GPCM_EHTR_SET 0x00000002 +#if !defined(CONFIG_MPC8308) #define OR_GPCM_EAD 0x00000001 #define OR_GPCM_EAD_SHIFT 0 +#endif /* helpers to convert values into an OR address mask (GPCM mode) */ #define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */ @@ -196,8 +200,10 @@ void lbc_sdram_init(void); #define OR_SDRAM_XAM_SHIFT 13 #define OR_SDRAM_COLS 0x00001C00 #define OR_SDRAM_COLS_SHIFT 10 +#define OR_SDRAM_MIN_COLS 7 #define OR_SDRAM_ROWS 0x000001C0 #define OR_SDRAM_ROWS_SHIFT 6 +#define OR_SDRAM_MIN_ROWS 9 #define OR_SDRAM_PMSEL 0x00000020 #define OR_SDRAM_PMSEL_SHIFT 5 #define OR_SDRAM_EAD 0x00000001 -- cgit