From fbfd92bf9bdc39d6537806ab58a83a48e5a2c004 Mon Sep 17 00:00:00 2001 From: Lukas Auer Date: Wed, 21 Aug 2019 21:14:43 +0200 Subject: riscv: add run mode configuration for SPL U-Boot SPL can be run in a different privilege mode from U-Boot proper. Add new configuration entries for SPL to allow the run mode to be configured independently of U-Boot proper. Extend all uses of the CONFIG_RISCV_SMODE and CONFIG_RISCV_MMODE configuration symbols to also cover the SPL equivalents. Ensure that files compatible with only one privilege mode are not included in builds targeting an incompatible privilege mode. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Anup Patel --- arch/riscv/cpu/ax25/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/riscv/cpu/ax25/Kconfig') diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index 6b4b92e692..f4b59cb71d 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/ax25/Kconfig @@ -4,8 +4,8 @@ config RISCV_NDS imply CPU imply CPU_RISCV imply RISCV_TIMER - imply ANDES_PLIC if RISCV_MMODE - imply ANDES_PLMT if RISCV_MMODE + imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE) + imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE) help Run U-Boot on AndeStar V5 platforms and use some specific features which are provided by Andes Technology AndeStar V5 families. @@ -14,7 +14,7 @@ if RISCV_NDS config RISCV_NDS_CACHE bool "AndeStar V5 families specific cache support" - depends on RISCV_MMODE + depends on RISCV_MMODE || SPL_RISCV_MMODE help Provide Andes Technology AndeStar V5 families specific cache support. -- cgit