From 7045ed9f1ad9bb2b8d19f3b5d39d7e1be8da36a6 Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Wed, 28 Aug 2019 18:46:09 +0800 Subject: riscv: cache: Flush L2 cache before jump to linux Flush and disable L2 cache in dcache_disable() which will be called in cleanup_before_linux() before jump to linux. The sequence will be preferred as below: L1 flush -> L1 disable -> L2 flush -> L2 disable Signed-off-by: Rick Chen Cc: KC Lin Reviewed-by: Bin Meng --- arch/riscv/cpu/ax25/cache.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/riscv/cpu/ax25/cache.c') diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index cd95058d9d..8f5455e519 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/ax25/cache.c @@ -5,6 +5,9 @@ */ #include +#include +#include +#include void flush_dcache_all(void) { @@ -59,11 +62,18 @@ void dcache_enable(void) { #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE + struct udevice *dev = NULL; + asm volatile ( "csrr t1, mcache_ctl\n\t" "ori t0, t1, 0x2\n\t" "csrw mcache_ctl, t0\n\t" ); + + uclass_find_first_device(UCLASS_CACHE, &dev); + + if (dev) + cache_enable(dev); #endif #endif } @@ -72,12 +82,19 @@ void dcache_disable(void) { #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE + struct udevice *dev = NULL; + asm volatile ( "fence\n\t" "csrr t1, mcache_ctl\n\t" "andi t0, t1, ~0x2\n\t" "csrw mcache_ctl, t0\n\t" ); + + uclass_find_first_device(UCLASS_CACHE, &dev); + + if (dev) + cache_disable(dev); #endif #endif } -- cgit From 61ce84b2cf1a6672c8e402ce8174554b25629692 Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Wed, 28 Aug 2019 18:46:11 +0800 Subject: riscv: cache: use CCTL to flush d-cache Use CCTL command to do d-cache write back and invalidate instead of fence. Signed-off-by: Rick Chen Cc: KC Lin Reviewed-by: Bin Meng --- arch/riscv/cpu/ax25/cache.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) (limited to 'arch/riscv/cpu/ax25/cache.c') diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index 8f5455e519..41de30cc02 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/ax25/cache.c @@ -8,17 +8,21 @@ #include #include #include +#include + +#ifdef CONFIG_RISCV_NDS_CACHE +/* mcctlcommand */ +#define CCTL_REG_MCCTLCOMMAND_NUM 0x7cc + +/* D-cache operation */ +#define CCTL_L1D_WBINVAL_ALL 6 +#endif void flush_dcache_all(void) { - /* - * Andes' AX25 does not have a coherence agent. U-Boot must use data - * cache flush and invalidate functions to keep data in the system - * coherent. - * The implementation of the fence instruction in the AX25 flushes the - * data cache and is used for this purpose. - */ - asm volatile ("fence" ::: "memory"); +#ifdef CONFIG_RISCV_NDS_CACHE + csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL); +#endif } void flush_dcache_range(unsigned long start, unsigned long end) @@ -84,8 +88,8 @@ void dcache_disable(void) #ifdef CONFIG_RISCV_NDS_CACHE struct udevice *dev = NULL; + csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL); asm volatile ( - "fence\n\t" "csrr t1, mcache_ctl\n\t" "andi t0, t1, ~0x2\n\t" "csrw mcache_ctl, t0\n\t" -- cgit