From fdff1f96a6505bccb258f5b52e6c94c7e0b29512 Mon Sep 17 00:00:00 2001 From: Anup Patel <Anup.Patel@wdc.com> Date: Mon, 25 Feb 2019 08:14:10 +0000 Subject: riscv: Rename cpu/qemu to cpu/generic The QEMU CPU support under arch/riscv is pretty much generic and works fine for SiFive Unleashed as well. In fact, there will be quite a few RISC-V SOCs for which QEMU CPU support will work fine. This patch renames cpu/qemu to cpu/generic to indicate the above fact. If there are SOC specific errata workarounds required in cpu/generic then those can be done at runtime in cpu/generic based on CPU vendor specific DT compatible string. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> --- arch/riscv/cpu/generic/dram.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 arch/riscv/cpu/generic/dram.c (limited to 'arch/riscv/cpu/generic/dram.c') diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c new file mode 100644 index 0000000000..84d87d2a7f --- /dev/null +++ b/arch/riscv/cpu/generic/dram.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + */ + +#include <common.h> +#include <fdtdec.h> + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} -- cgit