From cf6ee112d802bc378172cfa5db3a430509cc82d8 Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Wed, 28 Aug 2019 18:46:10 +0800 Subject: riscv: dts: move out AE350 L2 node from cpus node When L2 node exists inside cpus node, uclass_get_device can not parse L2 node successfully. So move it outside from cpus node. Also add tag-ram-ctl and data-ram-ctl attributes for v5l2 cache controller driver. This can adjust timing by requirement from dtb to improve performance. Signed-off-by: Rick Chen Cc: KC Lin Reviewed-by: Bin Meng --- arch/riscv/dts/ae350_64.dts | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) (limited to 'arch/riscv/dts/ae350_64.dts') diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts index 705491a8e4..d8f00f8d3a 100644 --- a/arch/riscv/dts/ae350_64.dts +++ b/arch/riscv/dts/ae350_64.dts @@ -62,13 +62,18 @@ compatible = "riscv,cpu-intc"; }; }; + }; - L2: l2-cache@e0500000 { - compatible = "cache"; - cache-level = <2>; - cache-size = <0x40000>; - reg = <0x0 0xe0500000 0x0 0x40000>; - }; + L2: l2-cache@e0500000 { + compatible = "v5l2cache"; + cache-level = <2>; + cache-size = <0x40000>; + reg = <0x0 0xe0500000 0x0 0x40000>; + andes,inst-prefetch = <3>; + andes,data-prefetch = <3>; + /* The value format is */ + andes,tag-ram-ctl = <0 0>; + andes,data-ram-ctl = <0 0>; }; memory@0 { -- cgit