From 5ce50206ed24080707946849d3542534fadf8cbf Mon Sep 17 00:00:00 2001
From: Pragnesh Patel <pragnesh.patel@sifive.com>
Date: Fri, 29 May 2020 12:14:51 +0530
Subject: riscv: sifive: fu540: enable all cache ways from U-Boot proper

Add L2 cache node to enable all cache ways from U-Boot proper.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
---
 arch/riscv/include/asm/arch-fu540/cache.h | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 arch/riscv/include/asm/arch-fu540/cache.h

(limited to 'arch/riscv/include/asm/arch-fu540/cache.h')

diff --git a/arch/riscv/include/asm/arch-fu540/cache.h b/arch/riscv/include/asm/arch-fu540/cache.h
new file mode 100644
index 0000000000..135a17c679
--- /dev/null
+++ b/arch/riscv/include/asm/arch-fu540/cache.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 SiFive, Inc.
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel@sifve.com>
+ */
+
+#ifndef _CACHE_SIFIVE_H
+#define _CACHE_SIFIVE_H
+
+int cache_enable_ways(void);
+
+#endif /* _CACHE_SIFIVE_H */
-- 
cgit