From 01cdef22ee455a4e67775b91e7f4c2a38c896159 Mon Sep 17 00:00:00 2001
From: Pragnesh Patel <pragnesh.patel@sifive.com>
Date: Fri, 29 May 2020 11:33:35 +0530
Subject: riscv: sifive: fu540: add SPL configuration

Add a support for SPL which will boot from L2 LIM (0x0800_0000) and
then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin)
from MMC boot devices.

SPL related code is leveraged from FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
---
 arch/riscv/cpu/fu540/Makefile                   |  4 ++++
 arch/riscv/cpu/fu540/spl.c                      | 23 +++++++++++++++++++++++
 arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi |  5 +++++
 arch/riscv/include/asm/arch-fu540/spl.h         | 14 ++++++++++++++
 4 files changed, 46 insertions(+)
 create mode 100644 arch/riscv/cpu/fu540/spl.c
 create mode 100644 arch/riscv/include/asm/arch-fu540/spl.h

(limited to 'arch/riscv')

diff --git a/arch/riscv/cpu/fu540/Makefile b/arch/riscv/cpu/fu540/Makefile
index 44700d998c..043fb961a5 100644
--- a/arch/riscv/cpu/fu540/Makefile
+++ b/arch/riscv/cpu/fu540/Makefile
@@ -3,5 +3,9 @@
 # Copyright (C) 2020 SiFive, Inc
 # Pragnesh Patel <pragnesh.patel@sifive.com>
 
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-y += spl.o
+else
 obj-y += dram.o
 obj-y += cpu.o
+endif
diff --git a/arch/riscv/cpu/fu540/spl.c b/arch/riscv/cpu/fu540/spl.c
new file mode 100644
index 0000000000..a2034e933f
--- /dev/null
+++ b/arch/riscv/cpu/fu540/spl.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 SiFive, Inc
+ * Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#include <dm.h>
+#include <log.h>
+
+int soc_spl_init(void)
+{
+	int ret;
+	struct udevice *dev;
+
+	/* DDR init */
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		debug("DRAM init failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index 9787332bf1..303806454b 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -4,6 +4,7 @@
  */
 
 #include "fu540-c000-u-boot.dtsi"
+#include "fu540-hifive-unleashed-a00-ddr.dtsi"
 
 / {
 	aliases {
@@ -26,3 +27,7 @@
 		u-boot,dm-spl;
 	};
 };
+
+&gpio {
+	u-boot,dm-spl;
+};
diff --git a/arch/riscv/include/asm/arch-fu540/spl.h b/arch/riscv/include/asm/arch-fu540/spl.h
new file mode 100644
index 0000000000..0c188be747
--- /dev/null
+++ b/arch/riscv/include/asm/arch-fu540/spl.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 SiFive, Inc.
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel@sifve.com>
+ */
+
+#ifndef _SPL_SIFIVE_H
+#define _SPL_SIFIVE_H
+
+int soc_spl_init(void);
+
+#endif /* _SPL_SIFIVE_H */
-- 
cgit