From 117a433d9e66ff986c97f60c2f6daa167f8ee729 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 26 Sep 2018 06:55:06 -0700 Subject: riscv: kconfig: Normalize architecture name spelling It's RISC-V that is the official name, not RISCV. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Reviewed-by: Rick Chen --- arch/riscv/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/riscv') diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 20a43d88e3..49f87de1dc 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -1,4 +1,4 @@ -menu "RISCV architecture" +menu "RISC-V architecture" depends on RISCV config SYS_ARCH @@ -20,13 +20,13 @@ choice default CPU_RISCV_32 config CPU_RISCV_32 - bool "RISCV 32 bit" + bool "RISC-V 32-bit" select 32BIT help Choose this option to build an U-Boot for RISCV32 architecture. config CPU_RISCV_64 - bool "RISCV 64 bit" + bool "RISC-V 64-bit" select 64BIT help Choose this option to build an U-Boot for RISCV64 architecture. -- cgit From 3ad4866dd7796718db939247e39f5ab9a121f9e3 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 26 Sep 2018 06:55:07 -0700 Subject: riscv: Remove setup.h This was copied from ARM, and does not apply to RISC-V. While we are here, bootm.h is eventually removed as its content is only the inclusion of setup.h. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- arch/riscv/include/asm/bootm.h | 13 --- arch/riscv/include/asm/setup.h | 194 ----------------------------------------- arch/riscv/lib/bootm.c | 1 - 3 files changed, 208 deletions(-) delete mode 100644 arch/riscv/include/asm/bootm.h delete mode 100644 arch/riscv/include/asm/setup.h (limited to 'arch/riscv') diff --git a/arch/riscv/include/asm/bootm.h b/arch/riscv/include/asm/bootm.h deleted file mode 100644 index 67863458ec..0000000000 --- a/arch/riscv/include/asm/bootm.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2013, Google Inc. - * - * Copyright (C) 2011 - * Corscience GmbH & Co. KG - Simon Schwarz - */ -#ifndef NDS32_BOOTM_H -#define NDS32_BOOTM_H - -#include - -#endif diff --git a/arch/riscv/include/asm/setup.h b/arch/riscv/include/asm/setup.h deleted file mode 100644 index ff8de167c6..0000000000 --- a/arch/riscv/include/asm/setup.h +++ /dev/null @@ -1,194 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * linux/arch/nds32/include/asm/setup.h - * - * Copyright (C) 1997-1999 Russell King - * Copyright (C) 2008 Andes Technology Corporation - * Copyright (C) 2013 Ken Kuo (ken_kuo@andestech.com) - * Copyright (C) 2017 Rick Chen (rick@andestech.com) - * - * Structure passed to kernel to tell it about the - * hardware it's running on. See Documentation/arm/Setup - * for more info. - */ -#ifndef __RISCV_SETUP_H -#define __RISCV_SETUP_H - -#define COMMAND_LINE_SIZE 256 - -/* The list ends with an ATAG_NONE node. */ -#define ATAG_NONE 0x00000000 - -struct tag_header { - u32 size; - u32 tag; -}; - -/* The list must start with an ATAG_CORE node */ -#define ATAG_CORE 0x54410001 - -struct tag_core { - u32 flags; /* bit 0 = read-only */ - u32 pagesize; - u32 rootdev; -}; - -/* it is allowed to have multiple ATAG_MEM nodes */ -#define ATAG_MEM 0x54410002 - -struct tag_mem32 { - u32 size; - u32 start; /* physical start address */ -}; - -/* VGA text type displays */ -#define ATAG_VIDEOTEXT 0x54410003 - -struct tag_videotext { - u8 x; - u8 y; - u16 video_page; - u8 video_mode; - u8 video_cols; - u16 video_ega_bx; - u8 video_lines; - u8 video_isvga; - u16 video_points; -}; - -/* describes how the ramdisk will be used in kernel */ -#define ATAG_RAMDISK 0x54410004 - -struct tag_ramdisk { - u32 flags; /* bit 0 = load, bit 1 = prompt */ - u32 size; /* decompressed ramdisk size in _kilo_ bytes */ - u32 start; /* starting block of floppy-based RAM disk image */ -}; - -/* - * this one accidentally used virtual addresses - as such, - * it's deprecated. - * describes where the compressed ramdisk image lives (virtual address) - */ -#define ATAG_INITRD 0x54410005 - -/* describes where the compressed ramdisk image lives (physical address) */ -#define ATAG_INITRD2 0x54420005 - -struct tag_initrd { - u32 start; /* physical start address */ - u32 size; /* size of compressed ramdisk image in bytes */ -}; - -/* board serial number. "64 bits should be enough for everybody" */ -#define ATAG_SERIAL 0x54410006 - -struct tag_serialnr { - u32 low; - u32 high; -}; - -/* board revision */ -#define ATAG_REVISION 0x54410007 - -struct tag_revision { - u32 rev; -}; - -/* initial values for vesafb-type framebuffers. see struct screen_info - * in include/linux/tty.h - */ -#define ATAG_VIDEOLFB 0x54410008 - -struct tag_videolfb { - u16 lfb_width; - u16 lfb_height; - u16 lfb_depth; - u16 lfb_linelength; - u32 lfb_base; - u32 lfb_size; - u8 red_size; - u8 red_pos; - u8 green_size; - u8 green_pos; - u8 blue_size; - u8 blue_pos; - u8 rsvd_size; - u8 rsvd_pos; -}; - -/* command line: \0 terminated string */ -#define ATAG_CMDLINE 0x54410009 - -struct tag_cmdline { - char cmdline[COMMAND_LINE_SIZE]; -}; - -struct tag { - struct tag_header hdr; - union { - struct tag_core core; - struct tag_mem32 mem; - struct tag_videotext videotext; - struct tag_ramdisk ramdisk; - struct tag_initrd initrd; - struct tag_serialnr serialnr; - struct tag_revision revision; - struct tag_videolfb videolfb; - struct tag_cmdline cmdline; - } u; -}; - -struct tagtable { - u32 tag; - int (*parse)(const struct tag *); -}; - -#define tag_member_present(_tag, member) \ - typeof(_tag) (tag) = (_tag); \ - ((unsigned long)(&((struct tag *)0L)->member + 1) \ - <= (tag)->hdr.size * 4) - -#define tag_next(_t) \ - typeof(_t) (t) = (_t); \ - ((struct tag *)((u32 *)(t) + (t)->hdr.size)) -#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2) - -#define for_each_tag(_t, base) \ - typeof(_t) (t) = (_t); \ - for (t = base; t->hdr.size; t = tag_next(t)) - -#ifdef __KERNEL__ - -#define __tag __used __attribute__((__section__(".taglist"))) -#define __tagtable(tag, fn) \ -static struct tagtable __tagtable_##fn __tag = { tag, fn } - -/* - * Memory map description - */ -#define NR_BANKS 8 - -struct meminfo { - int nr_banks; - struct { - unsigned long start; - unsigned long size; - int node; - } bank[NR_BANKS]; -}; - -/* - * Early command line parameters. - */ -struct early_params { - const char *arg; - void (*fn)(char **p); -}; - -#define __early_param(name, fn) \ -static struct early_params __early_##fn __used \ -__attribute__((__section__("__early_param"))) = { name, fn } - -#endif -#endif diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 2610a57bbf..6662aff4fd 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -11,7 +11,6 @@ #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; -- cgit From 4afeedf1728fe7e992b460d0369a06f8bfe4f9f3 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 26 Sep 2018 06:55:08 -0700 Subject: riscv: bootm: Correct the 1st kernel argument to hart id The first argument of Linux kernel is the risc-v core hart id, from which the kernel is booted from. It is not the mach_id, which seems to be copied from arm. While we are here, this also changes the Linux kernel entry parameters' type to support both 32-bit and 64-bit. Note the hart id is hardcoded to zero for now, and we should change to fill in it with the value read from mhartid CSR of the hart which this routine is currently running on. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Reviewed-by: Rick Chen --- arch/riscv/lib/bootm.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) (limited to 'arch/riscv') diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 6662aff4fd..6893108fe3 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -25,10 +25,7 @@ int arch_fixup_fdt(void *blob) int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) { - bd_t *bd = gd->bd; - char *s; - int machid = bd->bi_arch_number; - void (*theKernel)(int arch, uint params); + void (*kernel)(ulong hart, void *dtb); /* * allow the PREP bootm subcommand, it is required for bootm to work @@ -39,18 +36,12 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) return 1; - theKernel = (void (*)(int, uint))images->ep; - - s = env_get("machid"); - if (s) { - machid = simple_strtoul(s, NULL, 16); - printf("Using machid 0x%x from environment\n", machid); - } + kernel = (void (*)(ulong, void *))images->ep; bootstage_mark(BOOTSTAGE_ID_RUN_OS); debug("## Transferring control to Linux (at address %08lx) ...\n", - (ulong)theKernel); + (ulong)kernel); if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { #ifdef CONFIG_OF_LIBFDT @@ -66,8 +57,9 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) printf("\nStarting kernel ...\n\n"); cleanup_before_linux(); + /* TODO: hardcode the hart id to zero for now */ if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) - theKernel(machid, (unsigned long)images->ft_addr); + kernel(0, images->ft_addr); /* does not return */ -- cgit From 8cdc6b58d71b849bb687d3d914b9b1fa26136264 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 26 Sep 2018 06:55:09 -0700 Subject: riscv: Remove mach type Since the mach_id is not used by RISC-V, remove it. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- arch/riscv/include/asm/mach-types.h | 29 ----------------------------- arch/riscv/include/asm/u-boot.h | 1 - 2 files changed, 30 deletions(-) delete mode 100644 arch/riscv/include/asm/mach-types.h (limited to 'arch/riscv') diff --git a/arch/riscv/include/asm/mach-types.h b/arch/riscv/include/asm/mach-types.h deleted file mode 100644 index f219cedfd3..0000000000 --- a/arch/riscv/include/asm/mach-types.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Andes Technology Corporation - * Rick Chen, Andes Technology Corporation - */ - -#ifndef __ASM_RISCV_MACH_TYPE_H -#define __ASM_RISCV_MACH_TYPE_H - -#ifndef __ASSEMBLY__ -/* The type of machine we're running on */ -extern unsigned int __machine_arch_type; -#endif - -#define MACH_TYPE_AE350 1 - -#ifdef CONFIG_ARCH_AE350 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_AE350 -# endif -# define machine_is_ae350() (machine_arch_type == MACH_TYPE_AE350) -#else -# define machine_is_ae350() (1) -#endif - -#endif /* __ASM_RISCV_MACH_TYPE_H */ diff --git a/arch/riscv/include/asm/u-boot.h b/arch/riscv/include/asm/u-boot.h index 9e5b32d33e..3186835e0a 100644 --- a/arch/riscv/include/asm/u-boot.h +++ b/arch/riscv/include/asm/u-boot.h @@ -23,7 +23,6 @@ #include typedef struct bd_info { - unsigned long bi_arch_number; /* unique id for this board */ unsigned long bi_boot_params; /* where this board expects params */ unsigned long bi_memstart; /* start of DRAM memory */ unsigned long bi_memsize; /* size of DRAM memory in bytes */ -- cgit From dfb828ed1cc8a39a9211179c6848dfc65718e1a0 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 26 Sep 2018 06:55:11 -0700 Subject: riscv: Move the linker script to the CPU root directory The linker script can be shared by all RISC-V targets. Move it to a common place. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- arch/riscv/cpu/ax25/u-boot.lds | 90 ------------------------------------------ arch/riscv/cpu/u-boot.lds | 90 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 90 insertions(+), 90 deletions(-) delete mode 100644 arch/riscv/cpu/ax25/u-boot.lds create mode 100644 arch/riscv/cpu/u-boot.lds (limited to 'arch/riscv') diff --git a/arch/riscv/cpu/ax25/u-boot.lds b/arch/riscv/cpu/ax25/u-boot.lds deleted file mode 100644 index c50b9642f1..0000000000 --- a/arch/riscv/cpu/ax25/u-boot.lds +++ /dev/null @@ -1,90 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Andes Technology Corporation - * Rick Chen, Andes Technology Corporation - */ -OUTPUT_ARCH("riscv") -ENTRY(_start) - -SECTIONS -{ - . = ALIGN(4); - .text : - { - arch/riscv/cpu/ax25/start.o (.text) - } - - /* This needs to come before *(.text*) */ - .efi_runtime : { - __efi_runtime_start = .; - *(.text.efi_runtime*) - *(.rodata.efi_runtime*) - *(.data.efi_runtime*) - __efi_runtime_stop = .; - } - - .text_rest : - { - *(.text*) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - __global_pointer$ = . + 0x800; - *(.data*) - } - . = ALIGN(4); - - .got : { - __got_start = .; - *(.got.plt) *(.got) - __got_end = .; - } - - . = ALIGN(4); - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN(4); - - .efi_runtime_rel : { - __efi_runtime_rel_start = .; - *(.rel*.efi_runtime) - *(.rel*.efi_runtime.*) - __efi_runtime_rel_stop = .; - } - - . = ALIGN(4); - - /DISCARD/ : { *(.rela.plt*) } - .rela.dyn : { - __rel_dyn_start = .; - *(.rela*) - __rel_dyn_end = .; - } - - . = ALIGN(4); - - .dynsym : { - __dyn_sym_start = .; - *(.dynsym) - __dyn_sym_end = .; - } - - . = ALIGN(4); - - _end = .; - - .bss : { - __bss_start = .; - *(.bss*) - . = ALIGN(4); - __bss_end = .; - } - -} diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds new file mode 100644 index 0000000000..c50b9642f1 --- /dev/null +++ b/arch/riscv/cpu/u-boot.lds @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + */ +OUTPUT_ARCH("riscv") +ENTRY(_start) + +SECTIONS +{ + . = ALIGN(4); + .text : + { + arch/riscv/cpu/ax25/start.o (.text) + } + + /* This needs to come before *(.text*) */ + .efi_runtime : { + __efi_runtime_start = .; + *(.text.efi_runtime*) + *(.rodata.efi_runtime*) + *(.data.efi_runtime*) + __efi_runtime_stop = .; + } + + .text_rest : + { + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + __global_pointer$ = . + 0x800; + *(.data*) + } + . = ALIGN(4); + + .got : { + __got_start = .; + *(.got.plt) *(.got) + __got_end = .; + } + + . = ALIGN(4); + + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + + .efi_runtime_rel : { + __efi_runtime_rel_start = .; + *(.rel*.efi_runtime) + *(.rel*.efi_runtime.*) + __efi_runtime_rel_stop = .; + } + + . = ALIGN(4); + + /DISCARD/ : { *(.rela.plt*) } + .rela.dyn : { + __rel_dyn_start = .; + *(.rela*) + __rel_dyn_end = .; + } + + . = ALIGN(4); + + .dynsym : { + __dyn_sym_start = .; + *(.dynsym) + __dyn_sym_end = .; + } + + . = ALIGN(4); + + _end = .; + + .bss : { + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } + +} -- cgit From 3d6015651bcb09d2a26e325e533c78525140d613 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 26 Sep 2018 06:55:12 -0700 Subject: riscv: Fix coding style issues in the linker script There are several coding style issues in the linker script. Fix them. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- arch/riscv/cpu/u-boot.lds | 58 +++++++++++++++++++++++------------------------ 1 file changed, 28 insertions(+), 30 deletions(-) (limited to 'arch/riscv') diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds index c50b9642f1..f414473e54 100644 --- a/arch/riscv/cpu/u-boot.lds +++ b/arch/riscv/cpu/u-boot.lds @@ -3,28 +3,27 @@ * Copyright (C) 2017 Andes Technology Corporation * Rick Chen, Andes Technology Corporation */ + OUTPUT_ARCH("riscv") ENTRY(_start) SECTIONS { . = ALIGN(4); - .text : - { + .text : { arch/riscv/cpu/ax25/start.o (.text) } /* This needs to come before *(.text*) */ .efi_runtime : { - __efi_runtime_start = .; + __efi_runtime_start = .; *(.text.efi_runtime*) *(.rodata.efi_runtime*) *(.data.efi_runtime*) - __efi_runtime_stop = .; + __efi_runtime_stop = .; } - .text_rest : - { + .text_rest : { *(.text*) } @@ -39,10 +38,10 @@ SECTIONS . = ALIGN(4); .got : { - __got_start = .; - *(.got.plt) *(.got) - __got_end = .; - } + __got_start = .; + *(.got.plt) *(.got) + __got_end = .; + } . = ALIGN(4); @@ -50,41 +49,40 @@ SECTIONS KEEP(*(SORT(.u_boot_list*))); } - . = ALIGN(4); + . = ALIGN(4); .efi_runtime_rel : { - __efi_runtime_rel_start = .; + __efi_runtime_rel_start = .; *(.rel*.efi_runtime) *(.rel*.efi_runtime.*) - __efi_runtime_rel_stop = .; + __efi_runtime_rel_stop = .; } - . = ALIGN(4); + . = ALIGN(4); - /DISCARD/ : { *(.rela.plt*) } - .rela.dyn : { - __rel_dyn_start = .; - *(.rela*) - __rel_dyn_end = .; - } + /DISCARD/ : { *(.rela.plt*) } + .rela.dyn : { + __rel_dyn_start = .; + *(.rela*) + __rel_dyn_end = .; + } - . = ALIGN(4); + . = ALIGN(4); - .dynsym : { - __dyn_sym_start = .; - *(.dynsym) - __dyn_sym_end = .; - } + .dynsym : { + __dyn_sym_start = .; + *(.dynsym) + __dyn_sym_end = .; + } - . = ALIGN(4); + . = ALIGN(4); _end = .; .bss : { - __bss_start = .; - *(.bss*) + __bss_start = .; + *(.bss*) . = ALIGN(4); __bss_end = .; } - } -- cgit From ce7a8e0740f1f9ec915109392184d335ba231448 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 26 Sep 2018 06:55:13 -0700 Subject: riscv: Explicitly pass -march and -mabi to the compiler At present the compiler flag against which architecture and abi variant the riscv image is built for is not explicitly indicated which means the default compiler configuration is used. But this does not work if we want to build a different target (eg: 32-bit riscv images using a toolchain configured for 64-bit riscv). Fix this by explicitly passing -march and -mabi to the compiler. Since generically we don't use floating point in U-Boot, specify the RV[32|64]IMA ISA and software floating ABI. This also fix some alignment coding style issues. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- arch/riscv/config.mk | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch/riscv') diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk index c0b3858edd..b235ae1413 100644 --- a/arch/riscv/config.mk +++ b/arch/riscv/config.mk @@ -18,12 +18,16 @@ endif 64bit-emul := elf64lriscv ifdef CONFIG_32BIT +PLATFORM_CPPFLAGS += -march=rv32ima -mabi=ilp32 PLATFORM_LDFLAGS += -m $(32bit-emul) +CFLAGS_EFI += -march=rv32ima -mabi=ilp32 EFI_LDS := elf_riscv32_efi.lds endif ifdef CONFIG_64BIT +PLATFORM_CPPFLAGS += -march=rv64ima -mabi=lp64 PLATFORM_LDFLAGS += -m $(64bit-emul) +CFLAGS_EFI += -march=rv64ima -mabi=lp64 EFI_LDS := elf_riscv64_efi.lds endif @@ -31,8 +35,8 @@ CONFIG_STANDALONE_LOAD_ADDR = 0x00000000 \ -T $(srctree)/examples/standalone/riscv.lds PLATFORM_CPPFLAGS += -ffixed-gp -fpic -PLATFORM_RELFLAGS += -fno-common -gdwarf-2 -ffunction-sections -LDFLAGS_u-boot += --gc-sections -static -pie +PLATFORM_RELFLAGS += -fno-common -gdwarf-2 -ffunction-sections +LDFLAGS_u-boot += --gc-sections -static -pie EFI_CRT0 := crt0_riscv_efi.o EFI_RELOC := reloc_riscv_efi.o -- cgit From 2fab2e9c88c4ceba9156411474b8cfceadeb61fa Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 26 Sep 2018 06:55:14 -0700 Subject: riscv: Add a helper routine to print CPU information This adds a helper routine to print CPU information. Currently it prints all the instruction set extensions that the processor core supports. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- arch/riscv/Makefile | 1 + arch/riscv/cpu/Makefile | 5 ++ arch/riscv/cpu/cpu.c | 49 +++++++++++++++++ arch/riscv/include/asm/csr.h | 124 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 179 insertions(+) create mode 100644 arch/riscv/cpu/Makefile create mode 100644 arch/riscv/cpu/cpu.c create mode 100644 arch/riscv/include/asm/csr.h (limited to 'arch/riscv') diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 084888ad8b..af432e16ff 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -5,5 +5,6 @@ head-y := arch/riscv/cpu/$(CPU)/start.o +libs-y += arch/riscv/cpu/ libs-y += arch/riscv/cpu/$(CPU)/ libs-y += arch/riscv/lib/ diff --git a/arch/riscv/cpu/Makefile b/arch/riscv/cpu/Makefile new file mode 100644 index 0000000000..63de163e3f --- /dev/null +++ b/arch/riscv/cpu/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, Bin Meng + +obj-y += cpu.o diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c new file mode 100644 index 0000000000..ae57fb8313 --- /dev/null +++ b/arch/riscv/cpu/cpu.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + */ + +#include +#include + +enum { + ISA_INVALID = 0, + ISA_32BIT, + ISA_64BIT, + ISA_128BIT +}; + +static const char * const isa_bits[] = { + [ISA_INVALID] = NULL, + [ISA_32BIT] = "32", + [ISA_64BIT] = "64", + [ISA_128BIT] = "128" +}; + +static inline bool supports_extension(char ext) +{ + return csr_read(misa) & (1 << (ext - 'a')); +} + +int print_cpuinfo(void) +{ + char name[32]; + char *s = name; + int bit; + + s += sprintf(name, "rv"); + bit = csr_read(misa) >> (sizeof(long) * 8 - 2); + s += sprintf(s, isa_bits[bit]); + + supports_extension('i') ? *s++ = 'i' : 'r'; + supports_extension('m') ? *s++ = 'm' : 'i'; + supports_extension('a') ? *s++ = 'a' : 's'; + supports_extension('f') ? *s++ = 'f' : 'c'; + supports_extension('d') ? *s++ = 'd' : '-'; + supports_extension('c') ? *s++ = 'c' : 'v'; + *s++ = '\0'; + + printf("CPU: %s\n", name); + + return 0; +} diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h new file mode 100644 index 0000000000..50fccea5c8 --- /dev/null +++ b/arch/riscv/include/asm/csr.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2015 Regents of the University of California + * + * Taken from Linux arch/riscv/include/asm/csr.h + */ + +#ifndef _ASM_RISCV_CSR_H +#define _ASM_RISCV_CSR_H + +/* Status register flags */ +#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ +#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ +#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ +#define SR_SUM _AC(0x00040000, UL) /* Supervisor access User Memory */ + +#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ +#define SR_FS_OFF _AC(0x00000000, UL) +#define SR_FS_INITIAL _AC(0x00002000, UL) +#define SR_FS_CLEAN _AC(0x00004000, UL) +#define SR_FS_DIRTY _AC(0x00006000, UL) + +#define SR_XS _AC(0x00018000, UL) /* Extension Status */ +#define SR_XS_OFF _AC(0x00000000, UL) +#define SR_XS_INITIAL _AC(0x00008000, UL) +#define SR_XS_CLEAN _AC(0x00010000, UL) +#define SR_XS_DIRTY _AC(0x00018000, UL) + +#ifndef CONFIG_64BIT +#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ +#else +#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ +#endif + +/* SATP flags */ +#if __riscv_xlen == 32 +#define SATP_PPN _AC(0x003FFFFF, UL) +#define SATP_MODE_32 _AC(0x80000000, UL) +#define SATP_MODE SATP_MODE_32 +#else +#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) +#define SATP_MODE_39 _AC(0x8000000000000000, UL) +#define SATP_MODE SATP_MODE_39 +#endif + +/* Interrupt Enable and Interrupt Pending flags */ +#define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */ +#define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */ + +#define EXC_INST_MISALIGNED 0 +#define EXC_INST_ACCESS 1 +#define EXC_BREAKPOINT 3 +#define EXC_LOAD_ACCESS 5 +#define EXC_STORE_ACCESS 7 +#define EXC_SYSCALL 8 +#define EXC_INST_PAGE_FAULT 12 +#define EXC_LOAD_PAGE_FAULT 13 +#define EXC_STORE_PAGE_FAULT 15 + +#ifndef __ASSEMBLY__ + +#define csr_swap(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ("csrrw %0, " #csr ", %1" \ + : "=r" (__v) : "rK" (__v) \ + : "memory"); \ + __v; \ +}) + +#define csr_read(csr) \ +({ \ + register unsigned long __v; \ + __asm__ __volatile__ ("csrr %0, " #csr \ + : "=r" (__v) : \ + : "memory"); \ + __v; \ +}) + +#define csr_write(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ("csrw " #csr ", %0" \ + : : "rK" (__v) \ + : "memory"); \ +}) + +#define csr_read_set(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ("csrrs %0, " #csr ", %1" \ + : "=r" (__v) : "rK" (__v) \ + : "memory"); \ + __v; \ +}) + +#define csr_set(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ("csrs " #csr ", %0" \ + : : "rK" (__v) \ + : "memory"); \ +}) + +#define csr_read_clear(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ("csrrc %0, " #csr ", %1" \ + : "=r" (__v) : "rK" (__v) \ + : "memory"); \ + __v; \ +}) + +#define csr_clear(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ("csrc " #csr ", %0" \ + : : "rK" (__v) \ + : "memory"); \ +}) + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_RISCV_CSR_H */ -- cgit From e5ea1e586076b6c130e16e4a45749fc65679663d Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 26 Sep 2018 06:55:15 -0700 Subject: riscv: Remove CSR read/write defines in encoding.h There is no reason to keep two versions of CSR read/write defines in encoding.h. We already have one set of defines in csr.h, which is from Linux kernel, and let's drop the one in encoding.h. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Reviewed-by: Rick Chen --- arch/riscv/include/asm/encoding.h | 50 ++++----------------------------------- 1 file changed, 4 insertions(+), 46 deletions(-) (limited to 'arch/riscv') diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h index f237a72f06..9ea50ce640 100644 --- a/arch/riscv/include/asm/encoding.h +++ b/arch/riscv/include/asm/encoding.h @@ -128,6 +128,7 @@ ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE))) #ifdef __riscv + #ifdef CONFIG_64BIT # define MSTATUS_SD MSTATUS64_SD # define SSTATUS_SD SSTATUS64_SD @@ -141,53 +142,10 @@ # define MCAUSE_INT MCAUSE32_INT # define MCAUSE_CAUSE MCAUSE32_CAUSE #endif + #define RISCV_PGSHIFT 12 #define RISCV_PGSIZE BIT(RISCV_PGSHIFT) -#ifndef __ASSEMBLER__ - -#ifdef __GNUC__ - -#define read_csr(reg) ({ unsigned long __tmp; \ - asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ - __tmp; }) - -#define write_csr(reg, _val) ({ \ -typeof(_val) (val) = (_val); \ -if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ -else \ - asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) - -#define swap_csr(reg, _val) ({ unsigned long __tmp; \ -typeof(_val) (val) = (_val); \ -if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ -else \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ - __tmp; }) - -#define set_csr(reg, _bit) ({ unsigned long __tmp; \ -typeof(_bit) (bit) = (_bit); \ -if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ -else \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ - __tmp; }) - -#define clear_csr(reg, _bit) ({ unsigned long __tmp; \ -typeof(_bit) (bit) = (_bit); \ -if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ -else \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ - __tmp; }) - -#define rdtime() read_csr(time) -#define rdcycle() read_csr(cycle) -#define rdinstret() read_csr(instret) +#endif /* __riscv */ -#endif -#endif -#endif -#endif +#endif /* RISCV_CSR_ENCODING_H */ -- cgit From ed49ba4dcccb21cee1c32427cf5bbf09521cd8dd Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 26 Sep 2018 06:55:16 -0700 Subject: riscv: bootm: Pass mhartid CSR value to kernel So far this is hardcoded to zero, and we should read the value from mhartid CSR and pass it to Linux kernel. Suggested-by: Lukas Auer Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Reviewed-by: Rick Chen --- arch/riscv/lib/bootm.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/riscv') diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 6893108fe3..a7a9fb921b 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -11,6 +11,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -57,9 +58,9 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) printf("\nStarting kernel ...\n\n"); cleanup_before_linux(); - /* TODO: hardcode the hart id to zero for now */ + if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) - kernel(0, images->ft_addr); + kernel(csr_read(mhartid), images->ft_addr); /* does not return */ -- cgit From b5369c5813aa407139fc137ccbd0944190f15ebc Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 26 Sep 2018 06:55:17 -0700 Subject: riscv: Make start.S available for all targets Currently start.S is inside arch/riscv/cpu/ax25/, but it can be common for all RISC-V targets. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- arch/riscv/Makefile | 2 +- arch/riscv/cpu/Makefile | 2 + arch/riscv/cpu/ax25/Makefile | 2 - arch/riscv/cpu/ax25/start.S | 292 ------------------------------------------- arch/riscv/cpu/start.S | 292 +++++++++++++++++++++++++++++++++++++++++++ arch/riscv/cpu/u-boot.lds | 2 +- 6 files changed, 296 insertions(+), 296 deletions(-) delete mode 100644 arch/riscv/cpu/ax25/start.S create mode 100644 arch/riscv/cpu/start.S (limited to 'arch/riscv') diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index af432e16ff..8fb6a889d8 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -3,7 +3,7 @@ # Copyright (C) 2017 Andes Technology Corporation. # Rick Chen, Andes Technology Corporation -head-y := arch/riscv/cpu/$(CPU)/start.o +head-y := arch/riscv/cpu/start.o libs-y += arch/riscv/cpu/ libs-y += arch/riscv/cpu/$(CPU)/ diff --git a/arch/riscv/cpu/Makefile b/arch/riscv/cpu/Makefile index 63de163e3f..2cc6757fcf 100644 --- a/arch/riscv/cpu/Makefile +++ b/arch/riscv/cpu/Makefile @@ -2,4 +2,6 @@ # # Copyright (C) 2018, Bin Meng +extra-y = start.o + obj-y += cpu.o diff --git a/arch/riscv/cpu/ax25/Makefile b/arch/riscv/cpu/ax25/Makefile index c3f164c122..2ab0342fe8 100644 --- a/arch/riscv/cpu/ax25/Makefile +++ b/arch/riscv/cpu/ax25/Makefile @@ -3,6 +3,4 @@ # Copyright (C) 2017 Andes Technology Corporation # Rick Chen, Andes Technology Corporation -extra-y = start.o - obj-y := cpu.o diff --git a/arch/riscv/cpu/ax25/start.S b/arch/riscv/cpu/ax25/start.S deleted file mode 100644 index 7cd7755190..0000000000 --- a/arch/riscv/cpu/ax25/start.S +++ /dev/null @@ -1,292 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Startup Code for RISC-V Core - * - * Copyright (c) 2017 Microsemi Corporation. - * Copyright (c) 2017 Padmarao Begari - * - * Copyright (C) 2017 Andes Technology Corporation - * Rick Chen, Andes Technology Corporation - */ - -#include -#include -#include -#include -#include - -#ifdef CONFIG_32BIT -#define LREG lw -#define SREG sw -#define REGBYTES 4 -#define RELOC_TYPE R_RISCV_32 -#define SYM_INDEX 0x8 -#define SYM_SIZE 0x10 -#else -#define LREG ld -#define SREG sd -#define REGBYTES 8 -#define RELOC_TYPE R_RISCV_64 -#define SYM_INDEX 0x20 -#define SYM_SIZE 0x18 -#endif - -.section .text -.globl _start -_start: - j handle_reset - -nmi_vector: - j nmi_vector - -trap_vector: - j trap_entry - -.global trap_entry -handle_reset: - li t0, CONFIG_SYS_SDRAM_BASE - SREG a2, 0(t0) - la t0, trap_entry - csrw mtvec, t0 - csrwi mstatus, 0 - csrwi mie, 0 - -/* - * Do CPU critical regs init only at reboot, - * not when booting from ram - */ -#ifdef CONFIG_INIT_CRITICAL - jal cpu_init_crit /* Do CPU critical regs init */ -#endif - -/* - * Set stackpointer in internal/ex RAM to call board_init_f - */ -call_board_init_f: - li t0, -16 - li t1, CONFIG_SYS_INIT_SP_ADDR - and sp, t1, t0 /* force 16 byte alignment */ - -#ifdef CONFIG_DEBUG_UART - jal debug_uart_init -#endif - -call_board_init_f_0: - mv a0, sp - jal board_init_f_alloc_reserve - mv sp, a0 - jal board_init_f_init_reserve - - mv a0, zero /* a0 <-- boot_flags = 0 */ - la t5, board_init_f - jr t5 /* jump to board_init_f() */ - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - */ -.globl relocate_code -relocate_code: - mv s2, a0 /* save addr_sp */ - mv s3, a1 /* save addr of gd */ - mv s4, a2 /* save addr of destination */ - -/* - *Set up the stack - */ -stack_setup: - mv sp, s2 - la t0, _start - sub t6, s4, t0 /* t6 <- relocation offset */ - beq t0, s4, clear_bss /* skip relocation */ - - mv t1, s4 /* t1 <- scratch for copy_loop */ - la t3, __bss_start - sub t3, t3, t0 /* t3 <- __bss_start_ofs */ - add t2, t0, t3 /* t2 <- source end address */ - -copy_loop: - LREG t5, 0(t0) - addi t0, t0, REGBYTES - SREG t5, 0(t1) - addi t1, t1, REGBYTES - blt t0, t2, copy_loop - -/* - * Update dynamic relocations after board_init_f - */ -fix_rela_dyn: - la t1, __rel_dyn_start - la t2, __rel_dyn_end - beq t1, t2, clear_bss - add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */ - add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */ - -/* - * skip first reserved entry: address, type, addend - */ - bne t1, t2, 7f - -6: - LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */ - li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */ - bne t5, t3, 8f /* skip non-RISCV_RELOC entries */ - LREG t3, -(REGBYTES*3)(t1) - LREG t5, -(REGBYTES)(t1) /* t5 <-- addend */ - add t5, t5, t6 /* t5 <-- location to fix up in RAM */ - add t3, t3, t6 /* t3 <-- location to fix up in RAM */ - SREG t5, 0(t3) -7: - addi t1, t1, (REGBYTES*3) - ble t1, t2, 6b - -8: - la t4, __dyn_sym_start - add t4, t4, t6 - -9: - LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */ - srli t0, t5, SYM_INDEX /* t0 <--- sym table index */ - andi t5, t5, 0xFF /* t5 <--- relocation type */ - li t3, RELOC_TYPE - bne t5, t3, 10f /* skip non-addned entries */ - - LREG t3, -(REGBYTES*3)(t1) - li t5, SYM_SIZE - mul t0, t0, t5 - add s1, t4, t0 - LREG t5, REGBYTES(s1) - add t5, t5, t6 /* t5 <-- location to fix up in RAM */ - add t3, t3, t6 /* t3 <-- location to fix up in RAM */ - SREG t5, 0(t3) -10: - addi t1, t1, (REGBYTES*3) - ble t1, t2, 9b - -/* - * trap update -*/ - la t0, trap_entry - add t0, t0, t6 - csrw mtvec, t0 - -clear_bss: - la t0, __bss_start /* t0 <- rel __bss_start in FLASH */ - add t0, t0, t6 /* t0 <- rel __bss_start in RAM */ - la t1, __bss_end /* t1 <- rel __bss_end in FLASH */ - add t1, t1, t6 /* t1 <- rel __bss_end in RAM */ - li t2, 0x00000000 /* clear */ - beq t0, t1, call_board_init_r - -clbss_l: - SREG t2, 0(t0) /* clear loop... */ - addi t0, t0, REGBYTES - bne t0, t1, clbss_l - -/* - * We are done. Do not return, instead branch to second part of board - * initialization, now running from RAM. - */ -call_board_init_r: - la t0, board_init_r - mv t4, t0 /* offset of board_init_r() */ - add t4, t4, t6 /* real address of board_init_r() */ -/* - * setup parameters for board_init_r - */ - mv a0, s3 /* gd_t */ - mv a1, s4 /* dest_addr */ - -/* - * jump to it ... - */ - jr t4 /* jump to board_init_r() */ - -/* - * trap entry - */ -trap_entry: - addi sp, sp, -32*REGBYTES - SREG x1, 1*REGBYTES(sp) - SREG x2, 2*REGBYTES(sp) - SREG x3, 3*REGBYTES(sp) - SREG x4, 4*REGBYTES(sp) - SREG x5, 5*REGBYTES(sp) - SREG x6, 6*REGBYTES(sp) - SREG x7, 7*REGBYTES(sp) - SREG x8, 8*REGBYTES(sp) - SREG x9, 9*REGBYTES(sp) - SREG x10, 10*REGBYTES(sp) - SREG x11, 11*REGBYTES(sp) - SREG x12, 12*REGBYTES(sp) - SREG x13, 13*REGBYTES(sp) - SREG x14, 14*REGBYTES(sp) - SREG x15, 15*REGBYTES(sp) - SREG x16, 16*REGBYTES(sp) - SREG x17, 17*REGBYTES(sp) - SREG x18, 18*REGBYTES(sp) - SREG x19, 19*REGBYTES(sp) - SREG x20, 20*REGBYTES(sp) - SREG x21, 21*REGBYTES(sp) - SREG x22, 22*REGBYTES(sp) - SREG x23, 23*REGBYTES(sp) - SREG x24, 24*REGBYTES(sp) - SREG x25, 25*REGBYTES(sp) - SREG x26, 26*REGBYTES(sp) - SREG x27, 27*REGBYTES(sp) - SREG x28, 28*REGBYTES(sp) - SREG x29, 29*REGBYTES(sp) - SREG x30, 30*REGBYTES(sp) - SREG x31, 31*REGBYTES(sp) - csrr a0, mcause - csrr a1, mepc - mv a2, sp - jal handle_trap - csrw mepc, a0 - -/* - * Remain in M-mode after mret - */ - li t0, MSTATUS_MPP - csrs mstatus, t0 - LREG x1, 1*REGBYTES(sp) - LREG x2, 2*REGBYTES(sp) - LREG x3, 3*REGBYTES(sp) - LREG x4, 4*REGBYTES(sp) - LREG x5, 5*REGBYTES(sp) - LREG x6, 6*REGBYTES(sp) - LREG x7, 7*REGBYTES(sp) - LREG x8, 8*REGBYTES(sp) - LREG x9, 9*REGBYTES(sp) - LREG x10, 10*REGBYTES(sp) - LREG x11, 11*REGBYTES(sp) - LREG x12, 12*REGBYTES(sp) - LREG x13, 13*REGBYTES(sp) - LREG x14, 14*REGBYTES(sp) - LREG x15, 15*REGBYTES(sp) - LREG x16, 16*REGBYTES(sp) - LREG x17, 17*REGBYTES(sp) - LREG x18, 18*REGBYTES(sp) - LREG x19, 19*REGBYTES(sp) - LREG x20, 20*REGBYTES(sp) - LREG x21, 21*REGBYTES(sp) - LREG x22, 22*REGBYTES(sp) - LREG x23, 23*REGBYTES(sp) - LREG x24, 24*REGBYTES(sp) - LREG x25, 25*REGBYTES(sp) - LREG x26, 26*REGBYTES(sp) - LREG x27, 27*REGBYTES(sp) - LREG x28, 28*REGBYTES(sp) - LREG x29, 29*REGBYTES(sp) - LREG x30, 30*REGBYTES(sp) - LREG x31, 31*REGBYTES(sp) - addi sp, sp, 32*REGBYTES - mret - -#ifdef CONFIG_INIT_CRITICAL -cpu_init_crit: - ret -#endif diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S new file mode 100644 index 0000000000..7cd7755190 --- /dev/null +++ b/arch/riscv/cpu/start.S @@ -0,0 +1,292 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Startup Code for RISC-V Core + * + * Copyright (c) 2017 Microsemi Corporation. + * Copyright (c) 2017 Padmarao Begari + * + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_32BIT +#define LREG lw +#define SREG sw +#define REGBYTES 4 +#define RELOC_TYPE R_RISCV_32 +#define SYM_INDEX 0x8 +#define SYM_SIZE 0x10 +#else +#define LREG ld +#define SREG sd +#define REGBYTES 8 +#define RELOC_TYPE R_RISCV_64 +#define SYM_INDEX 0x20 +#define SYM_SIZE 0x18 +#endif + +.section .text +.globl _start +_start: + j handle_reset + +nmi_vector: + j nmi_vector + +trap_vector: + j trap_entry + +.global trap_entry +handle_reset: + li t0, CONFIG_SYS_SDRAM_BASE + SREG a2, 0(t0) + la t0, trap_entry + csrw mtvec, t0 + csrwi mstatus, 0 + csrwi mie, 0 + +/* + * Do CPU critical regs init only at reboot, + * not when booting from ram + */ +#ifdef CONFIG_INIT_CRITICAL + jal cpu_init_crit /* Do CPU critical regs init */ +#endif + +/* + * Set stackpointer in internal/ex RAM to call board_init_f + */ +call_board_init_f: + li t0, -16 + li t1, CONFIG_SYS_INIT_SP_ADDR + and sp, t1, t0 /* force 16 byte alignment */ + +#ifdef CONFIG_DEBUG_UART + jal debug_uart_init +#endif + +call_board_init_f_0: + mv a0, sp + jal board_init_f_alloc_reserve + mv sp, a0 + jal board_init_f_init_reserve + + mv a0, zero /* a0 <-- boot_flags = 0 */ + la t5, board_init_f + jr t5 /* jump to board_init_f() */ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + */ +.globl relocate_code +relocate_code: + mv s2, a0 /* save addr_sp */ + mv s3, a1 /* save addr of gd */ + mv s4, a2 /* save addr of destination */ + +/* + *Set up the stack + */ +stack_setup: + mv sp, s2 + la t0, _start + sub t6, s4, t0 /* t6 <- relocation offset */ + beq t0, s4, clear_bss /* skip relocation */ + + mv t1, s4 /* t1 <- scratch for copy_loop */ + la t3, __bss_start + sub t3, t3, t0 /* t3 <- __bss_start_ofs */ + add t2, t0, t3 /* t2 <- source end address */ + +copy_loop: + LREG t5, 0(t0) + addi t0, t0, REGBYTES + SREG t5, 0(t1) + addi t1, t1, REGBYTES + blt t0, t2, copy_loop + +/* + * Update dynamic relocations after board_init_f + */ +fix_rela_dyn: + la t1, __rel_dyn_start + la t2, __rel_dyn_end + beq t1, t2, clear_bss + add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */ + add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */ + +/* + * skip first reserved entry: address, type, addend + */ + bne t1, t2, 7f + +6: + LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */ + li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */ + bne t5, t3, 8f /* skip non-RISCV_RELOC entries */ + LREG t3, -(REGBYTES*3)(t1) + LREG t5, -(REGBYTES)(t1) /* t5 <-- addend */ + add t5, t5, t6 /* t5 <-- location to fix up in RAM */ + add t3, t3, t6 /* t3 <-- location to fix up in RAM */ + SREG t5, 0(t3) +7: + addi t1, t1, (REGBYTES*3) + ble t1, t2, 6b + +8: + la t4, __dyn_sym_start + add t4, t4, t6 + +9: + LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */ + srli t0, t5, SYM_INDEX /* t0 <--- sym table index */ + andi t5, t5, 0xFF /* t5 <--- relocation type */ + li t3, RELOC_TYPE + bne t5, t3, 10f /* skip non-addned entries */ + + LREG t3, -(REGBYTES*3)(t1) + li t5, SYM_SIZE + mul t0, t0, t5 + add s1, t4, t0 + LREG t5, REGBYTES(s1) + add t5, t5, t6 /* t5 <-- location to fix up in RAM */ + add t3, t3, t6 /* t3 <-- location to fix up in RAM */ + SREG t5, 0(t3) +10: + addi t1, t1, (REGBYTES*3) + ble t1, t2, 9b + +/* + * trap update +*/ + la t0, trap_entry + add t0, t0, t6 + csrw mtvec, t0 + +clear_bss: + la t0, __bss_start /* t0 <- rel __bss_start in FLASH */ + add t0, t0, t6 /* t0 <- rel __bss_start in RAM */ + la t1, __bss_end /* t1 <- rel __bss_end in FLASH */ + add t1, t1, t6 /* t1 <- rel __bss_end in RAM */ + li t2, 0x00000000 /* clear */ + beq t0, t1, call_board_init_r + +clbss_l: + SREG t2, 0(t0) /* clear loop... */ + addi t0, t0, REGBYTES + bne t0, t1, clbss_l + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ +call_board_init_r: + la t0, board_init_r + mv t4, t0 /* offset of board_init_r() */ + add t4, t4, t6 /* real address of board_init_r() */ +/* + * setup parameters for board_init_r + */ + mv a0, s3 /* gd_t */ + mv a1, s4 /* dest_addr */ + +/* + * jump to it ... + */ + jr t4 /* jump to board_init_r() */ + +/* + * trap entry + */ +trap_entry: + addi sp, sp, -32*REGBYTES + SREG x1, 1*REGBYTES(sp) + SREG x2, 2*REGBYTES(sp) + SREG x3, 3*REGBYTES(sp) + SREG x4, 4*REGBYTES(sp) + SREG x5, 5*REGBYTES(sp) + SREG x6, 6*REGBYTES(sp) + SREG x7, 7*REGBYTES(sp) + SREG x8, 8*REGBYTES(sp) + SREG x9, 9*REGBYTES(sp) + SREG x10, 10*REGBYTES(sp) + SREG x11, 11*REGBYTES(sp) + SREG x12, 12*REGBYTES(sp) + SREG x13, 13*REGBYTES(sp) + SREG x14, 14*REGBYTES(sp) + SREG x15, 15*REGBYTES(sp) + SREG x16, 16*REGBYTES(sp) + SREG x17, 17*REGBYTES(sp) + SREG x18, 18*REGBYTES(sp) + SREG x19, 19*REGBYTES(sp) + SREG x20, 20*REGBYTES(sp) + SREG x21, 21*REGBYTES(sp) + SREG x22, 22*REGBYTES(sp) + SREG x23, 23*REGBYTES(sp) + SREG x24, 24*REGBYTES(sp) + SREG x25, 25*REGBYTES(sp) + SREG x26, 26*REGBYTES(sp) + SREG x27, 27*REGBYTES(sp) + SREG x28, 28*REGBYTES(sp) + SREG x29, 29*REGBYTES(sp) + SREG x30, 30*REGBYTES(sp) + SREG x31, 31*REGBYTES(sp) + csrr a0, mcause + csrr a1, mepc + mv a2, sp + jal handle_trap + csrw mepc, a0 + +/* + * Remain in M-mode after mret + */ + li t0, MSTATUS_MPP + csrs mstatus, t0 + LREG x1, 1*REGBYTES(sp) + LREG x2, 2*REGBYTES(sp) + LREG x3, 3*REGBYTES(sp) + LREG x4, 4*REGBYTES(sp) + LREG x5, 5*REGBYTES(sp) + LREG x6, 6*REGBYTES(sp) + LREG x7, 7*REGBYTES(sp) + LREG x8, 8*REGBYTES(sp) + LREG x9, 9*REGBYTES(sp) + LREG x10, 10*REGBYTES(sp) + LREG x11, 11*REGBYTES(sp) + LREG x12, 12*REGBYTES(sp) + LREG x13, 13*REGBYTES(sp) + LREG x14, 14*REGBYTES(sp) + LREG x15, 15*REGBYTES(sp) + LREG x16, 16*REGBYTES(sp) + LREG x17, 17*REGBYTES(sp) + LREG x18, 18*REGBYTES(sp) + LREG x19, 19*REGBYTES(sp) + LREG x20, 20*REGBYTES(sp) + LREG x21, 21*REGBYTES(sp) + LREG x22, 22*REGBYTES(sp) + LREG x23, 23*REGBYTES(sp) + LREG x24, 24*REGBYTES(sp) + LREG x25, 25*REGBYTES(sp) + LREG x26, 26*REGBYTES(sp) + LREG x27, 27*REGBYTES(sp) + LREG x28, 28*REGBYTES(sp) + LREG x29, 29*REGBYTES(sp) + LREG x30, 30*REGBYTES(sp) + LREG x31, 31*REGBYTES(sp) + addi sp, sp, 32*REGBYTES + mret + +#ifdef CONFIG_INIT_CRITICAL +cpu_init_crit: + ret +#endif diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds index f414473e54..11bc4a738b 100644 --- a/arch/riscv/cpu/u-boot.lds +++ b/arch/riscv/cpu/u-boot.lds @@ -11,7 +11,7 @@ SECTIONS { . = ALIGN(4); .text : { - arch/riscv/cpu/ax25/start.o (.text) + arch/riscv/cpu/start.o (.text) } /* This needs to come before *(.text*) */ -- cgit From 4694c93fef4606ab1d6b604b84c156445f2c7a07 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 26 Sep 2018 06:55:18 -0700 Subject: riscv: ae350: Clean up mixed tabs and spaces in the dts There are quite a lot of mixed tabs and spaces in the ae350.dts. Clean them up. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- arch/riscv/dts/ae350.dts | 177 ++++++++++++++++++++++++----------------------- 1 file changed, 90 insertions(+), 87 deletions(-) (limited to 'arch/riscv') diff --git a/arch/riscv/dts/ae350.dts b/arch/riscv/dts/ae350.dts index 2927e4151b..4717ae88bc 100644 --- a/arch/riscv/dts/ae350.dts +++ b/arch/riscv/dts/ae350.dts @@ -1,144 +1,147 @@ /dts-v1/; / { - #address-cells = <2>; - #size-cells = <2>; - compatible = "andestech,ax25"; - model = "andestech,ax25"; + #address-cells = <2>; + #size-cells = <2>; + compatible = "andestech,ax25"; + model = "andestech,ax25"; aliases { uart0 = &serial0; spi0 = &spi; - } ; + }; chosen { bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7"; stdout-path = "uart0:38400n8"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - timebase-frequency = <10000000>; - CPU0: cpu@0 { - device_type = "cpu"; - reg = <0>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdc"; - mmu-type = "riscv,sv39"; - clock-frequency = <60000000>; - CPU0_intc: interrupt-controller { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - }; - }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <10000000>; + + CPU0: cpu@0 { + device_type = "cpu"; + reg = <0>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + clock-frequency = <60000000>; + + CPU0_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; }; memory@0 { device_type = "memory"; - reg = <0x0 0x00000000 0x0 0x40000000>; + reg = <0x0 0x00000000 0x0 0x40000000>; }; - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "andestech,riscv-ae350-soc"; - ranges; + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "andestech,riscv-ae350-soc"; + ranges; }; - plmt0@e6000000 { - compatible = "riscv,plmt0"; - interrupts-extended = <&CPU0_intc 7>; - reg = <0x0 0xe6000000 0x0 0x100000>; - }; + plmt0@e6000000 { + compatible = "riscv,plmt0"; + interrupts-extended = <&CPU0_intc 7>; + reg = <0x0 0xe6000000 0x0 0x100000>; + }; - plic0: interrupt-controller@e4000000 { - compatible = "riscv,plic0"; - #address-cells = <2>; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0x0 0xe4000000 0x0 0x2000000>; - riscv,ndev=<31>; - interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>; + plic0: interrupt-controller@e4000000 { + compatible = "riscv,plic0"; + #address-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0x0 0xe4000000 0x0 0x2000000>; + riscv,ndev=<31>; + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>; }; - plic1: interrupt-controller@e6400000 { - compatible = "riscv,plic1"; - #address-cells = <2>; - #interrupt-cells = <2>; + plic1: interrupt-controller@e6400000 { + compatible = "riscv,plic1"; + #address-cells = <2>; + #interrupt-cells = <2>; interrupt-controller; - reg = <0x0 0xe6400000 0x0 0x400000>; - riscv,ndev=<1>; - interrupts-extended = <&CPU0_intc 3>; - }; + reg = <0x0 0xe6400000 0x0 0x400000>; + riscv,ndev=<1>; + interrupts-extended = <&CPU0_intc 3>; + }; - spiclk: virt_100mhz { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; + spiclk: virt_100mhz { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; - timer0: timer@f0400000 { - compatible = "andestech,atcpit100"; - reg = <0x0 0xf0400000 0x0 0x1000>; - clock-frequency = <40000000>; - interrupts = <3 4>; - interrupt-parent = <&plic0>; + timer0: timer@f0400000 { + compatible = "andestech,atcpit100"; + reg = <0x0 0xf0400000 0x0 0x1000>; + clock-frequency = <40000000>; + interrupts = <3 4>; + interrupt-parent = <&plic0>; }; serial0: serial@f0300000 { compatible = "andestech,uart16550", "ns16550a"; - reg = <0x0 0xf0300000 0x0 0x1000>; - interrupts = <9 4>; + reg = <0x0 0xf0300000 0x0 0x1000>; + interrupts = <9 4>; clock-frequency = <19660800>; reg-shift = <2>; reg-offset = <32>; no-loopback-test = <1>; - interrupt-parent = <&plic0>; + interrupt-parent = <&plic0>; }; mac0: mac@e0100000 { compatible = "andestech,atmac100"; - reg = <0x0 0xe0100000 0x0 0x1000>; - interrupts = <19 4>; - interrupt-parent = <&plic0>; + reg = <0x0 0xe0100000 0x0 0x1000>; + interrupts = <19 4>; + interrupt-parent = <&plic0>; }; mmc0: mmc@f0e00000 { - compatible = "andestech,atfsdc010"; + compatible = "andestech,atfsdc010"; max-frequency = <100000000>; - clock-freq-min-max = <400000 100000000>; + clock-freq-min-max = <400000 100000000>; fifo-depth = <0x10>; - reg = <0x0 0xf0e00000 0x0 0x1000>; - interrupts = <18 4>; + reg = <0x0 0xf0e00000 0x0 0x1000>; + interrupts = <18 4>; cap-sd-highspeed; - interrupt-parent = <&plic0>; + interrupt-parent = <&plic0>; }; - smc0: smc@e0400000 { - compatible = "andestech,atfsmc020"; - reg = <0x0 0xe0400000 0x0 0x1000>; - }; + smc0: smc@e0400000 { + compatible = "andestech,atfsmc020"; + reg = <0x0 0xe0400000 0x0 0x1000>; + }; - nor@0,0 { - compatible = "cfi-flash"; - reg = <0x0 0x88000000 0x0 0x1000>; - bank-width = <2>; - device-width = <1>; - }; + nor@0,0 { + compatible = "cfi-flash"; + reg = <0x0 0x88000000 0x0 0x1000>; + bank-width = <2>; + device-width = <1>; + }; spi: spi@f0b00000 { compatible = "andestech,atcspi200"; - reg = <0x0 0xf0b00000 0x0 0x1000>; + reg = <0x0 0xf0b00000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; num-cs = <1>; clocks = <&spiclk>; interrupts = <3 4>; - interrupt-parent = <&plic0>; - flash@0 { + interrupt-parent = <&plic0>; + + flash@0 { compatible = "spi-flash"; spi-max-frequency = <50000000>; reg = <0>; -- cgit From 510e379c49ba8e0d90960d8cbc2ffb91091e229a Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 26 Sep 2018 06:55:21 -0700 Subject: riscv: Add QEMU virt board support This adds QEMU RISC-V 'virt' board target support, with the hope of helping people easily test U-Boot on RISC-V. The QEMU virt machine models a generic RISC-V virtual machine with support for the VirtIO standard networking and block storage devices. It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and it also uses device-tree to pass configuration information to guest software. It implements RISC-V privileged architecture spec v1.10. Both 32-bit and 64-bit builds are supported. Support is pretty much preliminary, only booting to U-Boot shell with the UART driver on a single core. Booting Linux is not supported yet. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- arch/riscv/Kconfig | 4 ++++ arch/riscv/cpu/qemu/Makefile | 6 ++++++ arch/riscv/cpu/qemu/cpu.c | 29 +++++++++++++++++++++++++++++ arch/riscv/cpu/qemu/dram.c | 17 +++++++++++++++++ 4 files changed, 56 insertions(+) create mode 100644 arch/riscv/cpu/qemu/Makefile create mode 100644 arch/riscv/cpu/qemu/cpu.c create mode 100644 arch/riscv/cpu/qemu/dram.c (limited to 'arch/riscv') diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 49f87de1dc..168ca3de7c 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -11,9 +11,13 @@ choice config TARGET_AX25_AE350 bool "Support ax25-ae350" +config TARGET_QEMU_VIRT + bool "Support QEMU Virt Board" + endchoice source "board/AndesTech/ax25-ae350/Kconfig" +source "board/emulation/qemu-riscv/Kconfig" choice prompt "CPU selection" diff --git a/arch/riscv/cpu/qemu/Makefile b/arch/riscv/cpu/qemu/Makefile new file mode 100644 index 0000000000..258e4620dd --- /dev/null +++ b/arch/riscv/cpu/qemu/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, Bin Meng + +obj-y += dram.o +obj-y += cpu.o diff --git a/arch/riscv/cpu/qemu/cpu.c b/arch/riscv/cpu/qemu/cpu.c new file mode 100644 index 0000000000..a064639373 --- /dev/null +++ b/arch/riscv/cpu/qemu/cpu.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + */ + +#include +#include + +/* + * cleanup_before_linux() is called just before we call linux + * it prepares the processor for linux + * + * we disable interrupt and caches. + */ +int cleanup_before_linux(void) +{ + disable_interrupts(); + + /* turn off I/D-cache */ + + return 0; +} + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + printf("reset unsupported yet\n"); + + return 0; +} diff --git a/arch/riscv/cpu/qemu/dram.c b/arch/riscv/cpu/qemu/dram.c new file mode 100644 index 0000000000..84d87d2a7f --- /dev/null +++ b/arch/riscv/cpu/qemu/dram.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + */ + +#include +#include + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} -- cgit From b984ddc2dd332117ef1345255a99dc248c826b74 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 26 Sep 2018 06:55:22 -0700 Subject: riscv: Move do_reset() to a common place We don't have a reset method on any RISC-V board yet. Instead of adding the same 'unsupported' message for each CPU variant it might make more sense to add a generic do_reset function for all CPU variants to lib/, similar to the one for ARM (arch/arm/lib/reset.c). Suggested-by: Lukas Auer Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- arch/riscv/cpu/ax25/cpu.c | 9 --------- arch/riscv/cpu/qemu/cpu.c | 8 -------- arch/riscv/lib/Makefile | 1 + arch/riscv/lib/reset.c | 17 +++++++++++++++++ 4 files changed, 18 insertions(+), 17 deletions(-) create mode 100644 arch/riscv/lib/reset.c (limited to 'arch/riscv') diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c index ab05b57d4f..fddcc156c3 100644 --- a/arch/riscv/cpu/ax25/cpu.c +++ b/arch/riscv/cpu/ax25/cpu.c @@ -6,9 +6,6 @@ /* CPU specific code */ #include -#include -#include -#include /* * cleanup_before_linux() is called just before we call linux @@ -24,9 +21,3 @@ int cleanup_before_linux(void) return 0; } - -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - disable_interrupts(); - panic("ax25-ae350 wdt not support yet.\n"); -} diff --git a/arch/riscv/cpu/qemu/cpu.c b/arch/riscv/cpu/qemu/cpu.c index a064639373..6c7a32755a 100644 --- a/arch/riscv/cpu/qemu/cpu.c +++ b/arch/riscv/cpu/qemu/cpu.c @@ -4,7 +4,6 @@ */ #include -#include /* * cleanup_before_linux() is called just before we call linux @@ -20,10 +19,3 @@ int cleanup_before_linux(void) return 0; } - -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - printf("reset unsupported yet\n"); - - return 0; -} diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index cc562f935a..b58db89752 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o obj-y += interrupts.o +obj-y += reset.o obj-y += setjmp.o # For building EFI apps diff --git a/arch/riscv/lib/reset.c b/arch/riscv/lib/reset.c new file mode 100644 index 0000000000..a6aa8e2594 --- /dev/null +++ b/arch/riscv/lib/reset.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + */ + +#include +#include + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + printf("resetting ...\n"); + + printf("reset unsupported yet\n"); + hang(); + + return 0; +} -- cgit From 9d9b3dc0d52b7dcfdb79d5a849fc7f1b68dd5700 Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Wed, 3 Oct 2018 13:59:03 +0800 Subject: riscv: cosmetic: Reword do_reset() printf message. The Sentence "reset unsupported yet" is not grammatically correct and should say "reset not supported yet" instead. Suggested-by: Lukas Auer Signed-off-by: Rick Chen --- arch/riscv/lib/reset.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/riscv') diff --git a/arch/riscv/lib/reset.c b/arch/riscv/lib/reset.c index a6aa8e2594..b8cecb309d 100644 --- a/arch/riscv/lib/reset.c +++ b/arch/riscv/lib/reset.c @@ -10,7 +10,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { printf("resetting ...\n"); - printf("reset unsupported yet\n"); + printf("reset not supported yet\n"); hang(); return 0; -- cgit From 5845f6612372a63877b2175e058a841e1237ffd6 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 6 Aug 2018 19:15:38 +0200 Subject: riscv: allow native compilation If environment variable CROSS_COMPILE is not set, this indicates native compilation. In this case we should not set an arbitrary value which is not applicable for 64bit anyway. Signed-off-by: Heinrich Schuchardt --- arch/riscv/config.mk | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/riscv') diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk index b235ae1413..ed9eb0c24c 100644 --- a/arch/riscv/config.mk +++ b/arch/riscv/config.mk @@ -10,10 +10,6 @@ # Rick Chen, Andes Technology Corporation # -ifeq ($(CROSS_COMPILE),) -CROSS_COMPILE := riscv32-unknown-linux-gnu- -endif - 32bit-emul := elf32lriscv 64bit-emul := elf64lriscv -- cgit