From 9baeca4b8936edc01e1c748a6f119915acb100c4 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 14 Nov 2014 18:18:40 -0700 Subject: x86: ivybridge: Set up EHCI USB Add init for EHCI so that USB can be used. Signed-off-by: Simon Glass --- arch/x86/cpu/ivybridge/Makefile | 1 + arch/x86/cpu/ivybridge/bd82x6x.c | 2 ++ arch/x86/cpu/ivybridge/usb_ehci.c | 29 +++++++++++++++++++++++++++++ 3 files changed, 32 insertions(+) create mode 100644 arch/x86/cpu/ivybridge/usb_ehci.c (limited to 'arch/x86/cpu/ivybridge') diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index c6342cd99d..4a00757ec2 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -17,3 +17,4 @@ obj-y += pci.o obj-y += report_platform.o obj-y += sata.o obj-y += sdram.o +obj-y += usb_ehci.o diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index b54f5c7882..1fcbc28543 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -102,6 +102,8 @@ int bd82x6x_init_pci_devices(void) return -EINVAL; } bd82x6x_sata_init(PCH_SATA_DEV, blob, sata_node); + bd82x6x_usb_ehci_init(PCH_EHCI1_DEV); + bd82x6x_usb_ehci_init(PCH_EHCI2_DEV); return 0; } diff --git a/arch/x86/cpu/ivybridge/usb_ehci.c b/arch/x86/cpu/ivybridge/usb_ehci.c new file mode 100644 index 0000000000..291c971a2f --- /dev/null +++ b/arch/x86/cpu/ivybridge/usb_ehci.c @@ -0,0 +1,29 @@ +/* + * From Coreboot + * Copyright (C) 2008-2009 coresystems GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include + +void bd82x6x_usb_ehci_init(pci_dev_t dev) +{ + u32 reg32; + + /* Disable Wake on Disconnect in RMH */ + reg32 = readl(RCB_REG(0x35b0)); + reg32 |= 0x22; + writel(reg32, RCB_REG(0x35b0)); + + debug("EHCI: Setting up controller.. "); + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER; + /* reg32 |= PCI_COMMAND_SERR; */ + pci_write_config32(dev, PCI_COMMAND, reg32); + + debug("done.\n"); +} -- cgit