From 0990c894cc2e8e94a2b049e4c83d484d0b3afd9c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 9 Jul 2020 18:43:17 -0600 Subject: x86: fsp: Support a warning message when DRAM init is slow With DDR4, Intel SOCs take quite a long time to init their memory. During this time, if the user is watching, it looks like SPL has hung. Add a message in this case. This works by adding a return code to fspm_update_config() that indicates whether MRC data was found and a new property to the device tree. Also add one more debug message while starting. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Reviewed-by: Wolfgang Wallner Tested-by: Wolfgang Wallner --- arch/x86/dts/chromebook_coral.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/x86/dts/chromebook_coral.dts') diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index 965d9f387d..a17a9c2800 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -117,6 +117,7 @@ reg = <0x00000000 0 0 0 0>; compatible = "intel,apl-hostbridge"; pciex-region-size = <0x10000000>; + fspm,training-delay = <21>; /* * Parameters used by the FSP-S binary blob. This is * really unfortunate since these parameters mostly -- cgit