From f2b85ab5e6a91e29c1d64304be371753d75ed172 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 18 Jan 2016 20:19:21 -0700 Subject: dm: x86: spi: Convert ICH SPI driver to driver model PCI API At present this SPI driver works by searching the PCI buses for its peripheral. It also uses the legacy PCI API. In addition the driver has code to determine the type of Intel PCH that is used (version 7 or version 9). Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has a node for the SPI peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the LPC device. Update the device tree files to show the SPI controller within the PCH, so that PCI access works as expected. This patch includes Bin's fix-up patch from here: https://patchwork.ozlabs.org/patch/569478/ Signed-off-by: Simon Glass Signed-off-by: Bin Meng Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/x86/dts/chromebook_link.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/x86/dts/chromebook_link.dts') diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index c4469a9768..a5c5dc126c 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -186,9 +186,9 @@ intel,pch-backlight = <0x04000000>; }; - pch { + pch@1f,0 { reg = <0x0000f800 0 0 0 0>; - compatible = "intel,bd82x6x", "intel,pch"; + compatible = "intel,bd82x6x", "intel,pch9"; u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; @@ -200,6 +200,7 @@ 1 0 0 0 0 0 0 0>; /* Enable EC SMI source */ intel,alt-gp-smi-enable = <0x0100>; + spi { #address-cells = <1>; #size-cells = <0>; -- cgit