From 5bf0f7f65d40447cec0f3d91abda59eb4a4f88af Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 9 Sep 2015 23:20:28 -0700 Subject: x86: galileo: Add PCIe root port IRQ routing Now we have enabled PCIe root port on Quark SoC, add its PIRQ routing information in the device tree as well. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/dts/galileo.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/x86/dts/galileo.dts') diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts index f119bf7f42..a4e16760d5 100644 --- a/arch/x86/dts/galileo.dts +++ b/arch/x86/dts/galileo.dts @@ -92,6 +92,18 @@ PCI_BDF(0, 21, 0) INTA PIRQE PCI_BDF(0, 21, 1) INTB PIRQF PCI_BDF(0, 21, 2) INTC PIRQG + PCI_BDF(0, 23, 0) INTA PIRQA + PCI_BDF(0, 23, 1) INTB PIRQB + + /* PCIe root ports downstream interrupts */ + PCI_BDF(1, 0, 0) INTA PIRQA + PCI_BDF(1, 0, 0) INTB PIRQB + PCI_BDF(1, 0, 0) INTC PIRQC + PCI_BDF(1, 0, 0) INTD PIRQD + PCI_BDF(2, 0, 0) INTA PIRQB + PCI_BDF(2, 0, 0) INTB PIRQC + PCI_BDF(2, 0, 0) INTC PIRQD + PCI_BDF(2, 0, 0) INTD PIRQA >; }; }; -- cgit