From 2047390abc04b921764bd23eeffc0d3e83a2a674 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 17 Jun 2016 02:13:14 -0700 Subject: x86: baytrail: Introduce ACPI global NVS This introduces baytrail-specific ACPI global NVS structure, defined in both C header file and ASL file. Signed-off-by: Bin Meng Reviewed-by: George McCollister Tested-by: George McCollister Reviewed-by: Simon Glass --- .../include/asm/arch-baytrail/acpi/global_nvs.asl | 15 +++++++++++++++ arch/x86/include/asm/arch-baytrail/global_nvs.h | 21 +++++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl create mode 100644 arch/x86/include/asm/arch-baytrail/global_nvs.h (limited to 'arch/x86/include/asm/arch-baytrail') diff --git a/arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl b/arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl new file mode 100644 index 0000000000..a28d4dfade --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2016 Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE) +Field(GNVS, ByteAcc, NoLock, Preserve) +{ + Offset (0x00), + PCNT, 8, /* processor count */ + IURE, 8, /* internal UART enabled */ +} diff --git a/arch/x86/include/asm/arch-baytrail/global_nvs.h b/arch/x86/include/asm/arch-baytrail/global_nvs.h new file mode 100644 index 0000000000..56e362633f --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/global_nvs.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2016, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _GLOBAL_NVS_H_ +#define _GLOBAL_NVS_H_ + +struct __packed acpi_global_nvs { + u8 pcnt; /* processor count */ + u8 iuart_en; /* internal UART enabled */ + + /* + * Add padding so sizeof(struct acpi_global_nvs) == 0x100. + * This must match the size defined in the global_nvs.asl. + */ + u8 rsvd[254]; +}; + +#endif /* _GLOBAL_NVS_H_ */ -- cgit From 79c2c257cf66da5ac90b5c53954310361e41bb0a Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 17 Jun 2016 02:13:16 -0700 Subject: x86: acpi: Pack global NVS into ACPI table Now that platform-specific ACPI global NVS is added, pack it into ACPI table and get its address fixed up. Signed-off-by: Bin Meng Reviewed-by: George McCollister Tested-by: George McCollister Reviewed-by: Simon Glass --- arch/x86/include/asm/arch-baytrail/acpi/platform.asl | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/x86/include/asm/arch-baytrail') diff --git a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl index 6bc82ecfe1..a80d2c0e51 100644 --- a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl +++ b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl @@ -22,6 +22,9 @@ Method(_WAK, 1) Return (Package() {0, 0}) } +/* ACPI global NVS */ +#include "global_nvs.asl" + /* TODO: add CPU ASL support */ Scope (\_SB) -- cgit From 3ff11aaa507aa222e76aa2517efc9786494994ed Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 17 Jun 2016 02:13:17 -0700 Subject: x86: baytrail: acpi: Hide internal UART per GNVS setting If global NVS says internal UART is not enabled, hide it in the ASL code so that OS won't see it. Signed-off-by: Bin Meng Reviewed-by: George McCollister Tested-by: George McCollister Reviewed-by: Simon Glass --- arch/x86/include/asm/arch-baytrail/acpi/lpc.asl | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) (limited to 'arch/x86/include/asm/arch-baytrail') diff --git a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl index 22f0d68f4d..fe34d3271c 100644 --- a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl +++ b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl @@ -119,17 +119,14 @@ Device (LPCB) Method(_STA, 0, Serialized) { - /* - * TODO: - * - * Need to hide the internal UART depending on whether - * internal UART is enabled or not so that external - * SuperIO UART can be exposed to system. - */ - Store(1, UI3E) - Store(1, UI4E) - Store(1, C1EN) - Return (STA_VISIBLE) + If (LEqual(IURE, 1)) { + Store(1, UI3E) + Store(1, UI4E) + Store(1, C1EN) + Return (STA_VISIBLE) + } Else { + Return (STA_MISSING) + } } -- cgit