From 83311886151f80ef24d30f850baece07d08863cb Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:00:11 -0600 Subject: x86: Rename existing FSP code to fsp1 Since there is now a new version of the FSP and it is incompatible with the existing version, move the code into an fsp1 directory. This will allow us to put FSP v2 code into an fsp2 directory. Add a Kconfig which defines which version is in use. Some of the code in this new fsp1/ directory is generic across both FSPv1 and FSPv2. Future patches will address this. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/x86/Kconfig | 25 +- arch/x86/cpu/baytrail/acpi.c | 2 +- arch/x86/cpu/baytrail/fsp_configs.c | 2 +- arch/x86/cpu/braswell/fsp_configs.c | 2 +- arch/x86/cpu/ivybridge/fsp_configs.c | 2 +- arch/x86/cpu/queensbay/fsp_configs.c | 2 +- arch/x86/cpu/queensbay/tnc.c | 2 +- arch/x86/include/asm/fsp/fsp_api.h | 67 ------ arch/x86/include/asm/fsp/fsp_azalia.h | 38 --- arch/x86/include/asm/fsp/fsp_bootmode.h | 23 -- arch/x86/include/asm/fsp/fsp_ffs.h | 153 ------------ arch/x86/include/asm/fsp/fsp_fv.h | 136 ----------- arch/x86/include/asm/fsp/fsp_hob.h | 98 -------- arch/x86/include/asm/fsp/fsp_infoheader.h | 38 --- arch/x86/include/asm/fsp/fsp_support.h | 188 --------------- arch/x86/include/asm/fsp/fsp_types.h | 62 ----- arch/x86/include/asm/fsp1/fsp_api.h | 67 ++++++ arch/x86/include/asm/fsp1/fsp_azalia.h | 38 +++ arch/x86/include/asm/fsp1/fsp_bootmode.h | 23 ++ arch/x86/include/asm/fsp1/fsp_ffs.h | 153 ++++++++++++ arch/x86/include/asm/fsp1/fsp_fv.h | 136 +++++++++++ arch/x86/include/asm/fsp1/fsp_hob.h | 98 ++++++++ arch/x86/include/asm/fsp1/fsp_infoheader.h | 38 +++ arch/x86/include/asm/fsp1/fsp_support.h | 188 +++++++++++++++ arch/x86/include/asm/fsp1/fsp_types.h | 62 +++++ arch/x86/include/asm/u-boot-x86.h | 2 +- arch/x86/lib/Makefile | 3 +- arch/x86/lib/fsp/Makefile | 9 - arch/x86/lib/fsp/fsp_car.S | 111 --------- arch/x86/lib/fsp/fsp_common.c | 165 ------------- arch/x86/lib/fsp/fsp_dram.c | 108 --------- arch/x86/lib/fsp/fsp_graphics.c | 127 ---------- arch/x86/lib/fsp/fsp_support.c | 366 ----------------------------- arch/x86/lib/fsp1/Makefile | 9 + arch/x86/lib/fsp1/fsp_car.S | 111 +++++++++ arch/x86/lib/fsp1/fsp_common.c | 165 +++++++++++++ arch/x86/lib/fsp1/fsp_dram.c | 108 +++++++++ arch/x86/lib/fsp1/fsp_graphics.c | 127 ++++++++++ arch/x86/lib/fsp1/fsp_support.c | 366 +++++++++++++++++++++++++++++ 39 files changed, 1722 insertions(+), 1698 deletions(-) delete mode 100644 arch/x86/include/asm/fsp/fsp_api.h delete mode 100644 arch/x86/include/asm/fsp/fsp_azalia.h delete mode 100644 arch/x86/include/asm/fsp/fsp_bootmode.h delete mode 100644 arch/x86/include/asm/fsp/fsp_ffs.h delete mode 100644 arch/x86/include/asm/fsp/fsp_fv.h delete mode 100644 arch/x86/include/asm/fsp/fsp_hob.h delete mode 100644 arch/x86/include/asm/fsp/fsp_infoheader.h delete mode 100644 arch/x86/include/asm/fsp/fsp_support.h delete mode 100644 arch/x86/include/asm/fsp/fsp_types.h create mode 100644 arch/x86/include/asm/fsp1/fsp_api.h create mode 100644 arch/x86/include/asm/fsp1/fsp_azalia.h create mode 100644 arch/x86/include/asm/fsp1/fsp_bootmode.h create mode 100644 arch/x86/include/asm/fsp1/fsp_ffs.h create mode 100644 arch/x86/include/asm/fsp1/fsp_fv.h create mode 100644 arch/x86/include/asm/fsp1/fsp_hob.h create mode 100644 arch/x86/include/asm/fsp1/fsp_infoheader.h create mode 100644 arch/x86/include/asm/fsp1/fsp_support.h create mode 100644 arch/x86/include/asm/fsp1/fsp_types.h delete mode 100644 arch/x86/lib/fsp/Makefile delete mode 100644 arch/x86/lib/fsp/fsp_car.S delete mode 100644 arch/x86/lib/fsp/fsp_common.c delete mode 100644 arch/x86/lib/fsp/fsp_dram.c delete mode 100644 arch/x86/lib/fsp/fsp_graphics.c delete mode 100644 arch/x86/lib/fsp/fsp_support.c create mode 100644 arch/x86/lib/fsp1/Makefile create mode 100644 arch/x86/lib/fsp1/fsp_car.S create mode 100644 arch/x86/lib/fsp1/fsp_common.c create mode 100644 arch/x86/lib/fsp1/fsp_dram.c create mode 100644 arch/x86/lib/fsp1/fsp_graphics.c create mode 100644 arch/x86/lib/fsp1/fsp_support.c (limited to 'arch/x86') diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 218e817cf3..314f8def7a 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -364,6 +364,29 @@ config HAVE_FSP Note: Without this binary U-Boot will not be able to set up its SDRAM so will not boot. +choice + prompt "FSP version" + depends on HAVE_FSP + default FSP_VERSION1 + help + Selects the FSP version to use. Intel has published several versions + of the FSP External Architecture Specification and this allows + selection of the version number used by a particular SoC. + +config FSP_VERSION1 + bool "FSP version 1.x" + help + This covers versions 1.0 and 1.1a. See here for details: + https://github.com/IntelFsp/fsp/wiki + +config FSP_VERSION2 + bool "FSP version 2.x" + help + This covers versions 2.0 and 2.1. See here for details: + https://github.com/IntelFsp/fsp/wiki + +endchoice + config FSP_FILE string "Firmware Support Package binary filename" depends on HAVE_FSP @@ -429,7 +452,7 @@ config ENABLE_MRC_CACHE For platforms that use Intel FSP for the memory initialization, please check FSP output HOB via U-Boot command 'fsp hob' to see - if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h). + if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp1/fsp_hob.h). If such GUID does not exist, MRC cache is not available on such platform (eg: Intel Queensbay), which means selecting this option here does not make any difference. diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c index 445e4ba2d7..1e3829a433 100644 --- a/arch/x86/cpu/baytrail/acpi.c +++ b/arch/x86/cpu/baytrail/acpi.c @@ -167,7 +167,7 @@ void acpi_create_gnvs(struct acpi_global_nvs *gnvs) * and PMC_BASE_ADDRESS are accessed, so we need make sure the base addresses * of these two blocks are programmed by either U-Boot or FSP. * - * It has been verified that 1st phase API (see arch/x86/lib/fsp/fsp_car.S) + * It has been verified that 1st phase API (see arch/x86/lib/fsp1/fsp_car.S) * on Intel BayTrail SoC already initializes these two base addresses so * we are safe to access these registers here. */ diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index cefd26299a..5b5d66aa5e 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -7,7 +7,7 @@ #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/cpu/braswell/fsp_configs.c b/arch/x86/cpu/braswell/fsp_configs.c index 7fe6fa7995..607e333f21 100644 --- a/arch/x86/cpu/braswell/fsp_configs.c +++ b/arch/x86/cpu/braswell/fsp_configs.c @@ -5,7 +5,7 @@ #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/cpu/ivybridge/fsp_configs.c b/arch/x86/cpu/ivybridge/fsp_configs.c index 2fd06b3bed..773c2b2a0a 100644 --- a/arch/x86/cpu/ivybridge/fsp_configs.c +++ b/arch/x86/cpu/ivybridge/fsp_configs.c @@ -5,7 +5,7 @@ #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/cpu/queensbay/fsp_configs.c b/arch/x86/cpu/queensbay/fsp_configs.c index c4d117783c..0dd1901e07 100644 --- a/arch/x86/cpu/queensbay/fsp_configs.c +++ b/arch/x86/cpu/queensbay/fsp_configs.c @@ -5,7 +5,7 @@ */ #include -#include +#include void update_fsp_configs(struct fsp_config_data *config, struct fspinit_rtbuf *rt_buf) diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index 76556fc7f7..66737e655b 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include static int __maybe_unused disable_igd(void) diff --git a/arch/x86/include/asm/fsp/fsp_api.h b/arch/x86/include/asm/fsp/fsp_api.h deleted file mode 100644 index f2d70799f3..0000000000 --- a/arch/x86/include/asm/fsp/fsp_api.h +++ /dev/null @@ -1,67 +0,0 @@ -/* SPDX-License-Identifier: Intel */ -/* - * Copyright (C) 2013, Intel Corporation - * Copyright (C) 2014, Bin Meng - */ - -#ifndef __FSP_API_H__ -#define __FSP_API_H__ - -#include - -/* - * FSP common configuration structure. - * This needs to be included in the platform-specific struct fsp_config_data. - */ -struct fsp_cfg_common { - struct fsp_header *fsp_hdr; - u32 stack_top; - u32 boot_mode; -}; - -/* - * FspInit continuation function prototype. - * Control will be returned to this callback function after FspInit API call. - */ -typedef void (*fsp_continuation_f)(u32 status, void *hob_list); - -struct fsp_init_params { - /* Non-volatile storage buffer pointer */ - void *nvs_buf; - /* Runtime buffer pointer */ - void *rt_buf; - /* Continuation function address */ - fsp_continuation_f continuation; -}; - -struct common_buf { - /* - * Stack top pointer used by the bootloader. The new stack frame will be - * set up at this location after FspInit API call. - */ - u32 stack_top; - u32 boot_mode; /* Current system boot mode */ - void *upd_data; /* User platform configuraiton data region */ - u32 tolum_size; /* Top of low usable memory size (FSP 1.1) */ - u32 reserved[6]; /* Reserved */ -}; - -enum fsp_phase { - /* Notification code for post PCI enuermation */ - INIT_PHASE_PCI = 0x20, - /* Notification code before transfering control to the payload */ - INIT_PHASE_BOOT = 0x40 -}; - -struct fsp_notify_params { - /* Notification phase used for NotifyPhase API */ - enum fsp_phase phase; -}; - -/* FspInit API function prototype */ -typedef asmlinkage u32 (*fsp_init_f)(struct fsp_init_params *params); - -/* FspNotify API function prototype */ -typedef asmlinkage u32 (*fsp_notify_f)(struct fsp_notify_params *params); - -#endif diff --git a/arch/x86/include/asm/fsp/fsp_azalia.h b/arch/x86/include/asm/fsp/fsp_azalia.h deleted file mode 100644 index e59180bdae..0000000000 --- a/arch/x86/include/asm/fsp/fsp_azalia.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: Intel */ -/* - * Copyright (C) 2013, Intel Corporation - * Copyright (C) 2015, Google, Inc - */ - -#ifndef _FSP_AZALIA_H_ -#define _FSP_AZALIA_H_ - -struct __packed azalia_verb_table_header { - u32 vendor_device_id; - u16 sub_system_id; - u8 revision_id; /* 0xff applies to all steppings */ - u8 front_panel_support; - u16 number_of_rear_jacks; - u16 number_of_front_jacks; -}; - -struct __packed azalia_verb_table { - struct azalia_verb_table_header header; - const u32 *data; -}; - -struct __packed azalia_config { - u8 pme_enable:1; - u8 docking_supported:1; - u8 docking_attached:1; - u8 hdmi_codec_enable:1; - u8 azalia_v_ci_enable:1; - u8 rsvdbits:3; - /* number of verb tables provided by platform */ - u8 verb_table_num; - const struct azalia_verb_table *verb_table; - /* delay timer after azalia reset */ - u16 reset_wait_timer_ms; -}; - -#endif diff --git a/arch/x86/include/asm/fsp/fsp_bootmode.h b/arch/x86/include/asm/fsp/fsp_bootmode.h deleted file mode 100644 index bc96ec308c..0000000000 --- a/arch/x86/include/asm/fsp/fsp_bootmode.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: Intel */ -/* - * Copyright (C) 2013, Intel Corporation - * Copyright (C) 2014, Bin Meng - */ - -#ifndef __FSP_BOOT_MODE_H__ -#define __FSP_BOOT_MODE_H__ - -/* 0x21 - 0xf..f are reserved */ -#define BOOT_FULL_CONFIG 0x00 -#define BOOT_MINIMAL_CONFIG 0x01 -#define BOOT_NO_CONFIG_CHANGES 0x02 -#define BOOT_FULL_CONFIG_PLUS_DIAG 0x03 -#define BOOT_DEFAULT_SETTINGS 0x04 -#define BOOT_ON_S4_RESUME 0x05 -#define BOOT_ON_S5_RESUME 0x06 -#define BOOT_ON_S2_RESUME 0x10 -#define BOOT_ON_S3_RESUME 0x11 -#define BOOT_ON_FLASH_UPDATE 0x12 -#define BOOT_IN_RECOVERY_MODE 0x20 - -#endif diff --git a/arch/x86/include/asm/fsp/fsp_ffs.h b/arch/x86/include/asm/fsp/fsp_ffs.h deleted file mode 100644 index b7558e5a17..0000000000 --- a/arch/x86/include/asm/fsp/fsp_ffs.h +++ /dev/null @@ -1,153 +0,0 @@ -/* SPDX-License-Identifier: Intel */ -/* - * Copyright (C) 2013, Intel Corporation - * Copyright (C) 2014, Bin Meng - */ - -#ifndef __FSP_FFS_H__ -#define __FSP_FFS_H__ - -/* Used to verify the integrity of the file */ -union __packed ffs_integrity { - struct { - /* - * The IntegrityCheck.checksum.header field is an 8-bit - * checksum of the file header. The State and - * IntegrityCheck.checksum.file fields are assumed to be zero - * and the checksum is calculated such that the entire header - * sums to zero. - */ - u8 header; - /* - * If the FFS_ATTRIB_CHECKSUM (see definition below) bit of - * the Attributes field is set to one, the - * IntegrityCheck.checksum.file field is an 8-bit checksum of - * the file data. If the FFS_ATTRIB_CHECKSUM bit of the - * Attributes field is cleared to zero, the - * IntegrityCheck.checksum.file field must be initialized with - * a value of 0xAA. The IntegrityCheck.checksum.file field is - * valid any time the EFI_FILE_DATA_VALID bit is set in the - * State field. - */ - u8 file; - } checksum; - - /* This is the full 16 bits of the IntegrityCheck field */ - u16 checksum16; -}; - -/* - * Each file begins with the header that describe the - * contents and state of the files. - */ -struct __packed ffs_file_header { - /* - * This GUID is the file name. - * It is used to uniquely identify the file. - */ - efi_guid_t name; - /* Used to verify the integrity of the file */ - union ffs_integrity integrity; - /* Identifies the type of file */ - u8 type; - /* Declares various file attribute bits */ - u8 attr; - /* The length of the file in bytes, including the FFS header */ - u8 size[3]; - /* - * Used to track the state of the file throughout the life of - * the file from creation to deletion. - */ - u8 state; -}; - -struct __packed ffs_file_header2 { - /* - * This GUID is the file name. It is used to uniquely identify the file. - * There may be only one instance of a file with the file name GUID of - * Name in any given firmware volume, except if the file type is - * EFI_FV_FILE_TYPE_FFS_PAD. - */ - efi_guid_t name; - /* Used to verify the integrity of the file */ - union ffs_integrity integrity; - /* Identifies the type of file */ - u8 type; - /* Declares various file attribute bits */ - u8 attr; - /* - * The length of the file in bytes, including the FFS header. - * The length of the file data is either - * (size - sizeof(struct ffs_file_header)). This calculation means a - * zero-length file has a size of 24 bytes, which is - * sizeof(struct ffs_file_header). Size is not required to be a - * multiple of 8 bytes. Given a file F, the next file header is located - * at the next 8-byte aligned firmware volume offset following the last - * byte of the file F. - */ - u8 size[3]; - /* - * Used to track the state of the file throughout the life of - * the file from creation to deletion. - */ - u8 state; - /* - * If FFS_ATTRIB_LARGE_FILE is set in attr, then ext_size exists - * and size must be set to zero. - * If FFS_ATTRIB_LARGE_FILE is not set then - * struct ffs_file_header is used. - */ - u32 ext_size; -}; - -/* - * Pseudo type. It is used as a wild card when retrieving sections. - * The section type EFI_SECTION_ALL matches all section types. - */ -#define EFI_SECTION_ALL 0x00 - -/* Encapsulation section Type values */ -#define EFI_SECTION_COMPRESSION 0x01 -#define EFI_SECTION_GUID_DEFINED 0x02 -#define EFI_SECTION_DISPOSABLE 0x03 - -/* Leaf section Type values */ -#define EFI_SECTION_PE32 0x10 -#define EFI_SECTION_PIC 0x11 -#define EFI_SECTION_TE 0x12 -#define EFI_SECTION_DXE_DEPEX 0x13 -#define EFI_SECTION_VERSION 0x14 -#define EFI_SECTION_USER_INTERFACE 0x15 -#define EFI_SECTION_COMPATIBILITY16 0x16 -#define EFI_SECTION_FIRMWARE_VOLUME_IMAGE 0x17 -#define EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18 -#define EFI_SECTION_RAW 0x19 -#define EFI_SECTION_PEI_DEPEX 0x1B -#define EFI_SECTION_SMM_DEPEX 0x1C - -/* Common section header */ -struct __packed raw_section { - /* - * A 24-bit unsigned integer that contains the total size of - * the section in bytes, including the EFI_COMMON_SECTION_HEADER. - */ - u8 size[3]; - u8 type; -}; - -struct __packed raw_section2 { - /* - * A 24-bit unsigned integer that contains the total size of - * the section in bytes, including the EFI_COMMON_SECTION_HEADER. - */ - u8 size[3]; - u8 type; - /* - * If size is 0xFFFFFF, then ext_size contains the size of - * the section. If size is not equal to 0xFFFFFF, then this - * field does not exist. - */ - u32 ext_size; -}; - -#endif diff --git a/arch/x86/include/asm/fsp/fsp_fv.h b/arch/x86/include/asm/fsp/fsp_fv.h deleted file mode 100644 index 511dfb78b8..0000000000 --- a/arch/x86/include/asm/fsp/fsp_fv.h +++ /dev/null @@ -1,136 +0,0 @@ -/* SPDX-License-Identifier: Intel */ -/* - * Copyright (C) 2013, Intel Corporation - * Copyright (C) 2014, Bin Meng - */ - -#ifndef __FSP_FV___ -#define __FSP_FV___ - -/* Value of EFI_FV_FILE_ATTRIBUTES */ -#define EFI_FV_FILE_ATTR_ALIGNMENT 0x0000001F -#define EFI_FV_FILE_ATTR_FIXED 0x00000100 -#define EFI_FV_FILE_ATTR_MEMORY_MAPPED 0x00000200 - -/* Attributes bit definitions */ -#define EFI_FVB2_READ_DISABLED_CAP 0x00000001 -#define EFI_FVB2_READ_ENABLED_CAP 0x00000002 -#define EFI_FVB2_READ_STATUS 0x00000004 -#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008 -#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010 -#define EFI_FVB2_WRITE_STATUS 0x00000020 -#define EFI_FVB2_LOCK_CAP 0x00000040 -#define EFI_FVB2_LOCK_STATUS 0x00000080 -#define EFI_FVB2_STICKY_WRITE 0x00000200 -#define EFI_FVB2_MEMORY_MAPPED 0x00000400 -#define EFI_FVB2_ERASE_POLARITY 0x00000800 -#define EFI_FVB2_READ_LOCK_CAP 0x00001000 -#define EFI_FVB2_READ_LOCK_STATUS 0x00002000 -#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000 -#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000 -#define EFI_FVB2_ALIGNMENT 0x001F0000 -#define EFI_FVB2_ALIGNMENT_1 0x00000000 -#define EFI_FVB2_ALIGNMENT_2 0x00010000 -#define EFI_FVB2_ALIGNMENT_4 0x00020000 -#define EFI_FVB2_ALIGNMENT_8 0x00030000 -#define EFI_FVB2_ALIGNMENT_16 0x00040000 -#define EFI_FVB2_ALIGNMENT_32 0x00050000 -#define EFI_FVB2_ALIGNMENT_64 0x00060000 -#define EFI_FVB2_ALIGNMENT_128 0x00070000 -#define EFI_FVB2_ALIGNMENT_256 0x00080000 -#define EFI_FVB2_ALIGNMENT_512 0x00090000 -#define EFI_FVB2_ALIGNMENT_1K 0x000A0000 -#define EFI_FVB2_ALIGNMENT_2K 0x000B0000 -#define EFI_FVB2_ALIGNMENT_4K 0x000C0000 -#define EFI_FVB2_ALIGNMENT_8K 0x000D0000 -#define EFI_FVB2_ALIGNMENT_16K 0x000E0000 -#define EFI_FVB2_ALIGNMENT_32K 0x000F0000 -#define EFI_FVB2_ALIGNMENT_64K 0x00100000 -#define EFI_FVB2_ALIGNMENT_128K 0x00110000 -#define EFI_FVB2_ALIGNMENT_256K 0x00120000 -#define EFI_FVB2_ALIGNMENT_512K 0x00130000 -#define EFI_FVB2_ALIGNMENT_1M 0x00140000 -#define EFI_FVB2_ALIGNMENT_2M 0x00150000 -#define EFI_FVB2_ALIGNMENT_4M 0x00160000 -#define EFI_FVB2_ALIGNMENT_8M 0x00170000 -#define EFI_FVB2_ALIGNMENT_16M 0x00180000 -#define EFI_FVB2_ALIGNMENT_32M 0x00190000 -#define EFI_FVB2_ALIGNMENT_64M 0x001A0000 -#define EFI_FVB2_ALIGNMENT_128M 0x001B0000 -#define EFI_FVB2_ALIGNMENT_256M 0x001C0000 -#define EFI_FVB2_ALIGNMENT_512M 0x001D0000 -#define EFI_FVB2_ALIGNMENT_1G 0x001E0000 -#define EFI_FVB2_ALIGNMENT_2G 0x001F0000 - -struct fv_blkmap_entry { - /* The number of sequential blocks which are of the same size */ - u32 num_blocks; - /* The size of the blocks */ - u32 length; -}; - -/* Describes the features and layout of the firmware volume */ -struct fv_header { - /* - * The first 16 bytes are reserved to allow for the reset vector of - * processors whose reset vector is at address 0. - */ - u8 zero_vec[16]; - /* - * Declares the file system with which the firmware volume - * is formatted. - */ - efi_guid_t fs_guid; - /* - * Length in bytes of the complete firmware volume, including - * the header. - */ - u64 fv_len; - /* Set to EFI_FVH_SIGNATURE */ - u32 sign; - /* - * Declares capabilities and power-on defaults for the firmware - * volume. - */ - u32 attr; - /* Length in bytes of the complete firmware volume header */ - u16 hdr_len; - /* - * A 16-bit checksum of the firmware volume header. - * A valid header sums to zero. - */ - u16 checksum; - /* - * Offset, relative to the start of the header, of the extended - * header (EFI_FIRMWARE_VOLUME_EXT_HEADER) or zero if there is - * no extended header. - */ - u16 ext_hdr_off; - /* This field must always be set to zero */ - u8 reserved[1]; - /* - * Set to 2. Future versions of this specification may define new - * header fields and will increment the Revision field accordingly. - */ - u8 rev; - /* - * An array of run-length encoded FvBlockMapEntry structures. - * The array is terminated with an entry of {0,0}. - */ - struct fv_blkmap_entry block_map[1]; -}; - -#define EFI_FVH_SIGNATURE SIGNATURE_32('_', 'F', 'V', 'H') - -/* Firmware Volume Header Revision definition */ -#define EFI_FVH_REVISION 0x02 - -/* Extension header pointed by ExtHeaderOffset of volume header */ -struct fv_ext_header { - /* firmware volume name */ - efi_guid_t fv_name; - /* Size of the rest of the extension header including this structure */ - u32 ext_hdr_size; -}; - -#endif diff --git a/arch/x86/include/asm/fsp/fsp_hob.h b/arch/x86/include/asm/fsp/fsp_hob.h deleted file mode 100644 index 3bb79c4b67..0000000000 --- a/arch/x86/include/asm/fsp/fsp_hob.h +++ /dev/null @@ -1,98 +0,0 @@ -/* SPDX-License-Identifier: Intel */ -/* - * Copyright (C) 2013, Intel Corporation - * Copyright (C) 2014, Bin Meng - */ - -#ifndef __FSP_HOB_H__ -#define __FSP_HOB_H__ - -#include - -enum pixel_format { - pixel_rgbx_8bpc, /* RGB 8 bit per color */ - pixel_bgrx_8bpc, /* BGR 8 bit per color */ - pixel_bitmask, -}; - -struct __packed hob_graphics_info { - phys_addr_t fb_base; /* framebuffer base address */ - u32 fb_size; /* framebuffer size */ - u32 version; - u32 width; - u32 height; - enum pixel_format pixel_format; - u32 red_mask; - u32 green_mask; - u32 blue_mask; - u32 reserved_mask; - u32 pixels_per_scanline; -}; - -/* FSP specific GUID HOB definitions */ -#define FSP_GUID_DATA1 0x912740be -#define FSP_GUID_DATA2 0x2284 -#define FSP_GUID_DATA3 0x4734 -#define FSP_GUID_DATA4_0 0xb9 -#define FSP_GUID_DATA4_1 0x71 -#define FSP_GUID_DATA4_2 0x84 -#define FSP_GUID_DATA4_3 0xb0 -#define FSP_GUID_DATA4_4 0x27 -#define FSP_GUID_DATA4_5 0x35 -#define FSP_GUID_DATA4_6 0x3f -#define FSP_GUID_DATA4_7 0x0c - -#define FSP_GUID_BYTE0 0xbe -#define FSP_GUID_BYTE1 0x40 -#define FSP_GUID_BYTE2 0x27 -#define FSP_GUID_BYTE3 0x91 -#define FSP_GUID_BYTE4 0x84 -#define FSP_GUID_BYTE5 0x22 -#define FSP_GUID_BYTE6 0x34 -#define FSP_GUID_BYTE7 0x47 -#define FSP_GUID_BYTE8 FSP_GUID_DATA4_0 -#define FSP_GUID_BYTE9 FSP_GUID_DATA4_1 -#define FSP_GUID_BYTE10 FSP_GUID_DATA4_2 -#define FSP_GUID_BYTE11 FSP_GUID_DATA4_3 -#define FSP_GUID_BYTE12 FSP_GUID_DATA4_4 -#define FSP_GUID_BYTE13 FSP_GUID_DATA4_5 -#define FSP_GUID_BYTE14 FSP_GUID_DATA4_6 -#define FSP_GUID_BYTE15 FSP_GUID_DATA4_7 - -#define FSP_HEADER_GUID \ - EFI_GUID(FSP_GUID_DATA1, FSP_GUID_DATA2, FSP_GUID_DATA3, \ - FSP_GUID_DATA4_0, FSP_GUID_DATA4_1, FSP_GUID_DATA4_2, \ - FSP_GUID_DATA4_3, FSP_GUID_DATA4_4, FSP_GUID_DATA4_5, \ - FSP_GUID_DATA4_6, FSP_GUID_DATA4_7) - -#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \ - EFI_GUID(0x721acf02, 0x4d77, 0x4c2a, \ - 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0) - -#define FSP_BOOTLOADER_TEMP_MEM_HOB_GUID \ - EFI_GUID(0xbbcff46c, 0xc8d3, 0x4113, \ - 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e) - -#define FSP_HOB_RESOURCE_OWNER_FSP_GUID \ - EFI_GUID(0x69a79759, 0x1373, 0x4367, \ - 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e) - -#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \ - EFI_GUID(0xd038747c, 0xd00c, 0x4980, \ - 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55) - -#define FSP_HOB_RESOURCE_OWNER_GRAPHICS_GUID \ - EFI_GUID(0x9c7c3aa7, 0x5332, 0x4917, \ - 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07) - -/* The following GUIDs are newly introduced in FSP spec 1.1 */ - -#define FSP_HOB_RESOURCE_OWNER_BOOTLOADER_TOLUM_GUID \ - EFI_GUID(0x73ff4f56, 0xaa8e, 0x4451, \ - 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44) - -#define FSP_GRAPHICS_INFO_HOB_GUID \ - EFI_GUID(0x39f62cce, 0x6825, 0x4669, \ - 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07) - -#endif diff --git a/arch/x86/include/asm/fsp/fsp_infoheader.h b/arch/x86/include/asm/fsp/fsp_infoheader.h deleted file mode 100644 index 86f78014b7..0000000000 --- a/arch/x86/include/asm/fsp/fsp_infoheader.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: Intel */ -/* - * Copyright (C) 2013, Intel Corporation - * Copyright (C) 2014, Bin Meng - */ - -#ifndef _FSP_HEADER_H_ -#define _FSP_HEADER_H_ - -#define FSP_HEADER_OFF 0x94 /* Fixed FSP header offset in the FSP image */ - -struct __packed fsp_header { - u32 sign; /* 'FSPH' */ - u32 hdr_len; /* header length */ - u8 reserved1[3]; - u8 hdr_rev; /* header rev */ - u32 img_rev; /* image rev */ - char img_id[8]; /* signature string */ - u32 img_size; /* image size */ - u32 img_base; /* image base */ - u32 img_attr; /* image attribute */ - u32 cfg_region_off; /* configuration region offset */ - u32 cfg_region_size; /* configuration region size */ - u32 api_num; /* number of API entries */ - u32 fsp_tempram_init; /* tempram_init offset */ - u32 fsp_init; /* fsp_init offset */ - u32 fsp_notify; /* fsp_notify offset */ - u32 fsp_mem_init; /* fsp_mem_init offset */ - u32 fsp_tempram_exit; /* fsp_tempram_exit offset */ - u32 fsp_silicon_init; /* fsp_silicon_init offset */ -}; - -#define FSP_HEADER_REVISION_1 1 -#define FSP_HEADER_REVISION_2 2 - -#define FSP_ATTR_GRAPHICS_SUPPORT (1 << 0) - -#endif diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h deleted file mode 100644 index 7b92392a27..0000000000 --- a/arch/x86/include/asm/fsp/fsp_support.h +++ /dev/null @@ -1,188 +0,0 @@ -/* SPDX-License-Identifier: Intel */ -/* - * Copyright (C) 2013, Intel Corporation - * Copyright (C) 2014, Bin Meng - */ - -#ifndef __FSP_SUPPORT_H__ -#define __FSP_SUPPORT_H__ - -#include "fsp_types.h" -#include "fsp_hob.h" -#include "fsp_fv.h" -#include "fsp_ffs.h" -#include "fsp_api.h" -#include "fsp_infoheader.h" -#include "fsp_bootmode.h" -#include "fsp_azalia.h" -#include -#include - -#define FSP_LOWMEM_BASE 0x100000UL -#define FSP_HIGHMEM_BASE 0x100000000ULL -#define UPD_TERMINATOR 0x55AA - - -/** - * FSP Continuation assembly helper routine - * - * This routine jumps to the C version of FSP continuation function - */ -void asm_continuation(void); - -/** - * FSP initialization complete - * - * This is the function that indicates FSP initialization is complete and jumps - * back to the bootloader with HOB list pointer as the parameter. - * - * @hob_list: HOB list pointer - */ -void fsp_init_done(void *hob_list); - -/** - * FSP Continuation function - * - * @status: Always 0 - * @hob_list: HOB list pointer - * - * @retval: Never returns - */ -void fsp_continue(u32 status, void *hob_list); - -/** - * Find FSP header offset in FSP image - * - * @retval: the offset of FSP header. If signature is invalid, returns 0. - */ -struct fsp_header *find_fsp_header(void); - -/** - * FSP initialization wrapper function. - * - * @stack_top: bootloader stack top address - * @boot_mode: boot mode defined in fsp_bootmode.h - * @nvs_buf: Non-volatile memory buffer pointer - */ -void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf); - -/** - * FSP notification wrapper function - * - * @fsp_hdr: Pointer to FSP information header - * @phase: FSP initialization phase defined in enum fsp_phase - * - * @retval: compatible status code with EFI_STATUS defined in PI spec - */ -u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase); - -/** - * This function retrieves the top of usable low memory. - * - * @hob_list: A HOB list pointer. - * - * @retval: Usable low memory top. - */ -u32 fsp_get_usable_lowmem_top(const void *hob_list); - -/** - * This function retrieves the top of usable high memory. - * - * @hob_list: A HOB list pointer. - * - * @retval: Usable high memory top. - */ -u64 fsp_get_usable_highmem_top(const void *hob_list); - -/** - * This function retrieves a special reserved memory region. - * - * @hob_list: A HOB list pointer. - * @len: A pointer to the GUID HOB data buffer length. - * If the GUID HOB is located, the length will be updated. - * @guid: A pointer to the owner guild. - * - * @retval: Reserved region start address. - * 0 if this region does not exist. - */ -u64 fsp_get_reserved_mem_from_guid(const void *hob_list, - u64 *len, const efi_guid_t *guid); - -/** - * This function retrieves the FSP reserved normal memory. - * - * @hob_list: A HOB list pointer. - * @len: A pointer to the FSP reserved memory length buffer. - * If the GUID HOB is located, the length will be updated. - * @retval: FSP reserved memory base - * 0 if this region does not exist. - */ -u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len); - -/** - * This function retrieves the TSEG reserved normal memory. - * - * @hob_list: A HOB list pointer. - * @len: A pointer to the TSEG reserved memory length buffer. - * If the GUID HOB is located, the length will be updated. - * - * @retval NULL: Failed to find the TSEG reserved memory. - * @retval others: TSEG reserved memory base. - */ -u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len); - -/** - * This function retrieves FSP Non-volatile Storage HOB buffer and size. - * - * @hob_list: A HOB list pointer. - * @len: A pointer to the NVS data buffer length. - * If the HOB is located, the length will be updated. - * - * @retval NULL: Failed to find the NVS HOB. - * @retval others: FSP NVS data buffer pointer. - */ -void *fsp_get_nvs_data(const void *hob_list, u32 *len); - -/** - * This function retrieves Bootloader temporary stack buffer and size. - * - * @hob_list: A HOB list pointer. - * @len: A pointer to the bootloader temporary stack length. - * If the HOB is located, the length will be updated. - * - * @retval NULL: Failed to find the bootloader temporary stack HOB. - * @retval others: Bootloader temporary stackbuffer pointer. - */ -void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len); - -/** - * This function retrieves graphics information. - * - * @hob_list: A HOB list pointer. - * @len: A pointer to the graphics info HOB length. - * If the HOB is located, the length will be updated. - * - * @retval NULL: Failed to find the graphics info HOB. - * @retval others: A pointer to struct hob_graphics_info. - */ -void *fsp_get_graphics_info(const void *hob_list, u32 *len); - -/** - * This function overrides the default configurations of FSP. - * - * @config: A pointer to the FSP configuration data structure - * @rt_buf: A pointer to the FSP runtime buffer data structure - * - * @return: None - */ -void update_fsp_configs(struct fsp_config_data *config, - struct fspinit_rtbuf *rt_buf); - -/** - * fsp_init_phase_pci() - Tell the FSP that we have completed PCI init - * - * @return 0 if OK, -EPERM if the FSP gave an error. - */ -int fsp_init_phase_pci(void); - -#endif diff --git a/arch/x86/include/asm/fsp/fsp_types.h b/arch/x86/include/asm/fsp/fsp_types.h deleted file mode 100644 index 3d5b17ecf1..0000000000 --- a/arch/x86/include/asm/fsp/fsp_types.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: Intel */ -/* - * Copyright (C) 2013, Intel Corporation - * Copyright (C) 2014, Bin Meng - */ - -#ifndef __FSP_TYPES_H__ -#define __FSP_TYPES_H__ - -/** - * Returns a 16-bit signature built from 2 ASCII characters. - * - * This macro returns a 16-bit value built from the two ASCII characters - * specified by A and B. - * - * @A: The first ASCII character. - * @B: The second ASCII character. - * - * @return: A 16-bit value built from the two ASCII characters specified by - * A and B. - */ -#define SIGNATURE_16(A, B) ((A) | (B << 8)) - -/** - * Returns a 32-bit signature built from 4 ASCII characters. - * - * This macro returns a 32-bit value built from the four ASCII characters - * specified by A, B, C, and D. - * - * @A: The first ASCII character. - * @B: The second ASCII character. - * @C: The third ASCII character. - * @D: The fourth ASCII character. - * - * @return: A 32-bit value built from the two ASCII characters specified by - * A, B, C and D. - */ -#define SIGNATURE_32(A, B, C, D) \ - (SIGNATURE_16(A, B) | (SIGNATURE_16(C, D) << 16)) - -/** - * Returns a 64-bit signature built from 8 ASCII characters. - * - * This macro returns a 64-bit value built from the eight ASCII characters - * specified by A, B, C, D, E, F, G,and H. - * - * @A: The first ASCII character. - * @B: The second ASCII character. - * @C: The third ASCII character. - * @D: The fourth ASCII character. - * @E: The fifth ASCII character. - * @F: The sixth ASCII character. - * @G: The seventh ASCII character. - * @H: The eighth ASCII character. - * - * @return: A 64-bit value built from the two ASCII characters specified by - * A, B, C, D, E, F, G and H. - */ -#define SIGNATURE_64(A, B, C, D, E, F, G, H) \ - (SIGNATURE_32(A, B, C, D) | ((u64)(SIGNATURE_32(E, F, G, H)) << 32)) - -#endif diff --git a/arch/x86/include/asm/fsp1/fsp_api.h b/arch/x86/include/asm/fsp1/fsp_api.h new file mode 100644 index 0000000000..f2d70799f3 --- /dev/null +++ b/arch/x86/include/asm/fsp1/fsp_api.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + */ + +#ifndef __FSP_API_H__ +#define __FSP_API_H__ + +#include + +/* + * FSP common configuration structure. + * This needs to be included in the platform-specific struct fsp_config_data. + */ +struct fsp_cfg_common { + struct fsp_header *fsp_hdr; + u32 stack_top; + u32 boot_mode; +}; + +/* + * FspInit continuation function prototype. + * Control will be returned to this callback function after FspInit API call. + */ +typedef void (*fsp_continuation_f)(u32 status, void *hob_list); + +struct fsp_init_params { + /* Non-volatile storage buffer pointer */ + void *nvs_buf; + /* Runtime buffer pointer */ + void *rt_buf; + /* Continuation function address */ + fsp_continuation_f continuation; +}; + +struct common_buf { + /* + * Stack top pointer used by the bootloader. The new stack frame will be + * set up at this location after FspInit API call. + */ + u32 stack_top; + u32 boot_mode; /* Current system boot mode */ + void *upd_data; /* User platform configuraiton data region */ + u32 tolum_size; /* Top of low usable memory size (FSP 1.1) */ + u32 reserved[6]; /* Reserved */ +}; + +enum fsp_phase { + /* Notification code for post PCI enuermation */ + INIT_PHASE_PCI = 0x20, + /* Notification code before transfering control to the payload */ + INIT_PHASE_BOOT = 0x40 +}; + +struct fsp_notify_params { + /* Notification phase used for NotifyPhase API */ + enum fsp_phase phase; +}; + +/* FspInit API function prototype */ +typedef asmlinkage u32 (*fsp_init_f)(struct fsp_init_params *params); + +/* FspNotify API function prototype */ +typedef asmlinkage u32 (*fsp_notify_f)(struct fsp_notify_params *params); + +#endif diff --git a/arch/x86/include/asm/fsp1/fsp_azalia.h b/arch/x86/include/asm/fsp1/fsp_azalia.h new file mode 100644 index 0000000000..e59180bdae --- /dev/null +++ b/arch/x86/include/asm/fsp1/fsp_azalia.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2015, Google, Inc + */ + +#ifndef _FSP_AZALIA_H_ +#define _FSP_AZALIA_H_ + +struct __packed azalia_verb_table_header { + u32 vendor_device_id; + u16 sub_system_id; + u8 revision_id; /* 0xff applies to all steppings */ + u8 front_panel_support; + u16 number_of_rear_jacks; + u16 number_of_front_jacks; +}; + +struct __packed azalia_verb_table { + struct azalia_verb_table_header header; + const u32 *data; +}; + +struct __packed azalia_config { + u8 pme_enable:1; + u8 docking_supported:1; + u8 docking_attached:1; + u8 hdmi_codec_enable:1; + u8 azalia_v_ci_enable:1; + u8 rsvdbits:3; + /* number of verb tables provided by platform */ + u8 verb_table_num; + const struct azalia_verb_table *verb_table; + /* delay timer after azalia reset */ + u16 reset_wait_timer_ms; +}; + +#endif diff --git a/arch/x86/include/asm/fsp1/fsp_bootmode.h b/arch/x86/include/asm/fsp1/fsp_bootmode.h new file mode 100644 index 0000000000..bc96ec308c --- /dev/null +++ b/arch/x86/include/asm/fsp1/fsp_bootmode.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + */ + +#ifndef __FSP_BOOT_MODE_H__ +#define __FSP_BOOT_MODE_H__ + +/* 0x21 - 0xf..f are reserved */ +#define BOOT_FULL_CONFIG 0x00 +#define BOOT_MINIMAL_CONFIG 0x01 +#define BOOT_NO_CONFIG_CHANGES 0x02 +#define BOOT_FULL_CONFIG_PLUS_DIAG 0x03 +#define BOOT_DEFAULT_SETTINGS 0x04 +#define BOOT_ON_S4_RESUME 0x05 +#define BOOT_ON_S5_RESUME 0x06 +#define BOOT_ON_S2_RESUME 0x10 +#define BOOT_ON_S3_RESUME 0x11 +#define BOOT_ON_FLASH_UPDATE 0x12 +#define BOOT_IN_RECOVERY_MODE 0x20 + +#endif diff --git a/arch/x86/include/asm/fsp1/fsp_ffs.h b/arch/x86/include/asm/fsp1/fsp_ffs.h new file mode 100644 index 0000000000..b7558e5a17 --- /dev/null +++ b/arch/x86/include/asm/fsp1/fsp_ffs.h @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + */ + +#ifndef __FSP_FFS_H__ +#define __FSP_FFS_H__ + +/* Used to verify the integrity of the file */ +union __packed ffs_integrity { + struct { + /* + * The IntegrityCheck.checksum.header field is an 8-bit + * checksum of the file header. The State and + * IntegrityCheck.checksum.file fields are assumed to be zero + * and the checksum is calculated such that the entire header + * sums to zero. + */ + u8 header; + /* + * If the FFS_ATTRIB_CHECKSUM (see definition below) bit of + * the Attributes field is set to one, the + * IntegrityCheck.checksum.file field is an 8-bit checksum of + * the file data. If the FFS_ATTRIB_CHECKSUM bit of the + * Attributes field is cleared to zero, the + * IntegrityCheck.checksum.file field must be initialized with + * a value of 0xAA. The IntegrityCheck.checksum.file field is + * valid any time the EFI_FILE_DATA_VALID bit is set in the + * State field. + */ + u8 file; + } checksum; + + /* This is the full 16 bits of the IntegrityCheck field */ + u16 checksum16; +}; + +/* + * Each file begins with the header that describe the + * contents and state of the files. + */ +struct __packed ffs_file_header { + /* + * This GUID is the file name. + * It is used to uniquely identify the file. + */ + efi_guid_t name; + /* Used to verify the integrity of the file */ + union ffs_integrity integrity; + /* Identifies the type of file */ + u8 type; + /* Declares various file attribute bits */ + u8 attr; + /* The length of the file in bytes, including the FFS header */ + u8 size[3]; + /* + * Used to track the state of the file throughout the life of + * the file from creation to deletion. + */ + u8 state; +}; + +struct __packed ffs_file_header2 { + /* + * This GUID is the file name. It is used to uniquely identify the file. + * There may be only one instance of a file with the file name GUID of + * Name in any given firmware volume, except if the file type is + * EFI_FV_FILE_TYPE_FFS_PAD. + */ + efi_guid_t name; + /* Used to verify the integrity of the file */ + union ffs_integrity integrity; + /* Identifies the type of file */ + u8 type; + /* Declares various file attribute bits */ + u8 attr; + /* + * The length of the file in bytes, including the FFS header. + * The length of the file data is either + * (size - sizeof(struct ffs_file_header)). This calculation means a + * zero-length file has a size of 24 bytes, which is + * sizeof(struct ffs_file_header). Size is not required to be a + * multiple of 8 bytes. Given a file F, the next file header is located + * at the next 8-byte aligned firmware volume offset following the last + * byte of the file F. + */ + u8 size[3]; + /* + * Used to track the state of the file throughout the life of + * the file from creation to deletion. + */ + u8 state; + /* + * If FFS_ATTRIB_LARGE_FILE is set in attr, then ext_size exists + * and size must be set to zero. + * If FFS_ATTRIB_LARGE_FILE is not set then + * struct ffs_file_header is used. + */ + u32 ext_size; +}; + +/* + * Pseudo type. It is used as a wild card when retrieving sections. + * The section type EFI_SECTION_ALL matches all section types. + */ +#define EFI_SECTION_ALL 0x00 + +/* Encapsulation section Type values */ +#define EFI_SECTION_COMPRESSION 0x01 +#define EFI_SECTION_GUID_DEFINED 0x02 +#define EFI_SECTION_DISPOSABLE 0x03 + +/* Leaf section Type values */ +#define EFI_SECTION_PE32 0x10 +#define EFI_SECTION_PIC 0x11 +#define EFI_SECTION_TE 0x12 +#define EFI_SECTION_DXE_DEPEX 0x13 +#define EFI_SECTION_VERSION 0x14 +#define EFI_SECTION_USER_INTERFACE 0x15 +#define EFI_SECTION_COMPATIBILITY16 0x16 +#define EFI_SECTION_FIRMWARE_VOLUME_IMAGE 0x17 +#define EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18 +#define EFI_SECTION_RAW 0x19 +#define EFI_SECTION_PEI_DEPEX 0x1B +#define EFI_SECTION_SMM_DEPEX 0x1C + +/* Common section header */ +struct __packed raw_section { + /* + * A 24-bit unsigned integer that contains the total size of + * the section in bytes, including the EFI_COMMON_SECTION_HEADER. + */ + u8 size[3]; + u8 type; +}; + +struct __packed raw_section2 { + /* + * A 24-bit unsigned integer that contains the total size of + * the section in bytes, including the EFI_COMMON_SECTION_HEADER. + */ + u8 size[3]; + u8 type; + /* + * If size is 0xFFFFFF, then ext_size contains the size of + * the section. If size is not equal to 0xFFFFFF, then this + * field does not exist. + */ + u32 ext_size; +}; + +#endif diff --git a/arch/x86/include/asm/fsp1/fsp_fv.h b/arch/x86/include/asm/fsp1/fsp_fv.h new file mode 100644 index 0000000000..511dfb78b8 --- /dev/null +++ b/arch/x86/include/asm/fsp1/fsp_fv.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + */ + +#ifndef __FSP_FV___ +#define __FSP_FV___ + +/* Value of EFI_FV_FILE_ATTRIBUTES */ +#define EFI_FV_FILE_ATTR_ALIGNMENT 0x0000001F +#define EFI_FV_FILE_ATTR_FIXED 0x00000100 +#define EFI_FV_FILE_ATTR_MEMORY_MAPPED 0x00000200 + +/* Attributes bit definitions */ +#define EFI_FVB2_READ_DISABLED_CAP 0x00000001 +#define EFI_FVB2_READ_ENABLED_CAP 0x00000002 +#define EFI_FVB2_READ_STATUS 0x00000004 +#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008 +#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010 +#define EFI_FVB2_WRITE_STATUS 0x00000020 +#define EFI_FVB2_LOCK_CAP 0x00000040 +#define EFI_FVB2_LOCK_STATUS 0x00000080 +#define EFI_FVB2_STICKY_WRITE 0x00000200 +#define EFI_FVB2_MEMORY_MAPPED 0x00000400 +#define EFI_FVB2_ERASE_POLARITY 0x00000800 +#define EFI_FVB2_READ_LOCK_CAP 0x00001000 +#define EFI_FVB2_READ_LOCK_STATUS 0x00002000 +#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000 +#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000 +#define EFI_FVB2_ALIGNMENT 0x001F0000 +#define EFI_FVB2_ALIGNMENT_1 0x00000000 +#define EFI_FVB2_ALIGNMENT_2 0x00010000 +#define EFI_FVB2_ALIGNMENT_4 0x00020000 +#define EFI_FVB2_ALIGNMENT_8 0x00030000 +#define EFI_FVB2_ALIGNMENT_16 0x00040000 +#define EFI_FVB2_ALIGNMENT_32 0x00050000 +#define EFI_FVB2_ALIGNMENT_64 0x00060000 +#define EFI_FVB2_ALIGNMENT_128 0x00070000 +#define EFI_FVB2_ALIGNMENT_256 0x00080000 +#define EFI_FVB2_ALIGNMENT_512 0x00090000 +#define EFI_FVB2_ALIGNMENT_1K 0x000A0000 +#define EFI_FVB2_ALIGNMENT_2K 0x000B0000 +#define EFI_FVB2_ALIGNMENT_4K 0x000C0000 +#define EFI_FVB2_ALIGNMENT_8K 0x000D0000 +#define EFI_FVB2_ALIGNMENT_16K 0x000E0000 +#define EFI_FVB2_ALIGNMENT_32K 0x000F0000 +#define EFI_FVB2_ALIGNMENT_64K 0x00100000 +#define EFI_FVB2_ALIGNMENT_128K 0x00110000 +#define EFI_FVB2_ALIGNMENT_256K 0x00120000 +#define EFI_FVB2_ALIGNMENT_512K 0x00130000 +#define EFI_FVB2_ALIGNMENT_1M 0x00140000 +#define EFI_FVB2_ALIGNMENT_2M 0x00150000 +#define EFI_FVB2_ALIGNMENT_4M 0x00160000 +#define EFI_FVB2_ALIGNMENT_8M 0x00170000 +#define EFI_FVB2_ALIGNMENT_16M 0x00180000 +#define EFI_FVB2_ALIGNMENT_32M 0x00190000 +#define EFI_FVB2_ALIGNMENT_64M 0x001A0000 +#define EFI_FVB2_ALIGNMENT_128M 0x001B0000 +#define EFI_FVB2_ALIGNMENT_256M 0x001C0000 +#define EFI_FVB2_ALIGNMENT_512M 0x001D0000 +#define EFI_FVB2_ALIGNMENT_1G 0x001E0000 +#define EFI_FVB2_ALIGNMENT_2G 0x001F0000 + +struct fv_blkmap_entry { + /* The number of sequential blocks which are of the same size */ + u32 num_blocks; + /* The size of the blocks */ + u32 length; +}; + +/* Describes the features and layout of the firmware volume */ +struct fv_header { + /* + * The first 16 bytes are reserved to allow for the reset vector of + * processors whose reset vector is at address 0. + */ + u8 zero_vec[16]; + /* + * Declares the file system with which the firmware volume + * is formatted. + */ + efi_guid_t fs_guid; + /* + * Length in bytes of the complete firmware volume, including + * the header. + */ + u64 fv_len; + /* Set to EFI_FVH_SIGNATURE */ + u32 sign; + /* + * Declares capabilities and power-on defaults for the firmware + * volume. + */ + u32 attr; + /* Length in bytes of the complete firmware volume header */ + u16 hdr_len; + /* + * A 16-bit checksum of the firmware volume header. + * A valid header sums to zero. + */ + u16 checksum; + /* + * Offset, relative to the start of the header, of the extended + * header (EFI_FIRMWARE_VOLUME_EXT_HEADER) or zero if there is + * no extended header. + */ + u16 ext_hdr_off; + /* This field must always be set to zero */ + u8 reserved[1]; + /* + * Set to 2. Future versions of this specification may define new + * header fields and will increment the Revision field accordingly. + */ + u8 rev; + /* + * An array of run-length encoded FvBlockMapEntry structures. + * The array is terminated with an entry of {0,0}. + */ + struct fv_blkmap_entry block_map[1]; +}; + +#define EFI_FVH_SIGNATURE SIGNATURE_32('_', 'F', 'V', 'H') + +/* Firmware Volume Header Revision definition */ +#define EFI_FVH_REVISION 0x02 + +/* Extension header pointed by ExtHeaderOffset of volume header */ +struct fv_ext_header { + /* firmware volume name */ + efi_guid_t fv_name; + /* Size of the rest of the extension header including this structure */ + u32 ext_hdr_size; +}; + +#endif diff --git a/arch/x86/include/asm/fsp1/fsp_hob.h b/arch/x86/include/asm/fsp1/fsp_hob.h new file mode 100644 index 0000000000..3bb79c4b67 --- /dev/null +++ b/arch/x86/include/asm/fsp1/fsp_hob.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + */ + +#ifndef __FSP_HOB_H__ +#define __FSP_HOB_H__ + +#include + +enum pixel_format { + pixel_rgbx_8bpc, /* RGB 8 bit per color */ + pixel_bgrx_8bpc, /* BGR 8 bit per color */ + pixel_bitmask, +}; + +struct __packed hob_graphics_info { + phys_addr_t fb_base; /* framebuffer base address */ + u32 fb_size; /* framebuffer size */ + u32 version; + u32 width; + u32 height; + enum pixel_format pixel_format; + u32 red_mask; + u32 green_mask; + u32 blue_mask; + u32 reserved_mask; + u32 pixels_per_scanline; +}; + +/* FSP specific GUID HOB definitions */ +#define FSP_GUID_DATA1 0x912740be +#define FSP_GUID_DATA2 0x2284 +#define FSP_GUID_DATA3 0x4734 +#define FSP_GUID_DATA4_0 0xb9 +#define FSP_GUID_DATA4_1 0x71 +#define FSP_GUID_DATA4_2 0x84 +#define FSP_GUID_DATA4_3 0xb0 +#define FSP_GUID_DATA4_4 0x27 +#define FSP_GUID_DATA4_5 0x35 +#define FSP_GUID_DATA4_6 0x3f +#define FSP_GUID_DATA4_7 0x0c + +#define FSP_GUID_BYTE0 0xbe +#define FSP_GUID_BYTE1 0x40 +#define FSP_GUID_BYTE2 0x27 +#define FSP_GUID_BYTE3 0x91 +#define FSP_GUID_BYTE4 0x84 +#define FSP_GUID_BYTE5 0x22 +#define FSP_GUID_BYTE6 0x34 +#define FSP_GUID_BYTE7 0x47 +#define FSP_GUID_BYTE8 FSP_GUID_DATA4_0 +#define FSP_GUID_BYTE9 FSP_GUID_DATA4_1 +#define FSP_GUID_BYTE10 FSP_GUID_DATA4_2 +#define FSP_GUID_BYTE11 FSP_GUID_DATA4_3 +#define FSP_GUID_BYTE12 FSP_GUID_DATA4_4 +#define FSP_GUID_BYTE13 FSP_GUID_DATA4_5 +#define FSP_GUID_BYTE14 FSP_GUID_DATA4_6 +#define FSP_GUID_BYTE15 FSP_GUID_DATA4_7 + +#define FSP_HEADER_GUID \ + EFI_GUID(FSP_GUID_DATA1, FSP_GUID_DATA2, FSP_GUID_DATA3, \ + FSP_GUID_DATA4_0, FSP_GUID_DATA4_1, FSP_GUID_DATA4_2, \ + FSP_GUID_DATA4_3, FSP_GUID_DATA4_4, FSP_GUID_DATA4_5, \ + FSP_GUID_DATA4_6, FSP_GUID_DATA4_7) + +#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \ + EFI_GUID(0x721acf02, 0x4d77, 0x4c2a, \ + 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0) + +#define FSP_BOOTLOADER_TEMP_MEM_HOB_GUID \ + EFI_GUID(0xbbcff46c, 0xc8d3, 0x4113, \ + 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e) + +#define FSP_HOB_RESOURCE_OWNER_FSP_GUID \ + EFI_GUID(0x69a79759, 0x1373, 0x4367, \ + 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e) + +#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \ + EFI_GUID(0xd038747c, 0xd00c, 0x4980, \ + 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55) + +#define FSP_HOB_RESOURCE_OWNER_GRAPHICS_GUID \ + EFI_GUID(0x9c7c3aa7, 0x5332, 0x4917, \ + 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07) + +/* The following GUIDs are newly introduced in FSP spec 1.1 */ + +#define FSP_HOB_RESOURCE_OWNER_BOOTLOADER_TOLUM_GUID \ + EFI_GUID(0x73ff4f56, 0xaa8e, 0x4451, \ + 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44) + +#define FSP_GRAPHICS_INFO_HOB_GUID \ + EFI_GUID(0x39f62cce, 0x6825, 0x4669, \ + 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07) + +#endif diff --git a/arch/x86/include/asm/fsp1/fsp_infoheader.h b/arch/x86/include/asm/fsp1/fsp_infoheader.h new file mode 100644 index 0000000000..86f78014b7 --- /dev/null +++ b/arch/x86/include/asm/fsp1/fsp_infoheader.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + */ + +#ifndef _FSP_HEADER_H_ +#define _FSP_HEADER_H_ + +#define FSP_HEADER_OFF 0x94 /* Fixed FSP header offset in the FSP image */ + +struct __packed fsp_header { + u32 sign; /* 'FSPH' */ + u32 hdr_len; /* header length */ + u8 reserved1[3]; + u8 hdr_rev; /* header rev */ + u32 img_rev; /* image rev */ + char img_id[8]; /* signature string */ + u32 img_size; /* image size */ + u32 img_base; /* image base */ + u32 img_attr; /* image attribute */ + u32 cfg_region_off; /* configuration region offset */ + u32 cfg_region_size; /* configuration region size */ + u32 api_num; /* number of API entries */ + u32 fsp_tempram_init; /* tempram_init offset */ + u32 fsp_init; /* fsp_init offset */ + u32 fsp_notify; /* fsp_notify offset */ + u32 fsp_mem_init; /* fsp_mem_init offset */ + u32 fsp_tempram_exit; /* fsp_tempram_exit offset */ + u32 fsp_silicon_init; /* fsp_silicon_init offset */ +}; + +#define FSP_HEADER_REVISION_1 1 +#define FSP_HEADER_REVISION_2 2 + +#define FSP_ATTR_GRAPHICS_SUPPORT (1 << 0) + +#endif diff --git a/arch/x86/include/asm/fsp1/fsp_support.h b/arch/x86/include/asm/fsp1/fsp_support.h new file mode 100644 index 0000000000..7b92392a27 --- /dev/null +++ b/arch/x86/include/asm/fsp1/fsp_support.h @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + */ + +#ifndef __FSP_SUPPORT_H__ +#define __FSP_SUPPORT_H__ + +#include "fsp_types.h" +#include "fsp_hob.h" +#include "fsp_fv.h" +#include "fsp_ffs.h" +#include "fsp_api.h" +#include "fsp_infoheader.h" +#include "fsp_bootmode.h" +#include "fsp_azalia.h" +#include +#include + +#define FSP_LOWMEM_BASE 0x100000UL +#define FSP_HIGHMEM_BASE 0x100000000ULL +#define UPD_TERMINATOR 0x55AA + + +/** + * FSP Continuation assembly helper routine + * + * This routine jumps to the C version of FSP continuation function + */ +void asm_continuation(void); + +/** + * FSP initialization complete + * + * This is the function that indicates FSP initialization is complete and jumps + * back to the bootloader with HOB list pointer as the parameter. + * + * @hob_list: HOB list pointer + */ +void fsp_init_done(void *hob_list); + +/** + * FSP Continuation function + * + * @status: Always 0 + * @hob_list: HOB list pointer + * + * @retval: Never returns + */ +void fsp_continue(u32 status, void *hob_list); + +/** + * Find FSP header offset in FSP image + * + * @retval: the offset of FSP header. If signature is invalid, returns 0. + */ +struct fsp_header *find_fsp_header(void); + +/** + * FSP initialization wrapper function. + * + * @stack_top: bootloader stack top address + * @boot_mode: boot mode defined in fsp_bootmode.h + * @nvs_buf: Non-volatile memory buffer pointer + */ +void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf); + +/** + * FSP notification wrapper function + * + * @fsp_hdr: Pointer to FSP information header + * @phase: FSP initialization phase defined in enum fsp_phase + * + * @retval: compatible status code with EFI_STATUS defined in PI spec + */ +u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase); + +/** + * This function retrieves the top of usable low memory. + * + * @hob_list: A HOB list pointer. + * + * @retval: Usable low memory top. + */ +u32 fsp_get_usable_lowmem_top(const void *hob_list); + +/** + * This function retrieves the top of usable high memory. + * + * @hob_list: A HOB list pointer. + * + * @retval: Usable high memory top. + */ +u64 fsp_get_usable_highmem_top(const void *hob_list); + +/** + * This function retrieves a special reserved memory region. + * + * @hob_list: A HOB list pointer. + * @len: A pointer to the GUID HOB data buffer length. + * If the GUID HOB is located, the length will be updated. + * @guid: A pointer to the owner guild. + * + * @retval: Reserved region start address. + * 0 if this region does not exist. + */ +u64 fsp_get_reserved_mem_from_guid(const void *hob_list, + u64 *len, const efi_guid_t *guid); + +/** + * This function retrieves the FSP reserved normal memory. + * + * @hob_list: A HOB list pointer. + * @len: A pointer to the FSP reserved memory length buffer. + * If the GUID HOB is located, the length will be updated. + * @retval: FSP reserved memory base + * 0 if this region does not exist. + */ +u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len); + +/** + * This function retrieves the TSEG reserved normal memory. + * + * @hob_list: A HOB list pointer. + * @len: A pointer to the TSEG reserved memory length buffer. + * If the GUID HOB is located, the length will be updated. + * + * @retval NULL: Failed to find the TSEG reserved memory. + * @retval others: TSEG reserved memory base. + */ +u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len); + +/** + * This function retrieves FSP Non-volatile Storage HOB buffer and size. + * + * @hob_list: A HOB list pointer. + * @len: A pointer to the NVS data buffer length. + * If the HOB is located, the length will be updated. + * + * @retval NULL: Failed to find the NVS HOB. + * @retval others: FSP NVS data buffer pointer. + */ +void *fsp_get_nvs_data(const void *hob_list, u32 *len); + +/** + * This function retrieves Bootloader temporary stack buffer and size. + * + * @hob_list: A HOB list pointer. + * @len: A pointer to the bootloader temporary stack length. + * If the HOB is located, the length will be updated. + * + * @retval NULL: Failed to find the bootloader temporary stack HOB. + * @retval others: Bootloader temporary stackbuffer pointer. + */ +void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len); + +/** + * This function retrieves graphics information. + * + * @hob_list: A HOB list pointer. + * @len: A pointer to the graphics info HOB length. + * If the HOB is located, the length will be updated. + * + * @retval NULL: Failed to find the graphics info HOB. + * @retval others: A pointer to struct hob_graphics_info. + */ +void *fsp_get_graphics_info(const void *hob_list, u32 *len); + +/** + * This function overrides the default configurations of FSP. + * + * @config: A pointer to the FSP configuration data structure + * @rt_buf: A pointer to the FSP runtime buffer data structure + * + * @return: None + */ +void update_fsp_configs(struct fsp_config_data *config, + struct fspinit_rtbuf *rt_buf); + +/** + * fsp_init_phase_pci() - Tell the FSP that we have completed PCI init + * + * @return 0 if OK, -EPERM if the FSP gave an error. + */ +int fsp_init_phase_pci(void); + +#endif diff --git a/arch/x86/include/asm/fsp1/fsp_types.h b/arch/x86/include/asm/fsp1/fsp_types.h new file mode 100644 index 0000000000..3d5b17ecf1 --- /dev/null +++ b/arch/x86/include/asm/fsp1/fsp_types.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + */ + +#ifndef __FSP_TYPES_H__ +#define __FSP_TYPES_H__ + +/** + * Returns a 16-bit signature built from 2 ASCII characters. + * + * This macro returns a 16-bit value built from the two ASCII characters + * specified by A and B. + * + * @A: The first ASCII character. + * @B: The second ASCII character. + * + * @return: A 16-bit value built from the two ASCII characters specified by + * A and B. + */ +#define SIGNATURE_16(A, B) ((A) | (B << 8)) + +/** + * Returns a 32-bit signature built from 4 ASCII characters. + * + * This macro returns a 32-bit value built from the four ASCII characters + * specified by A, B, C, and D. + * + * @A: The first ASCII character. + * @B: The second ASCII character. + * @C: The third ASCII character. + * @D: The fourth ASCII character. + * + * @return: A 32-bit value built from the two ASCII characters specified by + * A, B, C and D. + */ +#define SIGNATURE_32(A, B, C, D) \ + (SIGNATURE_16(A, B) | (SIGNATURE_16(C, D) << 16)) + +/** + * Returns a 64-bit signature built from 8 ASCII characters. + * + * This macro returns a 64-bit value built from the eight ASCII characters + * specified by A, B, C, D, E, F, G,and H. + * + * @A: The first ASCII character. + * @B: The second ASCII character. + * @C: The third ASCII character. + * @D: The fourth ASCII character. + * @E: The fifth ASCII character. + * @F: The sixth ASCII character. + * @G: The seventh ASCII character. + * @H: The eighth ASCII character. + * + * @return: A 64-bit value built from the two ASCII characters specified by + * A, B, C, D, E, F, G and H. + */ +#define SIGNATURE_64(A, B, C, D, E, F, G, H) \ + (SIGNATURE_32(A, B, C, D) | ((u64)(SIGNATURE_32(E, F, G, H)) << 32)) + +#endif diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index c252192bf4..2466ad2ad3 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -74,7 +74,7 @@ u32 isa_map_rom(u32 bus_addr, int size); /* arch/x86/lib/... */ int video_bios_init(void); -/* arch/x86/lib/fsp/... */ +/* arch/x86/lib/fsp1,2/... */ /** * fsp_save_s3_stack() - save stack address to CMOS for next S3 boot diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 906be5eab9..a8c7448ee4 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -43,7 +43,8 @@ ifndef CONFIG_SPL_BUILD obj-$(CONFIG_CMD_ZBOOT) += zimage.o endif obj-$(CONFIG_USE_HOB) += hob.o -obj-$(CONFIG_HAVE_FSP) += fsp/ +obj-$(CONFIG_FSP_VERSION1) += fsp1/ +obj-$(CONFIG_FSP_VERSION2) += fsp2/ ifdef CONFIG_SPL_BUILD ifdef CONFIG_TPL_BUILD diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile deleted file mode 100644 index 870de71bd7..0000000000 --- a/arch/x86/lib/fsp/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2015 Google, Inc - -obj-y += fsp_car.o -obj-y += fsp_common.o -obj-y += fsp_dram.o -obj-$(CONFIG_VIDEO_FSP) += fsp_graphics.o -obj-y += fsp_support.o diff --git a/arch/x86/lib/fsp/fsp_car.S b/arch/x86/lib/fsp/fsp_car.S deleted file mode 100644 index 8c54cea3db..0000000000 --- a/arch/x86/lib/fsp/fsp_car.S +++ /dev/null @@ -1,111 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, Bin Meng - */ - -#include -#include - -.globl car_init -car_init: - /* - * Note: ebp holds the BIST value (built-in self test) so far, but ebp - * will be destroyed through the FSP call, thus we have to test the - * BIST value here before we call into FSP. - */ - test %ebp, %ebp - jz car_init_start - post_code(POST_BIST_FAILURE) - jmp die - -car_init_start: - post_code(POST_CAR_START) - lea find_fsp_header_romstack, %esp - jmp find_fsp_header - -find_fsp_header_ret: - /* EAX points to FSP_INFO_HEADER */ - mov %eax, %ebp - - /* sanity test */ - cmp $CONFIG_FSP_ADDR, %eax - jb die - - /* calculate TempRamInitEntry address */ - mov 0x30(%ebp), %eax - add 0x1c(%ebp), %eax - - /* call FSP TempRamInitEntry to setup temporary stack */ - lea temp_ram_init_romstack, %esp - jmp *%eax - -temp_ram_init_ret: - addl $4, %esp - cmp $0, %eax - jnz car_init_fail - - post_code(POST_CAR_CPU_CACHE) - - /* - * The FSP TempRamInit initializes the ecx and edx registers to - * point to a temporary but writable memory range (Cache-As-RAM). - * ecx: the start of this temporary memory range, - * edx: the end of this range. - */ - - /* stack grows down from top of CAR */ - movl %edx, %esp - subl $4, %esp - - xor %esi, %esi - jmp car_init_done - -.global fsp_init_done -fsp_init_done: - /* - * We come here from fsp_continue() with eax pointing to the HOB list. - * Save eax to esi temporarily. - */ - movl %eax, %esi - -car_init_done: - /* - * Re-initialize the ebp (BIST) to zero, as we already reach here - * which means we passed BIST testing before. - */ - xorl %ebp, %ebp - jmp car_init_ret - -car_init_fail: - post_code(POST_CAR_FAILURE) - -die: - hlt - jmp die - hlt - - /* - * The function call before CAR initialization is tricky. It cannot - * be called using the 'call' instruction but only the 'jmp' with - * the help of a handcrafted stack in the ROM. The stack needs to - * contain the function return address as well as the parameters. - */ - .balign 4 -find_fsp_header_romstack: - .long find_fsp_header_ret - - .balign 4 -temp_ram_init_romstack: - .long temp_ram_init_ret - .long temp_ram_init_params -temp_ram_init_params: -_dt_ucode_base_size: - /* These next two fields are filled in by binman */ -.globl ucode_base -ucode_base: /* Declared in microcode.h */ - .long 0 /* microcode base */ -.globl ucode_size -ucode_size: /* Declared in microcode.h */ - .long 0 /* microcode size */ - .long CONFIG_SYS_MONITOR_BASE /* code region base */ - .long CONFIG_SYS_MONITOR_LEN /* code region size */ diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c deleted file mode 100644 index ed0827c6e9..0000000000 --- a/arch/x86/lib/fsp/fsp_common.c +++ /dev/null @@ -1,165 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014, Bin Meng - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int checkcpu(void) -{ - return 0; -} - -int print_cpuinfo(void) -{ - post_code(POST_CPU_INFO); - return default_print_cpuinfo(); -} - -int fsp_init_phase_pci(void) -{ - u32 status; - - /* call into FspNotify */ - debug("Calling into FSP (notify phase INIT_PHASE_PCI): "); - status = fsp_notify(NULL, INIT_PHASE_PCI); - if (status) - debug("fail, error code %x\n", status); - else - debug("OK\n"); - - return status ? -EPERM : 0; -} - -void board_final_cleanup(void) -{ - u32 status; - - /* call into FspNotify */ - debug("Calling into FSP (notify phase INIT_PHASE_BOOT): "); - status = fsp_notify(NULL, INIT_PHASE_BOOT); - if (status) - debug("fail, error code %x\n", status); - else - debug("OK\n"); - - return; -} - -static __maybe_unused void *fsp_prepare_mrc_cache(void) -{ - struct mrc_data_container *cache; - struct mrc_region entry; - int ret; - - ret = mrccache_get_region(NULL, &entry); - if (ret) - return NULL; - - cache = mrccache_find_current(&entry); - if (!cache) - return NULL; - - debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__, - cache->data, cache->data_size, cache->checksum); - - return cache->data; -} - -#ifdef CONFIG_HAVE_ACPI_RESUME -int fsp_save_s3_stack(void) -{ - struct udevice *dev; - int ret; - - if (gd->arch.prev_sleep_state == ACPI_S3) - return 0; - - ret = uclass_get_device(UCLASS_RTC, 0, &dev); - if (ret) { - debug("Cannot find RTC: err=%d\n", ret); - return -ENODEV; - } - - /* Save the stack address to CMOS */ - ret = rtc_write32(dev, CMOS_FSP_STACK_ADDR, gd->start_addr_sp); - if (ret) { - debug("Save stack address to CMOS: err=%d\n", ret); - return -EIO; - } - - return 0; -} -#endif - -int arch_fsp_init(void) -{ - void *nvs; - int stack = CONFIG_FSP_TEMP_RAM_ADDR; - int boot_mode = BOOT_FULL_CONFIG; -#ifdef CONFIG_HAVE_ACPI_RESUME - int prev_sleep_state = chipset_prev_sleep_state(); - gd->arch.prev_sleep_state = prev_sleep_state; -#endif - - if (!gd->arch.hob_list) { -#ifdef CONFIG_ENABLE_MRC_CACHE - nvs = fsp_prepare_mrc_cache(); -#else - nvs = NULL; -#endif - -#ifdef CONFIG_HAVE_ACPI_RESUME - if (prev_sleep_state == ACPI_S3) { - if (nvs == NULL) { - /* If waking from S3 and no cache then */ - debug("No MRC cache found in S3 resume path\n"); - post_code(POST_RESUME_FAILURE); - /* Clear Sleep Type */ - chipset_clear_sleep_state(); - /* Reboot */ - debug("Rebooting..\n"); - outb(SYS_RST | RST_CPU, IO_PORT_RESET); - /* Should not reach here.. */ - panic("Reboot System"); - } - - /* - * DM is not available yet at this point, hence call - * CMOS access library which does not depend on DM. - */ - stack = cmos_read32(CMOS_FSP_STACK_ADDR); - boot_mode = BOOT_ON_S3_RESUME; - } -#endif - /* - * The first time we enter here, call fsp_init(). - * Note the execution does not return to this function, - * instead it jumps to fsp_continue(). - */ - fsp_init(stack, boot_mode, nvs); - } else { - /* - * The second time we enter here, adjust the size of malloc() - * pool before relocation. Given gd->malloc_base was adjusted - * after the call to board_init_f_init_reserve() in arch/x86/ - * cpu/start.S, we should fix up gd->malloc_limit here. - */ - gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN; - } - - return 0; -} diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c deleted file mode 100644 index 3a23b70410..0000000000 --- a/arch/x86/lib/fsp/fsp_dram.c +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2014, Bin Meng - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - phys_size_t ram_size = 0; - const struct hob_header *hdr; - struct hob_res_desc *res_desc; - - hdr = gd->arch.hob_list; - while (!end_of_hob(hdr)) { - if (hdr->type == HOB_TYPE_RES_DESC) { - res_desc = (struct hob_res_desc *)hdr; - if (res_desc->type == RES_SYS_MEM || - res_desc->type == RES_MEM_RESERVED) { - ram_size += res_desc->len; - } - } - hdr = get_next_hob(hdr); - } - - gd->ram_size = ram_size; - post_code(POST_DRAM); - -#ifdef CONFIG_ENABLE_MRC_CACHE - gd->arch.mrc_output = fsp_get_nvs_data(gd->arch.hob_list, - &gd->arch.mrc_output_len); -#endif - - return 0; -} - -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = gd->ram_size; - - return 0; -} - -/* - * This function looks for the highest region of memory lower than 4GB which - * has enough space for U-Boot where U-Boot is aligned on a page boundary. - * It overrides the default implementation found elsewhere which simply - * picks the end of ram, wherever that may be. The location of the stack, - * the relocation address, and how far U-Boot is moved by relocation are - * set in the global data structure. - */ -ulong board_get_usable_ram_top(ulong total_size) -{ - return fsp_get_usable_lowmem_top(gd->arch.hob_list); -} - -unsigned int install_e820_map(unsigned int max_entries, - struct e820_entry *entries) -{ - unsigned int num_entries = 0; - const struct hob_header *hdr; - struct hob_res_desc *res_desc; - - hdr = gd->arch.hob_list; - - while (!end_of_hob(hdr)) { - if (hdr->type == HOB_TYPE_RES_DESC) { - res_desc = (struct hob_res_desc *)hdr; - entries[num_entries].addr = res_desc->phys_start; - entries[num_entries].size = res_desc->len; - - if (res_desc->type == RES_SYS_MEM) - entries[num_entries].type = E820_RAM; - else if (res_desc->type == RES_MEM_RESERVED) - entries[num_entries].type = E820_RESERVED; - - num_entries++; - } - hdr = get_next_hob(hdr); - } - - /* Mark PCIe ECAM address range as reserved */ - entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE; - entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE; - entries[num_entries].type = E820_RESERVED; - num_entries++; - -#ifdef CONFIG_HAVE_ACPI_RESUME - /* - * Everything between U-Boot's stack and ram top needs to be - * reserved in order for ACPI S3 resume to work. - */ - entries[num_entries].addr = gd->start_addr_sp - CONFIG_STACK_SIZE; - entries[num_entries].size = gd->ram_top - gd->start_addr_sp + \ - CONFIG_STACK_SIZE; - entries[num_entries].type = E820_RESERVED; - num_entries++; -#endif - - return num_entries; -} diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c deleted file mode 100644 index 91d2d08557..0000000000 --- a/arch/x86/lib/fsp/fsp_graphics.c +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2017, Bin Meng - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -struct pixel { - u8 pos; - u8 size; -}; - -static const struct fsp_framebuffer { - struct pixel red; - struct pixel green; - struct pixel blue; - struct pixel rsvd; -} fsp_framebuffer_format_map[] = { - [pixel_rgbx_8bpc] = { {0, 8}, {8, 8}, {16, 8}, {24, 8} }, - [pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} }, -}; - -static int save_vesa_mode(struct vesa_mode_info *vesa) -{ - const struct hob_graphics_info *ginfo; - const struct fsp_framebuffer *fbinfo; - - ginfo = fsp_get_graphics_info(gd->arch.hob_list, NULL); - - /* - * If there is no graphics info structure, bail out and keep - * running on the serial console. - * - * Note: on some platforms (eg: Braswell), the FSP will not produce - * the graphics info HOB unless you plug some cables to the display - * interface (eg: HDMI) on the board. - */ - if (!ginfo) { - debug("FSP graphics hand-off block not found\n"); - return -ENXIO; - } - - vesa->x_resolution = ginfo->width; - vesa->y_resolution = ginfo->height; - vesa->bits_per_pixel = 32; - vesa->bytes_per_scanline = ginfo->pixels_per_scanline * 4; - vesa->phys_base_ptr = ginfo->fb_base; - - if (ginfo->pixel_format >= pixel_bitmask) { - debug("FSP set unknown framebuffer format: %d\n", - ginfo->pixel_format); - return -EINVAL; - } - fbinfo = &fsp_framebuffer_format_map[ginfo->pixel_format]; - vesa->red_mask_size = fbinfo->red.size; - vesa->red_mask_pos = fbinfo->red.pos; - vesa->green_mask_size = fbinfo->green.size; - vesa->green_mask_pos = fbinfo->green.pos; - vesa->blue_mask_size = fbinfo->blue.size; - vesa->blue_mask_pos = fbinfo->blue.pos; - vesa->reserved_mask_size = fbinfo->rsvd.size; - vesa->reserved_mask_pos = fbinfo->rsvd.pos; - - return 0; -} - -static int fsp_video_probe(struct udevice *dev) -{ - struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); - struct video_priv *uc_priv = dev_get_uclass_priv(dev); - struct vesa_mode_info *vesa = &mode_info.vesa; - int ret; - - printf("Video: "); - - /* Initialize vesa_mode_info structure */ - ret = save_vesa_mode(vesa); - if (ret) - goto err; - - /* - * The framebuffer base address in the FSP graphics info HOB reflects - * the value assigned by the FSP. After PCI enumeration the framebuffer - * base address may be relocated. Let's get the updated one from device. - * - * For IGD, it seems to be always on BAR2. - */ - vesa->phys_base_ptr = dm_pci_read_bar32(dev, 2); - - ret = vbe_setup_video_priv(vesa, uc_priv, plat); - if (ret) - goto err; - - printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize, - vesa->bits_per_pixel); - - return 0; - -err: - printf("No video mode configured in FSP!\n"); - return ret; -} - -static const struct udevice_id fsp_video_ids[] = { - { .compatible = "fsp-fb" }, - { } -}; - -U_BOOT_DRIVER(fsp_video) = { - .name = "fsp_video", - .id = UCLASS_VIDEO, - .of_match = fsp_video_ids, - .probe = fsp_video_probe, -}; - -static struct pci_device_id fsp_video_supported[] = { - { PCI_DEVICE_CLASS(PCI_CLASS_DISPLAY_VGA << 8, 0xffff00) }, - { }, -}; - -U_BOOT_PCI_DEVICE(fsp_video, fsp_video_supported); diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c deleted file mode 100644 index 0eaa9b232b..0000000000 --- a/arch/x86/lib/fsp/fsp_support.c +++ /dev/null @@ -1,366 +0,0 @@ -// SPDX-License-Identifier: Intel -/* - * Copyright (C) 2013, Intel Corporation - * Copyright (C) 2014, Bin Meng - */ - -#include -#include -#include - -struct fsp_header *__attribute__((optimize("O0"))) find_fsp_header(void) -{ - /* - * This function may be called before the a stack is established, - * so special care must be taken. First, it cannot declare any local - * variable using stack. Only register variable can be used here. - * Secondly, some compiler version will add prolog or epilog code - * for the C function. If so the function call may not work before - * stack is ready. - * - * GCC 4.8.1 has been verified to be working for the following codes. - */ - volatile register u8 *fsp asm("eax"); - - /* Initalize the FSP base */ - fsp = (u8 *)CONFIG_FSP_ADDR; - - /* Check the FV signature, _FVH */ - if (((struct fv_header *)fsp)->sign == EFI_FVH_SIGNATURE) { - /* Go to the end of the FV header and align the address */ - fsp += ((struct fv_header *)fsp)->ext_hdr_off; - fsp += ((struct fv_ext_header *)fsp)->ext_hdr_size; - fsp = (u8 *)(((u32)fsp + 7) & 0xFFFFFFF8); - } else { - fsp = 0; - } - - /* Check the FFS GUID */ - if (fsp && - ((struct ffs_file_header *)fsp)->name.b[0] == FSP_GUID_BYTE0 && - ((struct ffs_file_header *)fsp)->name.b[1] == FSP_GUID_BYTE1 && - ((struct ffs_file_header *)fsp)->name.b[2] == FSP_GUID_BYTE2 && - ((struct ffs_file_header *)fsp)->name.b[3] == FSP_GUID_BYTE3 && - ((struct ffs_file_header *)fsp)->name.b[4] == FSP_GUID_BYTE4 && - ((struct ffs_file_header *)fsp)->name.b[5] == FSP_GUID_BYTE5 && - ((struct ffs_file_header *)fsp)->name.b[6] == FSP_GUID_BYTE6 && - ((struct ffs_file_header *)fsp)->name.b[7] == FSP_GUID_BYTE7 && - ((struct ffs_file_header *)fsp)->name.b[8] == FSP_GUID_BYTE8 && - ((struct ffs_file_header *)fsp)->name.b[9] == FSP_GUID_BYTE9 && - ((struct ffs_file_header *)fsp)->name.b[10] == FSP_GUID_BYTE10 && - ((struct ffs_file_header *)fsp)->name.b[11] == FSP_GUID_BYTE11 && - ((struct ffs_file_header *)fsp)->name.b[12] == FSP_GUID_BYTE12 && - ((struct ffs_file_header *)fsp)->name.b[13] == FSP_GUID_BYTE13 && - ((struct ffs_file_header *)fsp)->name.b[14] == FSP_GUID_BYTE14 && - ((struct ffs_file_header *)fsp)->name.b[15] == FSP_GUID_BYTE15) { - /* Add the FFS header size to find the raw section header */ - fsp += sizeof(struct ffs_file_header); - } else { - fsp = 0; - } - - if (fsp && - ((struct raw_section *)fsp)->type == EFI_SECTION_RAW) { - /* Add the raw section header size to find the FSP header */ - fsp += sizeof(struct raw_section); - } else { - fsp = 0; - } - - return (struct fsp_header *)fsp; -} - -void fsp_continue(u32 status, void *hob_list) -{ - post_code(POST_MRC); - - assert(status == 0); - - /* The boot loader main function entry */ - fsp_init_done(hob_list); -} - -void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) -{ - struct fsp_config_data config_data; - fsp_init_f init; - struct fsp_init_params params; - struct fspinit_rtbuf rt_buf; - struct fsp_header *fsp_hdr; - struct fsp_init_params *params_ptr; -#ifdef CONFIG_FSP_USE_UPD - struct vpd_region *fsp_vpd; - struct upd_region *fsp_upd; -#endif - - fsp_hdr = find_fsp_header(); - if (fsp_hdr == NULL) { - /* No valid FSP info header was found */ - panic("Invalid FSP header"); - } - - config_data.common.fsp_hdr = fsp_hdr; - config_data.common.stack_top = stack_top; - config_data.common.boot_mode = boot_mode; - -#ifdef CONFIG_FSP_USE_UPD - /* Get VPD region start */ - fsp_vpd = (struct vpd_region *)(fsp_hdr->img_base + - fsp_hdr->cfg_region_off); - - /* Verify the VPD data region is valid */ - assert(fsp_vpd->sign == VPD_IMAGE_ID); - - fsp_upd = &config_data.fsp_upd; - - /* Copy default data from Flash */ - memcpy(fsp_upd, (void *)(fsp_hdr->img_base + fsp_vpd->upd_offset), - sizeof(struct upd_region)); - - /* Verify the UPD data region is valid */ - assert(fsp_upd->terminator == UPD_TERMINATOR); -#endif - - memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf)); - - /* Override any configuration if required */ - update_fsp_configs(&config_data, &rt_buf); - - memset(¶ms, 0, sizeof(struct fsp_init_params)); - params.nvs_buf = nvs_buf; - params.rt_buf = (struct fspinit_rtbuf *)&rt_buf; - params.continuation = (fsp_continuation_f)asm_continuation; - - init = (fsp_init_f)(fsp_hdr->img_base + fsp_hdr->fsp_init); - params_ptr = ¶ms; - - post_code(POST_PRE_MRC); - - /* Load GDT for FSP */ - setup_fsp_gdt(); - - /* - * Use ASM code to ensure the register value in EAX & EDX - * will be passed into fsp_continue - */ - asm volatile ( - "pushl %0;" - "call *%%eax;" - ".global asm_continuation;" - "asm_continuation:;" - "movl 4(%%esp), %%eax;" /* status */ - "movl 8(%%esp), %%edx;" /* hob_list */ - "jmp fsp_continue;" - : : "m"(params_ptr), "a"(init) - ); - - /* - * Should never get here. - * Control will continue from fsp_continue. - * This line below is to prevent the compiler from optimizing - * structure intialization. - * - * DO NOT REMOVE! - */ - init(¶ms); -} - -u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase) -{ - fsp_notify_f notify; - struct fsp_notify_params params; - struct fsp_notify_params *params_ptr; - u32 status; - - if (!fsp_hdr) - fsp_hdr = (struct fsp_header *)find_fsp_header(); - - if (fsp_hdr == NULL) { - /* No valid FSP info header */ - panic("Invalid FSP header"); - } - - notify = (fsp_notify_f)(fsp_hdr->img_base + fsp_hdr->fsp_notify); - params.phase = phase; - params_ptr = ¶ms; - - /* - * Use ASM code to ensure correct parameter is on the stack for - * FspNotify as U-Boot is using different ABI from FSP - */ - asm volatile ( - "pushl %1;" /* push notify phase */ - "call *%%eax;" /* call FspNotify */ - "addl $4, %%esp;" /* clean up the stack */ - : "=a"(status) : "m"(params_ptr), "a"(notify), "m"(*params_ptr) - ); - - return status; -} - -u32 fsp_get_usable_lowmem_top(const void *hob_list) -{ - const struct hob_header *hdr; - struct hob_res_desc *res_desc; - phys_addr_t phys_start; - u32 top; -#ifdef CONFIG_FSP_BROKEN_HOB - struct hob_mem_alloc *res_mem; - phys_addr_t mem_base = 0; -#endif - - /* Get the HOB list for processing */ - hdr = hob_list; - - /* * Collect memory ranges */ - top = FSP_LOWMEM_BASE; - while (!end_of_hob(hdr)) { - if (hdr->type == HOB_TYPE_RES_DESC) { - res_desc = (struct hob_res_desc *)hdr; - if (res_desc->type == RES_SYS_MEM) { - phys_start = res_desc->phys_start; - /* Need memory above 1MB to be collected here */ - if (phys_start >= FSP_LOWMEM_BASE && - phys_start < (phys_addr_t)FSP_HIGHMEM_BASE) - top += (u32)(res_desc->len); - } - } - -#ifdef CONFIG_FSP_BROKEN_HOB - /* - * Find out the lowest memory base address allocated by FSP - * for the boot service data - */ - if (hdr->type == HOB_TYPE_MEM_ALLOC) { - res_mem = (struct hob_mem_alloc *)hdr; - if (!mem_base) - mem_base = res_mem->mem_base; - if (res_mem->mem_base < mem_base) - mem_base = res_mem->mem_base; - } -#endif - - hdr = get_next_hob(hdr); - } - -#ifdef CONFIG_FSP_BROKEN_HOB - /* - * Check whether the memory top address is below the FSP HOB list. - * If not, use the lowest memory base address allocated by FSP as - * the memory top address. This is to prevent U-Boot relocation - * overwrites the important boot service data which is used by FSP, - * otherwise the subsequent call to fsp_notify() will fail. - */ - if (top > (u32)hob_list) { - debug("Adjust memory top address due to a buggy FSP\n"); - top = (u32)mem_base; - } -#endif - - return top; -} - -u64 fsp_get_usable_highmem_top(const void *hob_list) -{ - const struct hob_header *hdr; - struct hob_res_desc *res_desc; - phys_addr_t phys_start; - u64 top; - - /* Get the HOB list for processing */ - hdr = hob_list; - - /* Collect memory ranges */ - top = FSP_HIGHMEM_BASE; - while (!end_of_hob(hdr)) { - if (hdr->type == HOB_TYPE_RES_DESC) { - res_desc = (struct hob_res_desc *)hdr; - if (res_desc->type == RES_SYS_MEM) { - phys_start = res_desc->phys_start; - /* Need memory above 4GB to be collected here */ - if (phys_start >= (phys_addr_t)FSP_HIGHMEM_BASE) - top += (u32)(res_desc->len); - } - } - hdr = get_next_hob(hdr); - } - - return top; -} - -u64 fsp_get_reserved_mem_from_guid(const void *hob_list, u64 *len, - const efi_guid_t *guid) -{ - const struct hob_header *hdr; - struct hob_res_desc *res_desc; - - /* Get the HOB list for processing */ - hdr = hob_list; - - /* Collect memory ranges */ - while (!end_of_hob(hdr)) { - if (hdr->type == HOB_TYPE_RES_DESC) { - res_desc = (struct hob_res_desc *)hdr; - if (res_desc->type == RES_MEM_RESERVED) { - if (!guidcmp(&res_desc->owner, guid)) { - if (len) - *len = (u32)(res_desc->len); - - return (u64)(res_desc->phys_start); - } - } - } - hdr = get_next_hob(hdr); - } - - return 0; -} - -u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len) -{ - const efi_guid_t guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID; - u64 length; - u32 base; - - base = (u32)fsp_get_reserved_mem_from_guid(hob_list, - &length, &guid); - if ((len != 0) && (base != 0)) - *len = (u32)length; - - return base; -} - -u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len) -{ - const efi_guid_t guid = FSP_HOB_RESOURCE_OWNER_TSEG_GUID; - u64 length; - u32 base; - - base = (u32)fsp_get_reserved_mem_from_guid(hob_list, - &length, &guid); - if ((len != 0) && (base != 0)) - *len = (u32)length; - - return base; -} - -void *fsp_get_nvs_data(const void *hob_list, u32 *len) -{ - const efi_guid_t guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID; - - return hob_get_guid_hob_data(hob_list, len, &guid); -} - -void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len) -{ - const efi_guid_t guid = FSP_BOOTLOADER_TEMP_MEM_HOB_GUID; - - return hob_get_guid_hob_data(hob_list, len, &guid); -} - -void *fsp_get_graphics_info(const void *hob_list, u32 *len) -{ - const efi_guid_t guid = FSP_GRAPHICS_INFO_HOB_GUID; - - return hob_get_guid_hob_data(hob_list, len, &guid); -} diff --git a/arch/x86/lib/fsp1/Makefile b/arch/x86/lib/fsp1/Makefile new file mode 100644 index 0000000000..870de71bd7 --- /dev/null +++ b/arch/x86/lib/fsp1/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2015 Google, Inc + +obj-y += fsp_car.o +obj-y += fsp_common.o +obj-y += fsp_dram.o +obj-$(CONFIG_VIDEO_FSP) += fsp_graphics.o +obj-y += fsp_support.o diff --git a/arch/x86/lib/fsp1/fsp_car.S b/arch/x86/lib/fsp1/fsp_car.S new file mode 100644 index 0000000000..8c54cea3db --- /dev/null +++ b/arch/x86/lib/fsp1/fsp_car.S @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014, Bin Meng + */ + +#include +#include + +.globl car_init +car_init: + /* + * Note: ebp holds the BIST value (built-in self test) so far, but ebp + * will be destroyed through the FSP call, thus we have to test the + * BIST value here before we call into FSP. + */ + test %ebp, %ebp + jz car_init_start + post_code(POST_BIST_FAILURE) + jmp die + +car_init_start: + post_code(POST_CAR_START) + lea find_fsp_header_romstack, %esp + jmp find_fsp_header + +find_fsp_header_ret: + /* EAX points to FSP_INFO_HEADER */ + mov %eax, %ebp + + /* sanity test */ + cmp $CONFIG_FSP_ADDR, %eax + jb die + + /* calculate TempRamInitEntry address */ + mov 0x30(%ebp), %eax + add 0x1c(%ebp), %eax + + /* call FSP TempRamInitEntry to setup temporary stack */ + lea temp_ram_init_romstack, %esp + jmp *%eax + +temp_ram_init_ret: + addl $4, %esp + cmp $0, %eax + jnz car_init_fail + + post_code(POST_CAR_CPU_CACHE) + + /* + * The FSP TempRamInit initializes the ecx and edx registers to + * point to a temporary but writable memory range (Cache-As-RAM). + * ecx: the start of this temporary memory range, + * edx: the end of this range. + */ + + /* stack grows down from top of CAR */ + movl %edx, %esp + subl $4, %esp + + xor %esi, %esi + jmp car_init_done + +.global fsp_init_done +fsp_init_done: + /* + * We come here from fsp_continue() with eax pointing to the HOB list. + * Save eax to esi temporarily. + */ + movl %eax, %esi + +car_init_done: + /* + * Re-initialize the ebp (BIST) to zero, as we already reach here + * which means we passed BIST testing before. + */ + xorl %ebp, %ebp + jmp car_init_ret + +car_init_fail: + post_code(POST_CAR_FAILURE) + +die: + hlt + jmp die + hlt + + /* + * The function call before CAR initialization is tricky. It cannot + * be called using the 'call' instruction but only the 'jmp' with + * the help of a handcrafted stack in the ROM. The stack needs to + * contain the function return address as well as the parameters. + */ + .balign 4 +find_fsp_header_romstack: + .long find_fsp_header_ret + + .balign 4 +temp_ram_init_romstack: + .long temp_ram_init_ret + .long temp_ram_init_params +temp_ram_init_params: +_dt_ucode_base_size: + /* These next two fields are filled in by binman */ +.globl ucode_base +ucode_base: /* Declared in microcode.h */ + .long 0 /* microcode base */ +.globl ucode_size +ucode_size: /* Declared in microcode.h */ + .long 0 /* microcode size */ + .long CONFIG_SYS_MONITOR_BASE /* code region base */ + .long CONFIG_SYS_MONITOR_LEN /* code region size */ diff --git a/arch/x86/lib/fsp1/fsp_common.c b/arch/x86/lib/fsp1/fsp_common.c new file mode 100644 index 0000000000..591eef7b81 --- /dev/null +++ b/arch/x86/lib/fsp1/fsp_common.c @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2014, Bin Meng + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkcpu(void) +{ + return 0; +} + +int print_cpuinfo(void) +{ + post_code(POST_CPU_INFO); + return default_print_cpuinfo(); +} + +int fsp_init_phase_pci(void) +{ + u32 status; + + /* call into FspNotify */ + debug("Calling into FSP (notify phase INIT_PHASE_PCI): "); + status = fsp_notify(NULL, INIT_PHASE_PCI); + if (status) + debug("fail, error code %x\n", status); + else + debug("OK\n"); + + return status ? -EPERM : 0; +} + +void board_final_cleanup(void) +{ + u32 status; + + /* call into FspNotify */ + debug("Calling into FSP (notify phase INIT_PHASE_BOOT): "); + status = fsp_notify(NULL, INIT_PHASE_BOOT); + if (status) + debug("fail, error code %x\n", status); + else + debug("OK\n"); + + return; +} + +static __maybe_unused void *fsp_prepare_mrc_cache(void) +{ + struct mrc_data_container *cache; + struct mrc_region entry; + int ret; + + ret = mrccache_get_region(NULL, &entry); + if (ret) + return NULL; + + cache = mrccache_find_current(&entry); + if (!cache) + return NULL; + + debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__, + cache->data, cache->data_size, cache->checksum); + + return cache->data; +} + +#ifdef CONFIG_HAVE_ACPI_RESUME +int fsp_save_s3_stack(void) +{ + struct udevice *dev; + int ret; + + if (gd->arch.prev_sleep_state == ACPI_S3) + return 0; + + ret = uclass_get_device(UCLASS_RTC, 0, &dev); + if (ret) { + debug("Cannot find RTC: err=%d\n", ret); + return -ENODEV; + } + + /* Save the stack address to CMOS */ + ret = rtc_write32(dev, CMOS_FSP_STACK_ADDR, gd->start_addr_sp); + if (ret) { + debug("Save stack address to CMOS: err=%d\n", ret); + return -EIO; + } + + return 0; +} +#endif + +int arch_fsp_init(void) +{ + void *nvs; + int stack = CONFIG_FSP_TEMP_RAM_ADDR; + int boot_mode = BOOT_FULL_CONFIG; +#ifdef CONFIG_HAVE_ACPI_RESUME + int prev_sleep_state = chipset_prev_sleep_state(); + gd->arch.prev_sleep_state = prev_sleep_state; +#endif + + if (!gd->arch.hob_list) { +#ifdef CONFIG_ENABLE_MRC_CACHE + nvs = fsp_prepare_mrc_cache(); +#else + nvs = NULL; +#endif + +#ifdef CONFIG_HAVE_ACPI_RESUME + if (prev_sleep_state == ACPI_S3) { + if (nvs == NULL) { + /* If waking from S3 and no cache then */ + debug("No MRC cache found in S3 resume path\n"); + post_code(POST_RESUME_FAILURE); + /* Clear Sleep Type */ + chipset_clear_sleep_state(); + /* Reboot */ + debug("Rebooting..\n"); + outb(SYS_RST | RST_CPU, IO_PORT_RESET); + /* Should not reach here.. */ + panic("Reboot System"); + } + + /* + * DM is not available yet at this point, hence call + * CMOS access library which does not depend on DM. + */ + stack = cmos_read32(CMOS_FSP_STACK_ADDR); + boot_mode = BOOT_ON_S3_RESUME; + } +#endif + /* + * The first time we enter here, call fsp_init(). + * Note the execution does not return to this function, + * instead it jumps to fsp_continue(). + */ + fsp_init(stack, boot_mode, nvs); + } else { + /* + * The second time we enter here, adjust the size of malloc() + * pool before relocation. Given gd->malloc_base was adjusted + * after the call to board_init_f_init_reserve() in arch/x86/ + * cpu/start.S, we should fix up gd->malloc_limit here. + */ + gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN; + } + + return 0; +} diff --git a/arch/x86/lib/fsp1/fsp_dram.c b/arch/x86/lib/fsp1/fsp_dram.c new file mode 100644 index 0000000000..3bf65b495c --- /dev/null +++ b/arch/x86/lib/fsp1/fsp_dram.c @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2014, Bin Meng + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + phys_size_t ram_size = 0; + const struct hob_header *hdr; + struct hob_res_desc *res_desc; + + hdr = gd->arch.hob_list; + while (!end_of_hob(hdr)) { + if (hdr->type == HOB_TYPE_RES_DESC) { + res_desc = (struct hob_res_desc *)hdr; + if (res_desc->type == RES_SYS_MEM || + res_desc->type == RES_MEM_RESERVED) { + ram_size += res_desc->len; + } + } + hdr = get_next_hob(hdr); + } + + gd->ram_size = ram_size; + post_code(POST_DRAM); + +#ifdef CONFIG_ENABLE_MRC_CACHE + gd->arch.mrc_output = fsp_get_nvs_data(gd->arch.hob_list, + &gd->arch.mrc_output_len); +#endif + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = gd->ram_size; + + return 0; +} + +/* + * This function looks for the highest region of memory lower than 4GB which + * has enough space for U-Boot where U-Boot is aligned on a page boundary. + * It overrides the default implementation found elsewhere which simply + * picks the end of ram, wherever that may be. The location of the stack, + * the relocation address, and how far U-Boot is moved by relocation are + * set in the global data structure. + */ +ulong board_get_usable_ram_top(ulong total_size) +{ + return fsp_get_usable_lowmem_top(gd->arch.hob_list); +} + +unsigned int install_e820_map(unsigned int max_entries, + struct e820_entry *entries) +{ + unsigned int num_entries = 0; + const struct hob_header *hdr; + struct hob_res_desc *res_desc; + + hdr = gd->arch.hob_list; + + while (!end_of_hob(hdr)) { + if (hdr->type == HOB_TYPE_RES_DESC) { + res_desc = (struct hob_res_desc *)hdr; + entries[num_entries].addr = res_desc->phys_start; + entries[num_entries].size = res_desc->len; + + if (res_desc->type == RES_SYS_MEM) + entries[num_entries].type = E820_RAM; + else if (res_desc->type == RES_MEM_RESERVED) + entries[num_entries].type = E820_RESERVED; + + num_entries++; + } + hdr = get_next_hob(hdr); + } + + /* Mark PCIe ECAM address range as reserved */ + entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE; + entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE; + entries[num_entries].type = E820_RESERVED; + num_entries++; + +#ifdef CONFIG_HAVE_ACPI_RESUME + /* + * Everything between U-Boot's stack and ram top needs to be + * reserved in order for ACPI S3 resume to work. + */ + entries[num_entries].addr = gd->start_addr_sp - CONFIG_STACK_SIZE; + entries[num_entries].size = gd->ram_top - gd->start_addr_sp + \ + CONFIG_STACK_SIZE; + entries[num_entries].type = E820_RESERVED; + num_entries++; +#endif + + return num_entries; +} diff --git a/arch/x86/lib/fsp1/fsp_graphics.c b/arch/x86/lib/fsp1/fsp_graphics.c new file mode 100644 index 0000000000..52e71334f9 --- /dev/null +++ b/arch/x86/lib/fsp1/fsp_graphics.c @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017, Bin Meng + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct pixel { + u8 pos; + u8 size; +}; + +static const struct fsp_framebuffer { + struct pixel red; + struct pixel green; + struct pixel blue; + struct pixel rsvd; +} fsp_framebuffer_format_map[] = { + [pixel_rgbx_8bpc] = { {0, 8}, {8, 8}, {16, 8}, {24, 8} }, + [pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} }, +}; + +static int save_vesa_mode(struct vesa_mode_info *vesa) +{ + const struct hob_graphics_info *ginfo; + const struct fsp_framebuffer *fbinfo; + + ginfo = fsp_get_graphics_info(gd->arch.hob_list, NULL); + + /* + * If there is no graphics info structure, bail out and keep + * running on the serial console. + * + * Note: on some platforms (eg: Braswell), the FSP will not produce + * the graphics info HOB unless you plug some cables to the display + * interface (eg: HDMI) on the board. + */ + if (!ginfo) { + debug("FSP graphics hand-off block not found\n"); + return -ENXIO; + } + + vesa->x_resolution = ginfo->width; + vesa->y_resolution = ginfo->height; + vesa->bits_per_pixel = 32; + vesa->bytes_per_scanline = ginfo->pixels_per_scanline * 4; + vesa->phys_base_ptr = ginfo->fb_base; + + if (ginfo->pixel_format >= pixel_bitmask) { + debug("FSP set unknown framebuffer format: %d\n", + ginfo->pixel_format); + return -EINVAL; + } + fbinfo = &fsp_framebuffer_format_map[ginfo->pixel_format]; + vesa->red_mask_size = fbinfo->red.size; + vesa->red_mask_pos = fbinfo->red.pos; + vesa->green_mask_size = fbinfo->green.size; + vesa->green_mask_pos = fbinfo->green.pos; + vesa->blue_mask_size = fbinfo->blue.size; + vesa->blue_mask_pos = fbinfo->blue.pos; + vesa->reserved_mask_size = fbinfo->rsvd.size; + vesa->reserved_mask_pos = fbinfo->rsvd.pos; + + return 0; +} + +static int fsp_video_probe(struct udevice *dev) +{ + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + struct vesa_mode_info *vesa = &mode_info.vesa; + int ret; + + printf("Video: "); + + /* Initialize vesa_mode_info structure */ + ret = save_vesa_mode(vesa); + if (ret) + goto err; + + /* + * The framebuffer base address in the FSP graphics info HOB reflects + * the value assigned by the FSP. After PCI enumeration the framebuffer + * base address may be relocated. Let's get the updated one from device. + * + * For IGD, it seems to be always on BAR2. + */ + vesa->phys_base_ptr = dm_pci_read_bar32(dev, 2); + + ret = vbe_setup_video_priv(vesa, uc_priv, plat); + if (ret) + goto err; + + printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize, + vesa->bits_per_pixel); + + return 0; + +err: + printf("No video mode configured in FSP!\n"); + return ret; +} + +static const struct udevice_id fsp_video_ids[] = { + { .compatible = "fsp-fb" }, + { } +}; + +U_BOOT_DRIVER(fsp_video) = { + .name = "fsp_video", + .id = UCLASS_VIDEO, + .of_match = fsp_video_ids, + .probe = fsp_video_probe, +}; + +static struct pci_device_id fsp_video_supported[] = { + { PCI_DEVICE_CLASS(PCI_CLASS_DISPLAY_VGA << 8, 0xffff00) }, + { }, +}; + +U_BOOT_PCI_DEVICE(fsp_video, fsp_video_supported); diff --git a/arch/x86/lib/fsp1/fsp_support.c b/arch/x86/lib/fsp1/fsp_support.c new file mode 100644 index 0000000000..019a42f53f --- /dev/null +++ b/arch/x86/lib/fsp1/fsp_support.c @@ -0,0 +1,366 @@ +// SPDX-License-Identifier: Intel +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + */ + +#include +#include +#include + +struct fsp_header *__attribute__((optimize("O0"))) find_fsp_header(void) +{ + /* + * This function may be called before the a stack is established, + * so special care must be taken. First, it cannot declare any local + * variable using stack. Only register variable can be used here. + * Secondly, some compiler version will add prolog or epilog code + * for the C function. If so the function call may not work before + * stack is ready. + * + * GCC 4.8.1 has been verified to be working for the following codes. + */ + volatile register u8 *fsp asm("eax"); + + /* Initalize the FSP base */ + fsp = (u8 *)CONFIG_FSP_ADDR; + + /* Check the FV signature, _FVH */ + if (((struct fv_header *)fsp)->sign == EFI_FVH_SIGNATURE) { + /* Go to the end of the FV header and align the address */ + fsp += ((struct fv_header *)fsp)->ext_hdr_off; + fsp += ((struct fv_ext_header *)fsp)->ext_hdr_size; + fsp = (u8 *)(((u32)fsp + 7) & 0xFFFFFFF8); + } else { + fsp = 0; + } + + /* Check the FFS GUID */ + if (fsp && + ((struct ffs_file_header *)fsp)->name.b[0] == FSP_GUID_BYTE0 && + ((struct ffs_file_header *)fsp)->name.b[1] == FSP_GUID_BYTE1 && + ((struct ffs_file_header *)fsp)->name.b[2] == FSP_GUID_BYTE2 && + ((struct ffs_file_header *)fsp)->name.b[3] == FSP_GUID_BYTE3 && + ((struct ffs_file_header *)fsp)->name.b[4] == FSP_GUID_BYTE4 && + ((struct ffs_file_header *)fsp)->name.b[5] == FSP_GUID_BYTE5 && + ((struct ffs_file_header *)fsp)->name.b[6] == FSP_GUID_BYTE6 && + ((struct ffs_file_header *)fsp)->name.b[7] == FSP_GUID_BYTE7 && + ((struct ffs_file_header *)fsp)->name.b[8] == FSP_GUID_BYTE8 && + ((struct ffs_file_header *)fsp)->name.b[9] == FSP_GUID_BYTE9 && + ((struct ffs_file_header *)fsp)->name.b[10] == FSP_GUID_BYTE10 && + ((struct ffs_file_header *)fsp)->name.b[11] == FSP_GUID_BYTE11 && + ((struct ffs_file_header *)fsp)->name.b[12] == FSP_GUID_BYTE12 && + ((struct ffs_file_header *)fsp)->name.b[13] == FSP_GUID_BYTE13 && + ((struct ffs_file_header *)fsp)->name.b[14] == FSP_GUID_BYTE14 && + ((struct ffs_file_header *)fsp)->name.b[15] == FSP_GUID_BYTE15) { + /* Add the FFS header size to find the raw section header */ + fsp += sizeof(struct ffs_file_header); + } else { + fsp = 0; + } + + if (fsp && + ((struct raw_section *)fsp)->type == EFI_SECTION_RAW) { + /* Add the raw section header size to find the FSP header */ + fsp += sizeof(struct raw_section); + } else { + fsp = 0; + } + + return (struct fsp_header *)fsp; +} + +void fsp_continue(u32 status, void *hob_list) +{ + post_code(POST_MRC); + + assert(status == 0); + + /* The boot loader main function entry */ + fsp_init_done(hob_list); +} + +void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) +{ + struct fsp_config_data config_data; + fsp_init_f init; + struct fsp_init_params params; + struct fspinit_rtbuf rt_buf; + struct fsp_header *fsp_hdr; + struct fsp_init_params *params_ptr; +#ifdef CONFIG_FSP_USE_UPD + struct vpd_region *fsp_vpd; + struct upd_region *fsp_upd; +#endif + + fsp_hdr = find_fsp_header(); + if (fsp_hdr == NULL) { + /* No valid FSP info header was found */ + panic("Invalid FSP header"); + } + + config_data.common.fsp_hdr = fsp_hdr; + config_data.common.stack_top = stack_top; + config_data.common.boot_mode = boot_mode; + +#ifdef CONFIG_FSP_USE_UPD + /* Get VPD region start */ + fsp_vpd = (struct vpd_region *)(fsp_hdr->img_base + + fsp_hdr->cfg_region_off); + + /* Verify the VPD data region is valid */ + assert(fsp_vpd->sign == VPD_IMAGE_ID); + + fsp_upd = &config_data.fsp_upd; + + /* Copy default data from Flash */ + memcpy(fsp_upd, (void *)(fsp_hdr->img_base + fsp_vpd->upd_offset), + sizeof(struct upd_region)); + + /* Verify the UPD data region is valid */ + assert(fsp_upd->terminator == UPD_TERMINATOR); +#endif + + memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf)); + + /* Override any configuration if required */ + update_fsp_configs(&config_data, &rt_buf); + + memset(¶ms, 0, sizeof(struct fsp_init_params)); + params.nvs_buf = nvs_buf; + params.rt_buf = (struct fspinit_rtbuf *)&rt_buf; + params.continuation = (fsp_continuation_f)asm_continuation; + + init = (fsp_init_f)(fsp_hdr->img_base + fsp_hdr->fsp_init); + params_ptr = ¶ms; + + post_code(POST_PRE_MRC); + + /* Load GDT for FSP */ + setup_fsp_gdt(); + + /* + * Use ASM code to ensure the register value in EAX & EDX + * will be passed into fsp_continue + */ + asm volatile ( + "pushl %0;" + "call *%%eax;" + ".global asm_continuation;" + "asm_continuation:;" + "movl 4(%%esp), %%eax;" /* status */ + "movl 8(%%esp), %%edx;" /* hob_list */ + "jmp fsp_continue;" + : : "m"(params_ptr), "a"(init) + ); + + /* + * Should never get here. + * Control will continue from fsp_continue. + * This line below is to prevent the compiler from optimizing + * structure intialization. + * + * DO NOT REMOVE! + */ + init(¶ms); +} + +u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase) +{ + fsp_notify_f notify; + struct fsp_notify_params params; + struct fsp_notify_params *params_ptr; + u32 status; + + if (!fsp_hdr) + fsp_hdr = (struct fsp_header *)find_fsp_header(); + + if (fsp_hdr == NULL) { + /* No valid FSP info header */ + panic("Invalid FSP header"); + } + + notify = (fsp_notify_f)(fsp_hdr->img_base + fsp_hdr->fsp_notify); + params.phase = phase; + params_ptr = ¶ms; + + /* + * Use ASM code to ensure correct parameter is on the stack for + * FspNotify as U-Boot is using different ABI from FSP + */ + asm volatile ( + "pushl %1;" /* push notify phase */ + "call *%%eax;" /* call FspNotify */ + "addl $4, %%esp;" /* clean up the stack */ + : "=a"(status) : "m"(params_ptr), "a"(notify), "m"(*params_ptr) + ); + + return status; +} + +u32 fsp_get_usable_lowmem_top(const void *hob_list) +{ + const struct hob_header *hdr; + struct hob_res_desc *res_desc; + phys_addr_t phys_start; + u32 top; +#ifdef CONFIG_FSP_BROKEN_HOB + struct hob_mem_alloc *res_mem; + phys_addr_t mem_base = 0; +#endif + + /* Get the HOB list for processing */ + hdr = hob_list; + + /* * Collect memory ranges */ + top = FSP_LOWMEM_BASE; + while (!end_of_hob(hdr)) { + if (hdr->type == HOB_TYPE_RES_DESC) { + res_desc = (struct hob_res_desc *)hdr; + if (res_desc->type == RES_SYS_MEM) { + phys_start = res_desc->phys_start; + /* Need memory above 1MB to be collected here */ + if (phys_start >= FSP_LOWMEM_BASE && + phys_start < (phys_addr_t)FSP_HIGHMEM_BASE) + top += (u32)(res_desc->len); + } + } + +#ifdef CONFIG_FSP_BROKEN_HOB + /* + * Find out the lowest memory base address allocated by FSP + * for the boot service data + */ + if (hdr->type == HOB_TYPE_MEM_ALLOC) { + res_mem = (struct hob_mem_alloc *)hdr; + if (!mem_base) + mem_base = res_mem->mem_base; + if (res_mem->mem_base < mem_base) + mem_base = res_mem->mem_base; + } +#endif + + hdr = get_next_hob(hdr); + } + +#ifdef CONFIG_FSP_BROKEN_HOB + /* + * Check whether the memory top address is below the FSP HOB list. + * If not, use the lowest memory base address allocated by FSP as + * the memory top address. This is to prevent U-Boot relocation + * overwrites the important boot service data which is used by FSP, + * otherwise the subsequent call to fsp_notify() will fail. + */ + if (top > (u32)hob_list) { + debug("Adjust memory top address due to a buggy FSP\n"); + top = (u32)mem_base; + } +#endif + + return top; +} + +u64 fsp_get_usable_highmem_top(const void *hob_list) +{ + const struct hob_header *hdr; + struct hob_res_desc *res_desc; + phys_addr_t phys_start; + u64 top; + + /* Get the HOB list for processing */ + hdr = hob_list; + + /* Collect memory ranges */ + top = FSP_HIGHMEM_BASE; + while (!end_of_hob(hdr)) { + if (hdr->type == HOB_TYPE_RES_DESC) { + res_desc = (struct hob_res_desc *)hdr; + if (res_desc->type == RES_SYS_MEM) { + phys_start = res_desc->phys_start; + /* Need memory above 4GB to be collected here */ + if (phys_start >= (phys_addr_t)FSP_HIGHMEM_BASE) + top += (u32)(res_desc->len); + } + } + hdr = get_next_hob(hdr); + } + + return top; +} + +u64 fsp_get_reserved_mem_from_guid(const void *hob_list, u64 *len, + const efi_guid_t *guid) +{ + const struct hob_header *hdr; + struct hob_res_desc *res_desc; + + /* Get the HOB list for processing */ + hdr = hob_list; + + /* Collect memory ranges */ + while (!end_of_hob(hdr)) { + if (hdr->type == HOB_TYPE_RES_DESC) { + res_desc = (struct hob_res_desc *)hdr; + if (res_desc->type == RES_MEM_RESERVED) { + if (!guidcmp(&res_desc->owner, guid)) { + if (len) + *len = (u32)(res_desc->len); + + return (u64)(res_desc->phys_start); + } + } + } + hdr = get_next_hob(hdr); + } + + return 0; +} + +u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len) +{ + const efi_guid_t guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID; + u64 length; + u32 base; + + base = (u32)fsp_get_reserved_mem_from_guid(hob_list, + &length, &guid); + if ((len != 0) && (base != 0)) + *len = (u32)length; + + return base; +} + +u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len) +{ + const efi_guid_t guid = FSP_HOB_RESOURCE_OWNER_TSEG_GUID; + u64 length; + u32 base; + + base = (u32)fsp_get_reserved_mem_from_guid(hob_list, + &length, &guid); + if ((len != 0) && (base != 0)) + *len = (u32)length; + + return base; +} + +void *fsp_get_nvs_data(const void *hob_list, u32 *len) +{ + const efi_guid_t guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID; + + return hob_get_guid_hob_data(hob_list, len, &guid); +} + +void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len) +{ + const efi_guid_t guid = FSP_BOOTLOADER_TEMP_MEM_HOB_GUID; + + return hob_get_guid_hob_data(hob_list, len, &guid); +} + +void *fsp_get_graphics_info(const void *hob_list, u32 *len) +{ + const efi_guid_t guid = FSP_GRAPHICS_INFO_HOB_GUID; + + return hob_get_guid_hob_data(hob_list, len, &guid); +} -- cgit From 6e93c64117bb8d04586bf095a8af75c25c2a7392 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:00:12 -0600 Subject: x86: Move fsp_azalia.h to the generic fsp directory This header file is the same for FSP v1 and v2. Move it into the general fsp directory. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng [bmeng: remove forward declarations in fsp_support.h] Signed-off-by: Bin Meng --- arch/x86/include/asm/fsp/fsp_azalia.h | 38 +++++++++++++++++++++++++++++++++ arch/x86/include/asm/fsp1/fsp_azalia.h | 38 --------------------------------- arch/x86/include/asm/fsp1/fsp_support.h | 3 +-- 3 files changed, 39 insertions(+), 40 deletions(-) create mode 100644 arch/x86/include/asm/fsp/fsp_azalia.h delete mode 100644 arch/x86/include/asm/fsp1/fsp_azalia.h (limited to 'arch/x86') diff --git a/arch/x86/include/asm/fsp/fsp_azalia.h b/arch/x86/include/asm/fsp/fsp_azalia.h new file mode 100644 index 0000000000..e59180bdae --- /dev/null +++ b/arch/x86/include/asm/fsp/fsp_azalia.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2015, Google, Inc + */ + +#ifndef _FSP_AZALIA_H_ +#define _FSP_AZALIA_H_ + +struct __packed azalia_verb_table_header { + u32 vendor_device_id; + u16 sub_system_id; + u8 revision_id; /* 0xff applies to all steppings */ + u8 front_panel_support; + u16 number_of_rear_jacks; + u16 number_of_front_jacks; +}; + +struct __packed azalia_verb_table { + struct azalia_verb_table_header header; + const u32 *data; +}; + +struct __packed azalia_config { + u8 pme_enable:1; + u8 docking_supported:1; + u8 docking_attached:1; + u8 hdmi_codec_enable:1; + u8 azalia_v_ci_enable:1; + u8 rsvdbits:3; + /* number of verb tables provided by platform */ + u8 verb_table_num; + const struct azalia_verb_table *verb_table; + /* delay timer after azalia reset */ + u16 reset_wait_timer_ms; +}; + +#endif diff --git a/arch/x86/include/asm/fsp1/fsp_azalia.h b/arch/x86/include/asm/fsp1/fsp_azalia.h deleted file mode 100644 index e59180bdae..0000000000 --- a/arch/x86/include/asm/fsp1/fsp_azalia.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: Intel */ -/* - * Copyright (C) 2013, Intel Corporation - * Copyright (C) 2015, Google, Inc - */ - -#ifndef _FSP_AZALIA_H_ -#define _FSP_AZALIA_H_ - -struct __packed azalia_verb_table_header { - u32 vendor_device_id; - u16 sub_system_id; - u8 revision_id; /* 0xff applies to all steppings */ - u8 front_panel_support; - u16 number_of_rear_jacks; - u16 number_of_front_jacks; -}; - -struct __packed azalia_verb_table { - struct azalia_verb_table_header header; - const u32 *data; -}; - -struct __packed azalia_config { - u8 pme_enable:1; - u8 docking_supported:1; - u8 docking_attached:1; - u8 hdmi_codec_enable:1; - u8 azalia_v_ci_enable:1; - u8 rsvdbits:3; - /* number of verb tables provided by platform */ - u8 verb_table_num; - const struct azalia_verb_table *verb_table; - /* delay timer after azalia reset */ - u16 reset_wait_timer_ms; -}; - -#endif diff --git a/arch/x86/include/asm/fsp1/fsp_support.h b/arch/x86/include/asm/fsp1/fsp_support.h index 7b92392a27..b0c36a41fe 100644 --- a/arch/x86/include/asm/fsp1/fsp_support.h +++ b/arch/x86/include/asm/fsp1/fsp_support.h @@ -14,7 +14,7 @@ #include "fsp_api.h" #include "fsp_infoheader.h" #include "fsp_bootmode.h" -#include "fsp_azalia.h" +#include #include #include @@ -22,7 +22,6 @@ #define FSP_HIGHMEM_BASE 0x100000000ULL #define UPD_TERMINATOR 0x55AA - /** * FSP Continuation assembly helper routine * -- cgit From 8cd29798d6a8e3cd3061ba855f6ea2b95ec47afc Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:00:13 -0600 Subject: x86: Create a new fsp_arch.h header At present fsp_support.h includes fsp_vpd.h which is an FPSv1 concept (VPD means Vital Product Data). For FSPv2 only UPD (Updatable Product Data) is used. To avoid mangling header files, put these two includes in a separate header which we can adjust as necessary for FSPv2. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/x86/include/asm/fsp1/fsp_support.h | 3 +-- arch/x86/include/asm/fsp_arch.h | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+), 2 deletions(-) create mode 100644 arch/x86/include/asm/fsp_arch.h (limited to 'arch/x86') diff --git a/arch/x86/include/asm/fsp1/fsp_support.h b/arch/x86/include/asm/fsp1/fsp_support.h index b0c36a41fe..2fa6619c03 100644 --- a/arch/x86/include/asm/fsp1/fsp_support.h +++ b/arch/x86/include/asm/fsp1/fsp_support.h @@ -14,9 +14,8 @@ #include "fsp_api.h" #include "fsp_infoheader.h" #include "fsp_bootmode.h" +#include #include -#include -#include #define FSP_LOWMEM_BASE 0x100000UL #define FSP_HIGHMEM_BASE 0x100000000ULL diff --git a/arch/x86/include/asm/fsp_arch.h b/arch/x86/include/asm/fsp_arch.h new file mode 100644 index 0000000000..fb7f9109f7 --- /dev/null +++ b/arch/x86/include/asm/fsp_arch.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Google LLC + * Written by Simon Glass + * + * Architecture-specific definitions (FSP config and VPD/UPD) + */ + +#ifndef __FSP_ARCH_H__ +#define __FSP_ARCH_H__ + +/* + * Note: use #ifndef __ASSEMBLY__ around any struct definitions or other C code + * since this file can be included from assembly. + */ + +#include +#include + +#endif -- cgit From 8a0b4e2dd7ce8a93ef49bed916e96c569a95ff23 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:00:14 -0600 Subject: x86: Move fsp_api.h inclusion out of fsp_support.h This header file is different for each version of FSP. Move it into the fsp_arch.h header file. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/x86/include/asm/fsp1/fsp_support.h | 1 - arch/x86/include/asm/fsp_arch.h | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/x86') diff --git a/arch/x86/include/asm/fsp1/fsp_support.h b/arch/x86/include/asm/fsp1/fsp_support.h index 2fa6619c03..c75afe9356 100644 --- a/arch/x86/include/asm/fsp1/fsp_support.h +++ b/arch/x86/include/asm/fsp1/fsp_support.h @@ -11,7 +11,6 @@ #include "fsp_hob.h" #include "fsp_fv.h" #include "fsp_ffs.h" -#include "fsp_api.h" #include "fsp_infoheader.h" #include "fsp_bootmode.h" #include diff --git a/arch/x86/include/asm/fsp_arch.h b/arch/x86/include/asm/fsp_arch.h index fb7f9109f7..b223141c44 100644 --- a/arch/x86/include/asm/fsp_arch.h +++ b/arch/x86/include/asm/fsp_arch.h @@ -14,6 +14,7 @@ * since this file can be included from assembly. */ +#include #include #include -- cgit From 2b5560a6bdafe4e1217938b8b772b8f545136dd8 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:00:15 -0600 Subject: x86: Move fsp_types.h to the generic fsp directory This header file is the same for FSP v1 and v2. Move it into the general fsp directory. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/x86/include/asm/fsp/fsp_types.h | 62 +++++++++++++++++++++++++++++++++ arch/x86/include/asm/fsp1/fsp_support.h | 2 +- arch/x86/include/asm/fsp1/fsp_types.h | 62 --------------------------------- 3 files changed, 63 insertions(+), 63 deletions(-) create mode 100644 arch/x86/include/asm/fsp/fsp_types.h delete mode 100644 arch/x86/include/asm/fsp1/fsp_types.h (limited to 'arch/x86') diff --git a/arch/x86/include/asm/fsp/fsp_types.h b/arch/x86/include/asm/fsp/fsp_types.h new file mode 100644 index 0000000000..3d5b17ecf1 --- /dev/null +++ b/arch/x86/include/asm/fsp/fsp_types.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + */ + +#ifndef __FSP_TYPES_H__ +#define __FSP_TYPES_H__ + +/** + * Returns a 16-bit signature built from 2 ASCII characters. + * + * This macro returns a 16-bit value built from the two ASCII characters + * specified by A and B. + * + * @A: The first ASCII character. + * @B: The second ASCII character. + * + * @return: A 16-bit value built from the two ASCII characters specified by + * A and B. + */ +#define SIGNATURE_16(A, B) ((A) | (B << 8)) + +/** + * Returns a 32-bit signature built from 4 ASCII characters. + * + * This macro returns a 32-bit value built from the four ASCII characters + * specified by A, B, C, and D. + * + * @A: The first ASCII character. + * @B: The second ASCII character. + * @C: The third ASCII character. + * @D: The fourth ASCII character. + * + * @return: A 32-bit value built from the two ASCII characters specified by + * A, B, C and D. + */ +#define SIGNATURE_32(A, B, C, D) \ + (SIGNATURE_16(A, B) | (SIGNATURE_16(C, D) << 16)) + +/** + * Returns a 64-bit signature built from 8 ASCII characters. + * + * This macro returns a 64-bit value built from the eight ASCII characters + * specified by A, B, C, D, E, F, G,and H. + * + * @A: The first ASCII character. + * @B: The second ASCII character. + * @C: The third ASCII character. + * @D: The fourth ASCII character. + * @E: The fifth ASCII character. + * @F: The sixth ASCII character. + * @G: The seventh ASCII character. + * @H: The eighth ASCII character. + * + * @return: A 64-bit value built from the two ASCII characters specified by + * A, B, C, D, E, F, G and H. + */ +#define SIGNATURE_64(A, B, C, D, E, F, G, H) \ + (SIGNATURE_32(A, B, C, D) | ((u64)(SIGNATURE_32(E, F, G, H)) << 32)) + +#endif diff --git a/arch/x86/include/asm/fsp1/fsp_support.h b/arch/x86/include/asm/fsp1/fsp_support.h index c75afe9356..e5ec2af83e 100644 --- a/arch/x86/include/asm/fsp1/fsp_support.h +++ b/arch/x86/include/asm/fsp1/fsp_support.h @@ -7,7 +7,7 @@ #ifndef __FSP_SUPPORT_H__ #define __FSP_SUPPORT_H__ -#include "fsp_types.h" +#include #include "fsp_hob.h" #include "fsp_fv.h" #include "fsp_ffs.h" diff --git a/arch/x86/include/asm/fsp1/fsp_types.h b/arch/x86/include/asm/fsp1/fsp_types.h deleted file mode 100644 index 3d5b17ecf1..0000000000 --- a/arch/x86/include/asm/fsp1/fsp_types.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: Intel */ -/* - * Copyright (C) 2013, Intel Corporation - * Copyright (C) 2014, Bin Meng - */ - -#ifndef __FSP_TYPES_H__ -#define __FSP_TYPES_H__ - -/** - * Returns a 16-bit signature built from 2 ASCII characters. - * - * This macro returns a 16-bit value built from the two ASCII characters - * specified by A and B. - * - * @A: The first ASCII character. - * @B: The second ASCII character. - * - * @return: A 16-bit value built from the two ASCII characters specified by - * A and B. - */ -#define SIGNATURE_16(A, B) ((A) | (B << 8)) - -/** - * Returns a 32-bit signature built from 4 ASCII characters. - * - * This macro returns a 32-bit value built from the four ASCII characters - * specified by A, B, C, and D. - * - * @A: The first ASCII character. - * @B: The second ASCII character. - * @C: The third ASCII character. - * @D: The fourth ASCII character. - * - * @return: A 32-bit value built from the two ASCII characters specified by - * A, B, C and D. - */ -#define SIGNATURE_32(A, B, C, D) \ - (SIGNATURE_16(A, B) | (SIGNATURE_16(C, D) << 16)) - -/** - * Returns a 64-bit signature built from 8 ASCII characters. - * - * This macro returns a 64-bit value built from the eight ASCII characters - * specified by A, B, C, D, E, F, G,and H. - * - * @A: The first ASCII character. - * @B: The second ASCII character. - * @C: The third ASCII character. - * @D: The fourth ASCII character. - * @E: The fifth ASCII character. - * @F: The sixth ASCII character. - * @G: The seventh ASCII character. - * @H: The eighth ASCII character. - * - * @return: A 64-bit value built from the two ASCII characters specified by - * A, B, C, D, E, F, G and H. - */ -#define SIGNATURE_64(A, B, C, D, E, F, G, H) \ - (SIGNATURE_32(A, B, C, D) | ((u64)(SIGNATURE_32(E, F, G, H)) << 32)) - -#endif -- cgit From aae5b4613a4b68efee33ac6803440ccc3a18ec55 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:00:16 -0600 Subject: x86: Move fsp_fv.h to the generic fsp directory This header file is the same for FSP v1 and v2. Move it into the general fsp directory. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/x86/include/asm/fsp/fsp_fv.h | 136 ++++++++++++++++++++++++++++++++ arch/x86/include/asm/fsp1/fsp_fv.h | 136 -------------------------------- arch/x86/include/asm/fsp1/fsp_support.h | 2 +- 3 files changed, 137 insertions(+), 137 deletions(-) create mode 100644 arch/x86/include/asm/fsp/fsp_fv.h delete mode 100644 arch/x86/include/asm/fsp1/fsp_fv.h (limited to 'arch/x86') diff --git a/arch/x86/include/asm/fsp/fsp_fv.h b/arch/x86/include/asm/fsp/fsp_fv.h new file mode 100644 index 0000000000..511dfb78b8 --- /dev/null +++ b/arch/x86/include/asm/fsp/fsp_fv.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + */ + +#ifndef __FSP_FV___ +#define __FSP_FV___ + +/* Value of EFI_FV_FILE_ATTRIBUTES */ +#define EFI_FV_FILE_ATTR_ALIGNMENT 0x0000001F +#define EFI_FV_FILE_ATTR_FIXED 0x00000100 +#define EFI_FV_FILE_ATTR_MEMORY_MAPPED 0x00000200 + +/* Attributes bit definitions */ +#define EFI_FVB2_READ_DISABLED_CAP 0x00000001 +#define EFI_FVB2_READ_ENABLED_CAP 0x00000002 +#define EFI_FVB2_READ_STATUS 0x00000004 +#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008 +#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010 +#define EFI_FVB2_WRITE_STATUS 0x00000020 +#define EFI_FVB2_LOCK_CAP 0x00000040 +#define EFI_FVB2_LOCK_STATUS 0x00000080 +#define EFI_FVB2_STICKY_WRITE 0x00000200 +#define EFI_FVB2_MEMORY_MAPPED 0x00000400 +#define EFI_FVB2_ERASE_POLARITY 0x00000800 +#define EFI_FVB2_READ_LOCK_CAP 0x00001000 +#define EFI_FVB2_READ_LOCK_STATUS 0x00002000 +#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000 +#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000 +#define EFI_FVB2_ALIGNMENT 0x001F0000 +#define EFI_FVB2_ALIGNMENT_1 0x00000000 +#define EFI_FVB2_ALIGNMENT_2 0x00010000 +#define EFI_FVB2_ALIGNMENT_4 0x00020000 +#define EFI_FVB2_ALIGNMENT_8 0x00030000 +#define EFI_FVB2_ALIGNMENT_16 0x00040000 +#define EFI_FVB2_ALIGNMENT_32 0x00050000 +#define EFI_FVB2_ALIGNMENT_64 0x00060000 +#define EFI_FVB2_ALIGNMENT_128 0x00070000 +#define EFI_FVB2_ALIGNMENT_256 0x00080000 +#define EFI_FVB2_ALIGNMENT_512 0x00090000 +#define EFI_FVB2_ALIGNMENT_1K 0x000A0000 +#define EFI_FVB2_ALIGNMENT_2K 0x000B0000 +#define EFI_FVB2_ALIGNMENT_4K 0x000C0000 +#define EFI_FVB2_ALIGNMENT_8K 0x000D0000 +#define EFI_FVB2_ALIGNMENT_16K 0x000E0000 +#define EFI_FVB2_ALIGNMENT_32K 0x000F0000 +#define EFI_FVB2_ALIGNMENT_64K 0x00100000 +#define EFI_FVB2_ALIGNMENT_128K 0x00110000 +#define EFI_FVB2_ALIGNMENT_256K 0x00120000 +#define EFI_FVB2_ALIGNMENT_512K 0x00130000 +#define EFI_FVB2_ALIGNMENT_1M 0x00140000 +#define EFI_FVB2_ALIGNMENT_2M 0x00150000 +#define EFI_FVB2_ALIGNMENT_4M 0x00160000 +#define EFI_FVB2_ALIGNMENT_8M 0x00170000 +#define EFI_FVB2_ALIGNMENT_16M 0x00180000 +#define EFI_FVB2_ALIGNMENT_32M 0x00190000 +#define EFI_FVB2_ALIGNMENT_64M 0x001A0000 +#define EFI_FVB2_ALIGNMENT_128M 0x001B0000 +#define EFI_FVB2_ALIGNMENT_256M 0x001C0000 +#define EFI_FVB2_ALIGNMENT_512M 0x001D0000 +#define EFI_FVB2_ALIGNMENT_1G 0x001E0000 +#define EFI_FVB2_ALIGNMENT_2G 0x001F0000 + +struct fv_blkmap_entry { + /* The number of sequential blocks which are of the same size */ + u32 num_blocks; + /* The size of the blocks */ + u32 length; +}; + +/* Describes the features and layout of the firmware volume */ +struct fv_header { + /* + * The first 16 bytes are reserved to allow for the reset vector of + * processors whose reset vector is at address 0. + */ + u8 zero_vec[16]; + /* + * Declares the file system with which the firmware volume + * is formatted. + */ + efi_guid_t fs_guid; + /* + * Length in bytes of the complete firmware volume, including + * the header. + */ + u64 fv_len; + /* Set to EFI_FVH_SIGNATURE */ + u32 sign; + /* + * Declares capabilities and power-on defaults for the firmware + * volume. + */ + u32 attr; + /* Length in bytes of the complete firmware volume header */ + u16 hdr_len; + /* + * A 16-bit checksum of the firmware volume header. + * A valid header sums to zero. + */ + u16 checksum; + /* + * Offset, relative to the start of the header, of the extended + * header (EFI_FIRMWARE_VOLUME_EXT_HEADER) or zero if there is + * no extended header. + */ + u16 ext_hdr_off; + /* This field must always be set to zero */ + u8 reserved[1]; + /* + * Set to 2. Future versions of this specification may define new + * header fields and will increment the Revision field accordingly. + */ + u8 rev; + /* + * An array of run-length encoded FvBlockMapEntry structures. + * The array is terminated with an entry of {0,0}. + */ + struct fv_blkmap_entry block_map[1]; +}; + +#define EFI_FVH_SIGNATURE SIGNATURE_32('_', 'F', 'V', 'H') + +/* Firmware Volume Header Revision definition */ +#define EFI_FVH_REVISION 0x02 + +/* Extension header pointed by ExtHeaderOffset of volume header */ +struct fv_ext_header { + /* firmware volume name */ + efi_guid_t fv_name; + /* Size of the rest of the extension header including this structure */ + u32 ext_hdr_size; +}; + +#endif diff --git a/arch/x86/include/asm/fsp1/fsp_fv.h b/arch/x86/include/asm/fsp1/fsp_fv.h deleted file mode 100644 index 511dfb78b8..0000000000 --- a/arch/x86/include/asm/fsp1/fsp_fv.h +++ /dev/null @@ -1,136 +0,0 @@ -/* SPDX-License-Identifier: Intel */ -/* - * Copyright (C) 2013, Intel Corporation - * Copyright (C) 2014, Bin Meng - */ - -#ifndef __FSP_FV___ -#define __FSP_FV___ - -/* Value of EFI_FV_FILE_ATTRIBUTES */ -#define EFI_FV_FILE_ATTR_ALIGNMENT 0x0000001F -#define EFI_FV_FILE_ATTR_FIXED 0x00000100 -#define EFI_FV_FILE_ATTR_MEMORY_MAPPED 0x00000200 - -/* Attributes bit definitions */ -#define EFI_FVB2_READ_DISABLED_CAP 0x00000001 -#define EFI_FVB2_READ_ENABLED_CAP 0x00000002 -#define EFI_FVB2_READ_STATUS 0x00000004 -#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008 -#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010 -#define EFI_FVB2_WRITE_STATUS 0x00000020 -#define EFI_FVB2_LOCK_CAP 0x00000040 -#define EFI_FVB2_LOCK_STATUS 0x00000080 -#define EFI_FVB2_STICKY_WRITE 0x00000200 -#define EFI_FVB2_MEMORY_MAPPED 0x00000400 -#define EFI_FVB2_ERASE_POLARITY 0x00000800 -#define EFI_FVB2_READ_LOCK_CAP 0x00001000 -#define EFI_FVB2_READ_LOCK_STATUS 0x00002000 -#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000 -#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000 -#define EFI_FVB2_ALIGNMENT 0x001F0000 -#define EFI_FVB2_ALIGNMENT_1 0x00000000 -#define EFI_FVB2_ALIGNMENT_2 0x00010000 -#define EFI_FVB2_ALIGNMENT_4 0x00020000 -#define EFI_FVB2_ALIGNMENT_8 0x00030000 -#define EFI_FVB2_ALIGNMENT_16 0x00040000 -#define EFI_FVB2_ALIGNMENT_32 0x00050000 -#define EFI_FVB2_ALIGNMENT_64 0x00060000 -#define EFI_FVB2_ALIGNMENT_128 0x00070000 -#define EFI_FVB2_ALIGNMENT_256 0x00080000 -#define EFI_FVB2_ALIGNMENT_512 0x00090000 -#define EFI_FVB2_ALIGNMENT_1K 0x000A0000 -#define EFI_FVB2_ALIGNMENT_2K 0x000B0000 -#define EFI_FVB2_ALIGNMENT_4K 0x000C0000 -#define EFI_FVB2_ALIGNMENT_8K 0x000D0000 -#define EFI_FVB2_ALIGNMENT_16K 0x000E0000 -#define EFI_FVB2_ALIGNMENT_32K 0x000F0000 -#define EFI_FVB2_ALIGNMENT_64K 0x00100000 -#define EFI_FVB2_ALIGNMENT_128K 0x00110000 -#define EFI_FVB2_ALIGNMENT_256K 0x00120000 -#define EFI_FVB2_ALIGNMENT_512K 0x00130000 -#define EFI_FVB2_ALIGNMENT_1M 0x00140000 -#define EFI_FVB2_ALIGNMENT_2M 0x00150000 -#define EFI_FVB2_ALIGNMENT_4M 0x00160000 -#define EFI_FVB2_ALIGNMENT_8M 0x00170000 -#define EFI_FVB2_ALIGNMENT_16M 0x00180000 -#define EFI_FVB2_ALIGNMENT_32M 0x00190000 -#define EFI_FVB2_ALIGNMENT_64M 0x001A0000 -#define EFI_FVB2_ALIGNMENT_128M 0x001B0000 -#define EFI_FVB2_ALIGNMENT_256M 0x001C0000 -#define EFI_FVB2_ALIGNMENT_512M 0x001D0000 -#define EFI_FVB2_ALIGNMENT_1G 0x001E0000 -#define EFI_FVB2_ALIGNMENT_2G 0x001F0000 - -struct fv_blkmap_entry { - /* The number of sequential blocks which are of the same size */ - u32 num_blocks; - /* The size of the blocks */ - u32 length; -}; - -/* Describes the features and layout of the firmware volume */ -struct fv_header { - /* - * The first 16 bytes are reserved to allow for the reset vector of - * processors whose reset vector is at address 0. - */ - u8 zero_vec[16]; - /* - * Declares the file system with which the firmware volume - * is formatted. - */ - efi_guid_t fs_guid; - /* - * Length in bytes of the complete firmware volume, including - * the header. - */ - u64 fv_len; - /* Set to EFI_FVH_SIGNATURE */ - u32 sign; - /* - * Declares capabilities and power-on defaults for the firmware - * volume. - */ - u32 attr; - /* Length in bytes of the complete firmware volume header */ - u16 hdr_len; - /* - * A 16-bit checksum of the firmware volume header. - * A valid header sums to zero. - */ - u16 checksum; - /* - * Offset, relative to the start of the header, of the extended - * header (EFI_FIRMWARE_VOLUME_EXT_HEADER) or zero if there is - * no extended header. - */ - u16 ext_hdr_off; - /* This field must always be set to zero */ - u8 reserved[1]; - /* - * Set to 2. Future versions of this specification may define new - * header fields and will increment the Revision field accordingly. - */ - u8 rev; - /* - * An array of run-length encoded FvBlockMapEntry structures. - * The array is terminated with an entry of {0,0}. - */ - struct fv_blkmap_entry block_map[1]; -}; - -#define EFI_FVH_SIGNATURE SIGNATURE_32('_', 'F', 'V', 'H') - -/* Firmware Volume Header Revision definition */ -#define EFI_FVH_REVISION 0x02 - -/* Extension header pointed by ExtHeaderOffset of volume header */ -struct fv_ext_header { - /* firmware volume name */ - efi_guid_t fv_name; - /* Size of the rest of the extension header including this structure */ - u32 ext_hdr_size; -}; - -#endif diff --git a/arch/x86/include/asm/fsp1/fsp_support.h b/arch/x86/include/asm/fsp1/fsp_support.h index e5ec2af83e..8376b2ad40 100644 --- a/arch/x86/include/asm/fsp1/fsp_support.h +++ b/arch/x86/include/asm/fsp1/fsp_support.h @@ -7,9 +7,9 @@ #ifndef __FSP_SUPPORT_H__ #define __FSP_SUPPORT_H__ +#include #include #include "fsp_hob.h" -#include "fsp_fv.h" #include "fsp_ffs.h" #include "fsp_infoheader.h" #include "fsp_bootmode.h" -- cgit From e4499b52652cf2e13756d5b23b8d0118d5bf76d6 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 2 Oct 2019 08:25:10 +0800 Subject: x86: Move fsp_hob.h to the generic fsp directory This header file is the same for FSP v1 and v2. Move it into the general fsp directory. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng [bmeng: remove inclusion of fsp_hob.h in fsp_support.h] Signed-off-by: Bin Meng --- arch/x86/include/asm/fsp/fsp_hob.h | 98 +++++++++++++++++++++++++++++++++ arch/x86/include/asm/fsp1/fsp_hob.h | 98 --------------------------------- arch/x86/include/asm/fsp1/fsp_support.h | 2 +- 3 files changed, 99 insertions(+), 99 deletions(-) create mode 100644 arch/x86/include/asm/fsp/fsp_hob.h delete mode 100644 arch/x86/include/asm/fsp1/fsp_hob.h (limited to 'arch/x86') diff --git a/arch/x86/include/asm/fsp/fsp_hob.h b/arch/x86/include/asm/fsp/fsp_hob.h new file mode 100644 index 0000000000..3bb79c4b67 --- /dev/null +++ b/arch/x86/include/asm/fsp/fsp_hob.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + */ + +#ifndef __FSP_HOB_H__ +#define __FSP_HOB_H__ + +#include + +enum pixel_format { + pixel_rgbx_8bpc, /* RGB 8 bit per color */ + pixel_bgrx_8bpc, /* BGR 8 bit per color */ + pixel_bitmask, +}; + +struct __packed hob_graphics_info { + phys_addr_t fb_base; /* framebuffer base address */ + u32 fb_size; /* framebuffer size */ + u32 version; + u32 width; + u32 height; + enum pixel_format pixel_format; + u32 red_mask; + u32 green_mask; + u32 blue_mask; + u32 reserved_mask; + u32 pixels_per_scanline; +}; + +/* FSP specific GUID HOB definitions */ +#define FSP_GUID_DATA1 0x912740be +#define FSP_GUID_DATA2 0x2284 +#define FSP_GUID_DATA3 0x4734 +#define FSP_GUID_DATA4_0 0xb9 +#define FSP_GUID_DATA4_1 0x71 +#define FSP_GUID_DATA4_2 0x84 +#define FSP_GUID_DATA4_3 0xb0 +#define FSP_GUID_DATA4_4 0x27 +#define FSP_GUID_DATA4_5 0x35 +#define FSP_GUID_DATA4_6 0x3f +#define FSP_GUID_DATA4_7 0x0c + +#define FSP_GUID_BYTE0 0xbe +#define FSP_GUID_BYTE1 0x40 +#define FSP_GUID_BYTE2 0x27 +#define FSP_GUID_BYTE3 0x91 +#define FSP_GUID_BYTE4 0x84 +#define FSP_GUID_BYTE5 0x22 +#define FSP_GUID_BYTE6 0x34 +#define FSP_GUID_BYTE7 0x47 +#define FSP_GUID_BYTE8 FSP_GUID_DATA4_0 +#define FSP_GUID_BYTE9 FSP_GUID_DATA4_1 +#define FSP_GUID_BYTE10 FSP_GUID_DATA4_2 +#define FSP_GUID_BYTE11 FSP_GUID_DATA4_3 +#define FSP_GUID_BYTE12 FSP_GUID_DATA4_4 +#define FSP_GUID_BYTE13 FSP_GUID_DATA4_5 +#define FSP_GUID_BYTE14 FSP_GUID_DATA4_6 +#define FSP_GUID_BYTE15 FSP_GUID_DATA4_7 + +#define FSP_HEADER_GUID \ + EFI_GUID(FSP_GUID_DATA1, FSP_GUID_DATA2, FSP_GUID_DATA3, \ + FSP_GUID_DATA4_0, FSP_GUID_DATA4_1, FSP_GUID_DATA4_2, \ + FSP_GUID_DATA4_3, FSP_GUID_DATA4_4, FSP_GUID_DATA4_5, \ + FSP_GUID_DATA4_6, FSP_GUID_DATA4_7) + +#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \ + EFI_GUID(0x721acf02, 0x4d77, 0x4c2a, \ + 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0) + +#define FSP_BOOTLOADER_TEMP_MEM_HOB_GUID \ + EFI_GUID(0xbbcff46c, 0xc8d3, 0x4113, \ + 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e) + +#define FSP_HOB_RESOURCE_OWNER_FSP_GUID \ + EFI_GUID(0x69a79759, 0x1373, 0x4367, \ + 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e) + +#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \ + EFI_GUID(0xd038747c, 0xd00c, 0x4980, \ + 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55) + +#define FSP_HOB_RESOURCE_OWNER_GRAPHICS_GUID \ + EFI_GUID(0x9c7c3aa7, 0x5332, 0x4917, \ + 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07) + +/* The following GUIDs are newly introduced in FSP spec 1.1 */ + +#define FSP_HOB_RESOURCE_OWNER_BOOTLOADER_TOLUM_GUID \ + EFI_GUID(0x73ff4f56, 0xaa8e, 0x4451, \ + 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44) + +#define FSP_GRAPHICS_INFO_HOB_GUID \ + EFI_GUID(0x39f62cce, 0x6825, 0x4669, \ + 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07) + +#endif diff --git a/arch/x86/include/asm/fsp1/fsp_hob.h b/arch/x86/include/asm/fsp1/fsp_hob.h deleted file mode 100644 index 3bb79c4b67..0000000000 --- a/arch/x86/include/asm/fsp1/fsp_hob.h +++ /dev/null @@ -1,98 +0,0 @@ -/* SPDX-License-Identifier: Intel */ -/* - * Copyright (C) 2013, Intel Corporation - * Copyright (C) 2014, Bin Meng - */ - -#ifndef __FSP_HOB_H__ -#define __FSP_HOB_H__ - -#include - -enum pixel_format { - pixel_rgbx_8bpc, /* RGB 8 bit per color */ - pixel_bgrx_8bpc, /* BGR 8 bit per color */ - pixel_bitmask, -}; - -struct __packed hob_graphics_info { - phys_addr_t fb_base; /* framebuffer base address */ - u32 fb_size; /* framebuffer size */ - u32 version; - u32 width; - u32 height; - enum pixel_format pixel_format; - u32 red_mask; - u32 green_mask; - u32 blue_mask; - u32 reserved_mask; - u32 pixels_per_scanline; -}; - -/* FSP specific GUID HOB definitions */ -#define FSP_GUID_DATA1 0x912740be -#define FSP_GUID_DATA2 0x2284 -#define FSP_GUID_DATA3 0x4734 -#define FSP_GUID_DATA4_0 0xb9 -#define FSP_GUID_DATA4_1 0x71 -#define FSP_GUID_DATA4_2 0x84 -#define FSP_GUID_DATA4_3 0xb0 -#define FSP_GUID_DATA4_4 0x27 -#define FSP_GUID_DATA4_5 0x35 -#define FSP_GUID_DATA4_6 0x3f -#define FSP_GUID_DATA4_7 0x0c - -#define FSP_GUID_BYTE0 0xbe -#define FSP_GUID_BYTE1 0x40 -#define FSP_GUID_BYTE2 0x27 -#define FSP_GUID_BYTE3 0x91 -#define FSP_GUID_BYTE4 0x84 -#define FSP_GUID_BYTE5 0x22 -#define FSP_GUID_BYTE6 0x34 -#define FSP_GUID_BYTE7 0x47 -#define FSP_GUID_BYTE8 FSP_GUID_DATA4_0 -#define FSP_GUID_BYTE9 FSP_GUID_DATA4_1 -#define FSP_GUID_BYTE10 FSP_GUID_DATA4_2 -#define FSP_GUID_BYTE11 FSP_GUID_DATA4_3 -#define FSP_GUID_BYTE12 FSP_GUID_DATA4_4 -#define FSP_GUID_BYTE13 FSP_GUID_DATA4_5 -#define FSP_GUID_BYTE14 FSP_GUID_DATA4_6 -#define FSP_GUID_BYTE15 FSP_GUID_DATA4_7 - -#define FSP_HEADER_GUID \ - EFI_GUID(FSP_GUID_DATA1, FSP_GUID_DATA2, FSP_GUID_DATA3, \ - FSP_GUID_DATA4_0, FSP_GUID_DATA4_1, FSP_GUID_DATA4_2, \ - FSP_GUID_DATA4_3, FSP_GUID_DATA4_4, FSP_GUID_DATA4_5, \ - FSP_GUID_DATA4_6, FSP_GUID_DATA4_7) - -#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \ - EFI_GUID(0x721acf02, 0x4d77, 0x4c2a, \ - 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0) - -#define FSP_BOOTLOADER_TEMP_MEM_HOB_GUID \ - EFI_GUID(0xbbcff46c, 0xc8d3, 0x4113, \ - 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e) - -#define FSP_HOB_RESOURCE_OWNER_FSP_GUID \ - EFI_GUID(0x69a79759, 0x1373, 0x4367, \ - 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e) - -#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \ - EFI_GUID(0xd038747c, 0xd00c, 0x4980, \ - 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55) - -#define FSP_HOB_RESOURCE_OWNER_GRAPHICS_GUID \ - EFI_GUID(0x9c7c3aa7, 0x5332, 0x4917, \ - 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07) - -/* The following GUIDs are newly introduced in FSP spec 1.1 */ - -#define FSP_HOB_RESOURCE_OWNER_BOOTLOADER_TOLUM_GUID \ - EFI_GUID(0x73ff4f56, 0xaa8e, 0x4451, \ - 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44) - -#define FSP_GRAPHICS_INFO_HOB_GUID \ - EFI_GUID(0x39f62cce, 0x6825, 0x4669, \ - 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07) - -#endif diff --git a/arch/x86/include/asm/fsp1/fsp_support.h b/arch/x86/include/asm/fsp1/fsp_support.h index 8376b2ad40..e204045482 100644 --- a/arch/x86/include/asm/fsp1/fsp_support.h +++ b/arch/x86/include/asm/fsp1/fsp_support.h @@ -8,8 +8,8 @@ #define __FSP_SUPPORT_H__ #include +#include #include -#include "fsp_hob.h" #include "fsp_ffs.h" #include "fsp_infoheader.h" #include "fsp_bootmode.h" -- cgit From 21a1133d823b3cadbbe9f18475948bfcd587be60 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 2 Oct 2019 08:26:41 +0800 Subject: x86: Move fsp_infoheader.h to the generic fsp directory This header file is the same for FSP v1 and v2. Move it into the general fsp directory. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng [bmeng: move rename of fsp_infoheader.h from previous patch to this one] Signed-off-by: Bin Meng --- arch/x86/include/asm/fsp/fsp_infoheader.h | 38 ++++++++++++++++++++++++++++++ arch/x86/include/asm/fsp1/fsp_infoheader.h | 38 ------------------------------ arch/x86/include/asm/fsp1/fsp_support.h | 2 +- 3 files changed, 39 insertions(+), 39 deletions(-) create mode 100644 arch/x86/include/asm/fsp/fsp_infoheader.h delete mode 100644 arch/x86/include/asm/fsp1/fsp_infoheader.h (limited to 'arch/x86') diff --git a/arch/x86/include/asm/fsp/fsp_infoheader.h b/arch/x86/include/asm/fsp/fsp_infoheader.h new file mode 100644 index 0000000000..86f78014b7 --- /dev/null +++ b/arch/x86/include/asm/fsp/fsp_infoheader.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + */ + +#ifndef _FSP_HEADER_H_ +#define _FSP_HEADER_H_ + +#define FSP_HEADER_OFF 0x94 /* Fixed FSP header offset in the FSP image */ + +struct __packed fsp_header { + u32 sign; /* 'FSPH' */ + u32 hdr_len; /* header length */ + u8 reserved1[3]; + u8 hdr_rev; /* header rev */ + u32 img_rev; /* image rev */ + char img_id[8]; /* signature string */ + u32 img_size; /* image size */ + u32 img_base; /* image base */ + u32 img_attr; /* image attribute */ + u32 cfg_region_off; /* configuration region offset */ + u32 cfg_region_size; /* configuration region size */ + u32 api_num; /* number of API entries */ + u32 fsp_tempram_init; /* tempram_init offset */ + u32 fsp_init; /* fsp_init offset */ + u32 fsp_notify; /* fsp_notify offset */ + u32 fsp_mem_init; /* fsp_mem_init offset */ + u32 fsp_tempram_exit; /* fsp_tempram_exit offset */ + u32 fsp_silicon_init; /* fsp_silicon_init offset */ +}; + +#define FSP_HEADER_REVISION_1 1 +#define FSP_HEADER_REVISION_2 2 + +#define FSP_ATTR_GRAPHICS_SUPPORT (1 << 0) + +#endif diff --git a/arch/x86/include/asm/fsp1/fsp_infoheader.h b/arch/x86/include/asm/fsp1/fsp_infoheader.h deleted file mode 100644 index 86f78014b7..0000000000 --- a/arch/x86/include/asm/fsp1/fsp_infoheader.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: Intel */ -/* - * Copyright (C) 2013, Intel Corporation - * Copyright (C) 2014, Bin Meng - */ - -#ifndef _FSP_HEADER_H_ -#define _FSP_HEADER_H_ - -#define FSP_HEADER_OFF 0x94 /* Fixed FSP header offset in the FSP image */ - -struct __packed fsp_header { - u32 sign; /* 'FSPH' */ - u32 hdr_len; /* header length */ - u8 reserved1[3]; - u8 hdr_rev; /* header rev */ - u32 img_rev; /* image rev */ - char img_id[8]; /* signature string */ - u32 img_size; /* image size */ - u32 img_base; /* image base */ - u32 img_attr; /* image attribute */ - u32 cfg_region_off; /* configuration region offset */ - u32 cfg_region_size; /* configuration region size */ - u32 api_num; /* number of API entries */ - u32 fsp_tempram_init; /* tempram_init offset */ - u32 fsp_init; /* fsp_init offset */ - u32 fsp_notify; /* fsp_notify offset */ - u32 fsp_mem_init; /* fsp_mem_init offset */ - u32 fsp_tempram_exit; /* fsp_tempram_exit offset */ - u32 fsp_silicon_init; /* fsp_silicon_init offset */ -}; - -#define FSP_HEADER_REVISION_1 1 -#define FSP_HEADER_REVISION_2 2 - -#define FSP_ATTR_GRAPHICS_SUPPORT (1 << 0) - -#endif diff --git a/arch/x86/include/asm/fsp1/fsp_support.h b/arch/x86/include/asm/fsp1/fsp_support.h index e204045482..ed4335ed29 100644 --- a/arch/x86/include/asm/fsp1/fsp_support.h +++ b/arch/x86/include/asm/fsp1/fsp_support.h @@ -9,9 +9,9 @@ #include #include +#include #include #include "fsp_ffs.h" -#include "fsp_infoheader.h" #include "fsp_bootmode.h" #include #include -- cgit From 79b228baae06a57d0d01358e832d5ea2f2cc02d3 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:00:19 -0600 Subject: x86: Move fsp_bootmode.h to the generic fsp directory This header file is the same for FSP v1 and v2, although there may be some additions to come. Move it into the generic fsp directory. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/x86/include/asm/fsp/fsp_bootmode.h | 23 +++++++++++++++++++++++ arch/x86/include/asm/fsp1/fsp_bootmode.h | 23 ----------------------- arch/x86/include/asm/fsp1/fsp_support.h | 2 +- 3 files changed, 24 insertions(+), 24 deletions(-) create mode 100644 arch/x86/include/asm/fsp/fsp_bootmode.h delete mode 100644 arch/x86/include/asm/fsp1/fsp_bootmode.h (limited to 'arch/x86') diff --git a/arch/x86/include/asm/fsp/fsp_bootmode.h b/arch/x86/include/asm/fsp/fsp_bootmode.h new file mode 100644 index 0000000000..bc96ec308c --- /dev/null +++ b/arch/x86/include/asm/fsp/fsp_bootmode.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + */ + +#ifndef __FSP_BOOT_MODE_H__ +#define __FSP_BOOT_MODE_H__ + +/* 0x21 - 0xf..f are reserved */ +#define BOOT_FULL_CONFIG 0x00 +#define BOOT_MINIMAL_CONFIG 0x01 +#define BOOT_NO_CONFIG_CHANGES 0x02 +#define BOOT_FULL_CONFIG_PLUS_DIAG 0x03 +#define BOOT_DEFAULT_SETTINGS 0x04 +#define BOOT_ON_S4_RESUME 0x05 +#define BOOT_ON_S5_RESUME 0x06 +#define BOOT_ON_S2_RESUME 0x10 +#define BOOT_ON_S3_RESUME 0x11 +#define BOOT_ON_FLASH_UPDATE 0x12 +#define BOOT_IN_RECOVERY_MODE 0x20 + +#endif diff --git a/arch/x86/include/asm/fsp1/fsp_bootmode.h b/arch/x86/include/asm/fsp1/fsp_bootmode.h deleted file mode 100644 index bc96ec308c..0000000000 --- a/arch/x86/include/asm/fsp1/fsp_bootmode.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: Intel */ -/* - * Copyright (C) 2013, Intel Corporation - * Copyright (C) 2014, Bin Meng - */ - -#ifndef __FSP_BOOT_MODE_H__ -#define __FSP_BOOT_MODE_H__ - -/* 0x21 - 0xf..f are reserved */ -#define BOOT_FULL_CONFIG 0x00 -#define BOOT_MINIMAL_CONFIG 0x01 -#define BOOT_NO_CONFIG_CHANGES 0x02 -#define BOOT_FULL_CONFIG_PLUS_DIAG 0x03 -#define BOOT_DEFAULT_SETTINGS 0x04 -#define BOOT_ON_S4_RESUME 0x05 -#define BOOT_ON_S5_RESUME 0x06 -#define BOOT_ON_S2_RESUME 0x10 -#define BOOT_ON_S3_RESUME 0x11 -#define BOOT_ON_FLASH_UPDATE 0x12 -#define BOOT_IN_RECOVERY_MODE 0x20 - -#endif diff --git a/arch/x86/include/asm/fsp1/fsp_support.h b/arch/x86/include/asm/fsp1/fsp_support.h index ed4335ed29..c2c5288ebd 100644 --- a/arch/x86/include/asm/fsp1/fsp_support.h +++ b/arch/x86/include/asm/fsp1/fsp_support.h @@ -7,12 +7,12 @@ #ifndef __FSP_SUPPORT_H__ #define __FSP_SUPPORT_H__ +#include #include #include #include #include #include "fsp_ffs.h" -#include "fsp_bootmode.h" #include #include -- cgit From 0e23d7660a06978d8953cbeedd931ab0df01294f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:00:20 -0600 Subject: x86: Move fsp_ffs.h include to fsp_arch.h This include file is only used for FSP v1. Avoid including it from fdt_support.h so we can use the latter with FSP v2. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/x86/include/asm/fsp_arch.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/x86') diff --git a/arch/x86/include/asm/fsp_arch.h b/arch/x86/include/asm/fsp_arch.h index b223141c44..3b2077b392 100644 --- a/arch/x86/include/asm/fsp_arch.h +++ b/arch/x86/include/asm/fsp_arch.h @@ -15,6 +15,7 @@ */ #include +#include #include #include -- cgit From e2adc369ec5c10dda8b0e15cfc6399d81bcfc6d1 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:11:25 -0600 Subject: x86: Rename some FSP functions to have an fsp_ prefix Given these exported function an fsp_ prefix since they are declared in an fsp.h header. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/x86/cpu/baytrail/fsp_configs.c | 2 +- arch/x86/cpu/braswell/fsp_configs.c | 2 +- arch/x86/cpu/ivybridge/fsp_configs.c | 2 +- arch/x86/cpu/queensbay/fsp_configs.c | 2 +- arch/x86/include/asm/fsp1/fsp_support.h | 6 +++--- arch/x86/lib/fsp1/fsp_car.S | 10 +++++----- arch/x86/lib/fsp1/fsp_support.c | 14 +++++++------- 7 files changed, 19 insertions(+), 19 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c index 5b5d66aa5e..1d1948c91a 100644 --- a/arch/x86/cpu/baytrail/fsp_configs.c +++ b/arch/x86/cpu/baytrail/fsp_configs.c @@ -27,7 +27,7 @@ __weak void update_fsp_azalia_configs(struct azalia_config **azalia) * If the device tree does not specify an integer setting, use the default * provided in Intel's Baytrail_FSP_Gold4.tgz release FSP/BayleyBayFsp.bsf file. */ -void update_fsp_configs(struct fsp_config_data *config, +void fsp_update_configs(struct fsp_config_data *config, struct fspinit_rtbuf *rt_buf) { struct upd_region *fsp_upd = &config->fsp_upd; diff --git a/arch/x86/cpu/braswell/fsp_configs.c b/arch/x86/cpu/braswell/fsp_configs.c index 607e333f21..60101d742d 100644 --- a/arch/x86/cpu/braswell/fsp_configs.c +++ b/arch/x86/cpu/braswell/fsp_configs.c @@ -40,7 +40,7 @@ __weak void update_fsp_gpio_configs(struct gpio_family **family, * If the device tree does not specify an integer setting, use the default * provided in Intel's Braswell release FSP/BraswellFsp.bsf file. */ -void update_fsp_configs(struct fsp_config_data *config, +void fsp_update_configs(struct fsp_config_data *config, struct fspinit_rtbuf *rt_buf) { struct upd_region *fsp_upd = &config->fsp_upd; diff --git a/arch/x86/cpu/ivybridge/fsp_configs.c b/arch/x86/cpu/ivybridge/fsp_configs.c index 773c2b2a0a..0e6453c847 100644 --- a/arch/x86/cpu/ivybridge/fsp_configs.c +++ b/arch/x86/cpu/ivybridge/fsp_configs.c @@ -9,7 +9,7 @@ DECLARE_GLOBAL_DATA_PTR; -void update_fsp_configs(struct fsp_config_data *config, +void fsp_update_configs(struct fsp_config_data *config, struct fspinit_rtbuf *rt_buf) { struct platform_config *plat_config = &config->plat_config; diff --git a/arch/x86/cpu/queensbay/fsp_configs.c b/arch/x86/cpu/queensbay/fsp_configs.c index 0dd1901e07..381edd0761 100644 --- a/arch/x86/cpu/queensbay/fsp_configs.c +++ b/arch/x86/cpu/queensbay/fsp_configs.c @@ -7,7 +7,7 @@ #include #include -void update_fsp_configs(struct fsp_config_data *config, +void fsp_update_configs(struct fsp_config_data *config, struct fspinit_rtbuf *rt_buf) { /* Initialize runtime buffer for fsp_init() */ diff --git a/arch/x86/include/asm/fsp1/fsp_support.h b/arch/x86/include/asm/fsp1/fsp_support.h index c2c5288ebd..a0095d0de4 100644 --- a/arch/x86/include/asm/fsp1/fsp_support.h +++ b/arch/x86/include/asm/fsp1/fsp_support.h @@ -25,7 +25,7 @@ * * This routine jumps to the C version of FSP continuation function */ -void asm_continuation(void); +void fsp_asm_continuation(void); /** * FSP initialization complete @@ -52,7 +52,7 @@ void fsp_continue(u32 status, void *hob_list); * * @retval: the offset of FSP header. If signature is invalid, returns 0. */ -struct fsp_header *find_fsp_header(void); +struct fsp_header *fsp_find_header(void); /** * FSP initialization wrapper function. @@ -172,7 +172,7 @@ void *fsp_get_graphics_info(const void *hob_list, u32 *len); * * @return: None */ -void update_fsp_configs(struct fsp_config_data *config, +void fsp_update_configs(struct fsp_config_data *config, struct fspinit_rtbuf *rt_buf); /** diff --git a/arch/x86/lib/fsp1/fsp_car.S b/arch/x86/lib/fsp1/fsp_car.S index 8c54cea3db..a64a653435 100644 --- a/arch/x86/lib/fsp1/fsp_car.S +++ b/arch/x86/lib/fsp1/fsp_car.S @@ -20,10 +20,10 @@ car_init: car_init_start: post_code(POST_CAR_START) - lea find_fsp_header_romstack, %esp - jmp find_fsp_header + lea fsp_find_header_romstack, %esp + jmp fsp_find_header -find_fsp_header_ret: +fsp_find_header_ret: /* EAX points to FSP_INFO_HEADER */ mov %eax, %ebp @@ -91,8 +91,8 @@ die: * contain the function return address as well as the parameters. */ .balign 4 -find_fsp_header_romstack: - .long find_fsp_header_ret +fsp_find_header_romstack: + .long fsp_find_header_ret .balign 4 temp_ram_init_romstack: diff --git a/arch/x86/lib/fsp1/fsp_support.c b/arch/x86/lib/fsp1/fsp_support.c index 019a42f53f..b5b7d664a1 100644 --- a/arch/x86/lib/fsp1/fsp_support.c +++ b/arch/x86/lib/fsp1/fsp_support.c @@ -8,7 +8,7 @@ #include #include -struct fsp_header *__attribute__((optimize("O0"))) find_fsp_header(void) +struct fsp_header *__attribute__((optimize("O0"))) fsp_find_header(void) { /* * This function may be called before the a stack is established, @@ -93,7 +93,7 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) struct upd_region *fsp_upd; #endif - fsp_hdr = find_fsp_header(); + fsp_hdr = fsp_find_header(); if (fsp_hdr == NULL) { /* No valid FSP info header was found */ panic("Invalid FSP header"); @@ -124,12 +124,12 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf)); /* Override any configuration if required */ - update_fsp_configs(&config_data, &rt_buf); + fsp_update_configs(&config_data, &rt_buf); memset(¶ms, 0, sizeof(struct fsp_init_params)); params.nvs_buf = nvs_buf; params.rt_buf = (struct fspinit_rtbuf *)&rt_buf; - params.continuation = (fsp_continuation_f)asm_continuation; + params.continuation = (fsp_continuation_f)fsp_asm_continuation; init = (fsp_init_f)(fsp_hdr->img_base + fsp_hdr->fsp_init); params_ptr = ¶ms; @@ -146,8 +146,8 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) asm volatile ( "pushl %0;" "call *%%eax;" - ".global asm_continuation;" - "asm_continuation:;" + ".global fsp_asm_continuation;" + "fsp_asm_continuation:;" "movl 4(%%esp), %%eax;" /* status */ "movl 8(%%esp), %%edx;" /* hob_list */ "jmp fsp_continue;" @@ -173,7 +173,7 @@ u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase) u32 status; if (!fsp_hdr) - fsp_hdr = (struct fsp_header *)find_fsp_header(); + fsp_hdr = (struct fsp_header *)fsp_find_header(); if (fsp_hdr == NULL) { /* No valid FSP info header */ -- cgit From 07f2f58b94b69ea962d1adea0b892825dea908e9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 24 Aug 2019 14:19:05 -0600 Subject: x86: fsp: Create a common fsp_support.h header Many support functions are common between FSP1 and FSP2. Add a new header to handle this. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng [bmeng: remove forward declarations in fsp_support.h] Signed-off-by: Bin Meng --- arch/x86/include/asm/fsp/fsp_support.h | 125 ++++++++++++++++++++++++++++++++ arch/x86/include/asm/fsp1/fsp_support.h | 119 +----------------------------- 2 files changed, 128 insertions(+), 116 deletions(-) create mode 100644 arch/x86/include/asm/fsp/fsp_support.h (limited to 'arch/x86') diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h new file mode 100644 index 0000000000..1c016faee8 --- /dev/null +++ b/arch/x86/include/asm/fsp/fsp_support.h @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + */ + +#ifndef __FSP_SUPPORT_H__ +#define __FSP_SUPPORT_H__ + +#include +#include +#include +#include +#include +#include +#include + +#define FSP_LOWMEM_BASE 0x100000UL +#define FSP_HIGHMEM_BASE 0x100000000ULL +#define UPD_TERMINATOR 0x55AA + +/** + * Find FSP header offset in FSP image + * + * @retval: the offset of FSP header. If signature is invalid, returns 0. + */ +struct fsp_header *fsp_find_header(void); + +/** + * FSP notification wrapper function + * + * @fsp_hdr: Pointer to FSP information header + * @phase: FSP initialization phase defined in enum fsp_phase + * + * @retval: compatible status code with EFI_STATUS defined in PI spec + */ +u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase); + +/** + * This function retrieves the top of usable low memory. + * + * @hob_list: A HOB list pointer. + * + * @retval: Usable low memory top. + */ +u32 fsp_get_usable_lowmem_top(const void *hob_list); + +/** + * This function retrieves the top of usable high memory. + * + * @hob_list: A HOB list pointer. + * + * @retval: Usable high memory top. + */ +u64 fsp_get_usable_highmem_top(const void *hob_list); + +/** + * This function retrieves a special reserved memory region. + * + * @hob_list: A HOB list pointer. + * @len: A pointer to the GUID HOB data buffer length. + * If the GUID HOB is located, the length will be updated. + * @guid: A pointer to the owner guild. + * + * @retval: Reserved region start address. + * 0 if this region does not exist. + */ +u64 fsp_get_reserved_mem_from_guid(const void *hob_list, + u64 *len, const efi_guid_t *guid); + +/** + * This function retrieves the FSP reserved normal memory. + * + * @hob_list: A HOB list pointer. + * @len: A pointer to the FSP reserved memory length buffer. + * If the GUID HOB is located, the length will be updated. + * @retval: FSP reserved memory base + * 0 if this region does not exist. + */ +u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len); + +/** + * This function retrieves the TSEG reserved normal memory. + * + * @hob_list: A HOB list pointer. + * @len: A pointer to the TSEG reserved memory length buffer. + * If the GUID HOB is located, the length will be updated. + * + * @retval NULL: Failed to find the TSEG reserved memory. + * @retval others: TSEG reserved memory base. + */ +u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len); + +/** + * This function retrieves FSP Non-volatile Storage HOB buffer and size. + * + * @hob_list: A HOB list pointer. + * @len: A pointer to the NVS data buffer length. + * If the HOB is located, the length will be updated. + * + * @retval NULL: Failed to find the NVS HOB. + * @retval others: FSP NVS data buffer pointer. + */ +void *fsp_get_nvs_data(const void *hob_list, u32 *len); + +/** + * This function retrieves graphics information. + * + * @hob_list: A HOB list pointer. + * @len: A pointer to the graphics info HOB length. + * If the HOB is located, the length will be updated. + * + * @retval NULL: Failed to find the graphics info HOB. + * @retval others: A pointer to struct hob_graphics_info. + */ +void *fsp_get_graphics_info(const void *hob_list, u32 *len); + +/** + * fsp_init_phase_pci() - Tell the FSP that we have completed PCI init + * + * @return 0 if OK, -EPERM if the FSP gave an error. + */ +int fsp_init_phase_pci(void); + +#endif diff --git a/arch/x86/include/asm/fsp1/fsp_support.h b/arch/x86/include/asm/fsp1/fsp_support.h index a0095d0de4..15c3a462e2 100644 --- a/arch/x86/include/asm/fsp1/fsp_support.h +++ b/arch/x86/include/asm/fsp1/fsp_support.h @@ -4,21 +4,11 @@ * Copyright (C) 2014, Bin Meng */ -#ifndef __FSP_SUPPORT_H__ -#define __FSP_SUPPORT_H__ +#ifndef __FSP1_SUPPORT_H__ +#define __FSP1_SUPPORT_H__ -#include -#include -#include -#include -#include +#include #include "fsp_ffs.h" -#include -#include - -#define FSP_LOWMEM_BASE 0x100000UL -#define FSP_HIGHMEM_BASE 0x100000000ULL -#define UPD_TERMINATOR 0x55AA /** * FSP Continuation assembly helper routine @@ -47,13 +37,6 @@ void fsp_init_done(void *hob_list); */ void fsp_continue(u32 status, void *hob_list); -/** - * Find FSP header offset in FSP image - * - * @retval: the offset of FSP header. If signature is invalid, returns 0. - */ -struct fsp_header *fsp_find_header(void); - /** * FSP initialization wrapper function. * @@ -63,83 +46,6 @@ struct fsp_header *fsp_find_header(void); */ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf); -/** - * FSP notification wrapper function - * - * @fsp_hdr: Pointer to FSP information header - * @phase: FSP initialization phase defined in enum fsp_phase - * - * @retval: compatible status code with EFI_STATUS defined in PI spec - */ -u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase); - -/** - * This function retrieves the top of usable low memory. - * - * @hob_list: A HOB list pointer. - * - * @retval: Usable low memory top. - */ -u32 fsp_get_usable_lowmem_top(const void *hob_list); - -/** - * This function retrieves the top of usable high memory. - * - * @hob_list: A HOB list pointer. - * - * @retval: Usable high memory top. - */ -u64 fsp_get_usable_highmem_top(const void *hob_list); - -/** - * This function retrieves a special reserved memory region. - * - * @hob_list: A HOB list pointer. - * @len: A pointer to the GUID HOB data buffer length. - * If the GUID HOB is located, the length will be updated. - * @guid: A pointer to the owner guild. - * - * @retval: Reserved region start address. - * 0 if this region does not exist. - */ -u64 fsp_get_reserved_mem_from_guid(const void *hob_list, - u64 *len, const efi_guid_t *guid); - -/** - * This function retrieves the FSP reserved normal memory. - * - * @hob_list: A HOB list pointer. - * @len: A pointer to the FSP reserved memory length buffer. - * If the GUID HOB is located, the length will be updated. - * @retval: FSP reserved memory base - * 0 if this region does not exist. - */ -u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len); - -/** - * This function retrieves the TSEG reserved normal memory. - * - * @hob_list: A HOB list pointer. - * @len: A pointer to the TSEG reserved memory length buffer. - * If the GUID HOB is located, the length will be updated. - * - * @retval NULL: Failed to find the TSEG reserved memory. - * @retval others: TSEG reserved memory base. - */ -u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len); - -/** - * This function retrieves FSP Non-volatile Storage HOB buffer and size. - * - * @hob_list: A HOB list pointer. - * @len: A pointer to the NVS data buffer length. - * If the HOB is located, the length will be updated. - * - * @retval NULL: Failed to find the NVS HOB. - * @retval others: FSP NVS data buffer pointer. - */ -void *fsp_get_nvs_data(const void *hob_list, u32 *len); - /** * This function retrieves Bootloader temporary stack buffer and size. * @@ -152,18 +58,6 @@ void *fsp_get_nvs_data(const void *hob_list, u32 *len); */ void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len); -/** - * This function retrieves graphics information. - * - * @hob_list: A HOB list pointer. - * @len: A pointer to the graphics info HOB length. - * If the HOB is located, the length will be updated. - * - * @retval NULL: Failed to find the graphics info HOB. - * @retval others: A pointer to struct hob_graphics_info. - */ -void *fsp_get_graphics_info(const void *hob_list, u32 *len); - /** * This function overrides the default configurations of FSP. * @@ -175,11 +69,4 @@ void *fsp_get_graphics_info(const void *hob_list, u32 *len); void fsp_update_configs(struct fsp_config_data *config, struct fspinit_rtbuf *rt_buf); -/** - * fsp_init_phase_pci() - Tell the FSP that we have completed PCI init - * - * @return 0 if OK, -EPERM if the FSP gave an error. - */ -int fsp_init_phase_pci(void); - #endif -- cgit From 86875f050bf433fa8078ae9c53d8493f79941f1a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:11:27 -0600 Subject: x86: fsp: Use if() instead of #ifdef Update a few #ifdefs to if() to improve build coverage. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng [bmeng: recover the codes that got wrongly deleted in dram_init()] Signed-off-by: Bin Meng --- arch/x86/lib/fsp1/fsp_common.c | 9 ++++----- arch/x86/lib/fsp1/fsp_dram.c | 5 ++--- 2 files changed, 6 insertions(+), 8 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/lib/fsp1/fsp_common.c b/arch/x86/lib/fsp1/fsp_common.c index 591eef7b81..bfd76dccba 100644 --- a/arch/x86/lib/fsp1/fsp_common.c +++ b/arch/x86/lib/fsp1/fsp_common.c @@ -116,11 +116,10 @@ int arch_fsp_init(void) #endif if (!gd->arch.hob_list) { -#ifdef CONFIG_ENABLE_MRC_CACHE - nvs = fsp_prepare_mrc_cache(); -#else - nvs = NULL; -#endif + if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) + nvs = fsp_prepare_mrc_cache(); + else + nvs = NULL; #ifdef CONFIG_HAVE_ACPI_RESUME if (prev_sleep_state == ACPI_S3) { diff --git a/arch/x86/lib/fsp1/fsp_dram.c b/arch/x86/lib/fsp1/fsp_dram.c index 3bf65b495c..75341bc528 100644 --- a/arch/x86/lib/fsp1/fsp_dram.c +++ b/arch/x86/lib/fsp1/fsp_dram.c @@ -32,10 +32,9 @@ int dram_init(void) gd->ram_size = ram_size; post_code(POST_DRAM); -#ifdef CONFIG_ENABLE_MRC_CACHE - gd->arch.mrc_output = fsp_get_nvs_data(gd->arch.hob_list, + if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) + gd->arch.mrc_output = fsp_get_nvs_data(gd->arch.hob_list, &gd->arch.mrc_output_len); -#endif return 0; } -- cgit From 12cf65a4d199e5d4ef8b167342579ab16d0f849b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 25 Aug 2019 10:10:59 -0600 Subject: x86: fsp: Tidy up comment style a little The comments in the FSP code use a different style from the rest of the x86 code. I am not sure it this is intentional. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng [bmeng: fix 2 comment style issues] Signed-off-by: Bin Meng --- arch/x86/include/asm/fsp/fsp_support.h | 42 ++++++++++++++++----------------- arch/x86/include/asm/fsp1/fsp_support.h | 30 +++++++++++++++-------- arch/x86/include/asm/hob.h | 18 +++++++------- arch/x86/lib/hob.c | 8 +++---- 4 files changed, 54 insertions(+), 44 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h index 1c016faee8..a6b32bf95d 100644 --- a/arch/x86/include/asm/fsp/fsp_support.h +++ b/arch/x86/include/asm/fsp/fsp_support.h @@ -20,98 +20,98 @@ #define UPD_TERMINATOR 0x55AA /** - * Find FSP header offset in FSP image + * fsp_find_header() - Find FSP header offset in FSP image * - * @retval: the offset of FSP header. If signature is invalid, returns 0. + * @return the offset of FSP header. If signature is invalid, returns 0. */ struct fsp_header *fsp_find_header(void); /** - * FSP notification wrapper function + * fsp_notify() - FSP notification wrapper function * * @fsp_hdr: Pointer to FSP information header * @phase: FSP initialization phase defined in enum fsp_phase * - * @retval: compatible status code with EFI_STATUS defined in PI spec + * @return compatible status code with EFI_STATUS defined in PI spec */ u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase); /** - * This function retrieves the top of usable low memory. + * fsp_get_usable_lowmem_top() - retrieves the top of usable low memory * * @hob_list: A HOB list pointer. * - * @retval: Usable low memory top. + * @return Usable low memory top. */ u32 fsp_get_usable_lowmem_top(const void *hob_list); /** - * This function retrieves the top of usable high memory. + * fsp_get_usable_highmem_top() - retrieves the top of usable high memory * * @hob_list: A HOB list pointer. * - * @retval: Usable high memory top. + * @return Usable high memory top. */ u64 fsp_get_usable_highmem_top(const void *hob_list); /** - * This function retrieves a special reserved memory region. + * fsp_get_reserved_mem_from_guid() - retrieves a special reserved memory region * * @hob_list: A HOB list pointer. * @len: A pointer to the GUID HOB data buffer length. * If the GUID HOB is located, the length will be updated. * @guid: A pointer to the owner guild. * - * @retval: Reserved region start address. + * @return Reserved region start address. * 0 if this region does not exist. */ u64 fsp_get_reserved_mem_from_guid(const void *hob_list, u64 *len, const efi_guid_t *guid); /** - * This function retrieves the FSP reserved normal memory. + * fsp_get_fsp_reserved_mem() - retrieves the FSP reserved normal memory * * @hob_list: A HOB list pointer. * @len: A pointer to the FSP reserved memory length buffer. * If the GUID HOB is located, the length will be updated. - * @retval: FSP reserved memory base + * @return FSP reserved memory base * 0 if this region does not exist. */ u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len); /** - * This function retrieves the TSEG reserved normal memory. + * fsp_get_tseg_reserved_mem() - retrieves the TSEG reserved normal memory * * @hob_list: A HOB list pointer. * @len: A pointer to the TSEG reserved memory length buffer. * If the GUID HOB is located, the length will be updated. * - * @retval NULL: Failed to find the TSEG reserved memory. - * @retval others: TSEG reserved memory base. + * @return NULL: Failed to find the TSEG reserved memory. + * @return others: TSEG reserved memory base. */ u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len); /** - * This function retrieves FSP Non-volatile Storage HOB buffer and size. + * fsp_get_nvs_data() - retrieves FSP Non-volatile Storage HOB buffer and size * * @hob_list: A HOB list pointer. * @len: A pointer to the NVS data buffer length. * If the HOB is located, the length will be updated. * - * @retval NULL: Failed to find the NVS HOB. - * @retval others: FSP NVS data buffer pointer. + * @return NULL: Failed to find the NVS HOB. + * @return others: FSP NVS data buffer pointer. */ void *fsp_get_nvs_data(const void *hob_list, u32 *len); /** - * This function retrieves graphics information. + * fsp_get_graphics_info() - retrieves graphics information. * * @hob_list: A HOB list pointer. * @len: A pointer to the graphics info HOB length. * If the HOB is located, the length will be updated. * - * @retval NULL: Failed to find the graphics info HOB. - * @retval others: A pointer to struct hob_graphics_info. + * @return NULL: Failed to find the graphics info HOB. + * @return others: A pointer to struct hob_graphics_info. */ void *fsp_get_graphics_info(const void *hob_list, u32 *len); diff --git a/arch/x86/include/asm/fsp1/fsp_support.h b/arch/x86/include/asm/fsp1/fsp_support.h index 15c3a462e2..236c167fc8 100644 --- a/arch/x86/include/asm/fsp1/fsp_support.h +++ b/arch/x86/include/asm/fsp1/fsp_support.h @@ -11,14 +11,14 @@ #include "fsp_ffs.h" /** - * FSP Continuation assembly helper routine + * fsp_asm_continuation() - FSP Continuation assembly helper routine * * This routine jumps to the C version of FSP continuation function */ void fsp_asm_continuation(void); /** - * FSP initialization complete + * fsp_init_done() - FSP initialization complete * * This is the function that indicates FSP initialization is complete and jumps * back to the bootloader with HOB list pointer as the parameter. @@ -28,17 +28,17 @@ void fsp_asm_continuation(void); void fsp_init_done(void *hob_list); /** - * FSP Continuation function + * fsp_continue() - FSP Continuation function * * @status: Always 0 * @hob_list: HOB list pointer * - * @retval: Never returns + * @return Never returns */ void fsp_continue(u32 status, void *hob_list); /** - * FSP initialization wrapper function. + * fsp_init() - FSP initialization wrapper function * * @stack_top: bootloader stack top address * @boot_mode: boot mode defined in fsp_bootmode.h @@ -47,24 +47,34 @@ void fsp_continue(u32 status, void *hob_list); void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf); /** - * This function retrieves Bootloader temporary stack buffer and size. + * fsp_notify() - FSP notification wrapper function + * + * @fsp_hdr: Pointer to FSP information header + * @phase: FSP initialization phase defined in enum fsp_phase + * + * @return compatible status code with EFI_STATUS defined in PI spec + */ +u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase); + +/** + * fsp_get_bootloader_tmp_mem() - retrieves temporary stack buffer and size * * @hob_list: A HOB list pointer. * @len: A pointer to the bootloader temporary stack length. * If the HOB is located, the length will be updated. * - * @retval NULL: Failed to find the bootloader temporary stack HOB. - * @retval others: Bootloader temporary stackbuffer pointer. + * @return NULL: Failed to find the bootloader temporary stack HOB. + * @return others: Bootloader temporary stackbuffer pointer. */ void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len); /** - * This function overrides the default configurations of FSP. + * fsp_update_configs() - overrides the default configurations of FSP * * @config: A pointer to the FSP configuration data structure * @rt_buf: A pointer to the FSP runtime buffer data structure * - * @return: None + * @return None */ void fsp_update_configs(struct fsp_config_data *config, struct fspinit_rtbuf *rt_buf); diff --git a/arch/x86/include/asm/hob.h b/arch/x86/include/asm/hob.h index b4239821aa..56e11dbb28 100644 --- a/arch/x86/include/asm/hob.h +++ b/arch/x86/include/asm/hob.h @@ -135,7 +135,7 @@ struct hob_guid { * * @hdr: A pointer to a HOB. * - * @return: A pointer to the next HOB in the HOB list. + * @return A pointer to the next HOB in the HOB list. */ static inline const struct hob_header *get_next_hob(const struct hob_header *hdr) @@ -152,8 +152,8 @@ static inline const struct hob_header *get_next_hob(const struct hob_header * * @hdr: A pointer to a HOB. * - * @retval true: The HOB specified by hdr is the last HOB in the HOB list. - * @retval false: The HOB specified by hdr is not the last HOB in the HOB list. + * @return true: The HOB specified by hdr is the last HOB in the HOB list. + * @return false: The HOB specified by hdr is not the last HOB in the HOB list. */ static inline bool end_of_hob(const struct hob_header *hdr) { @@ -169,7 +169,7 @@ static inline bool end_of_hob(const struct hob_header *hdr) * * @hdr: A pointer to a HOB. * - * @return: A pointer to the data buffer in a HOB. + * @return A pointer to the data buffer in a HOB. */ static inline void *get_guid_hob_data(const struct hob_header *hdr) { @@ -185,7 +185,7 @@ static inline void *get_guid_hob_data(const struct hob_header *hdr) * * @hdr: A pointer to a HOB. * - * @return: The size of the data buffer. + * @return The size of the data buffer. */ static inline u16 get_guid_hob_data_size(const struct hob_header *hdr) { @@ -198,7 +198,7 @@ static inline u16 get_guid_hob_data_size(const struct hob_header *hdr) * @type: HOB type to search * @hob_list: A pointer to the HOB list * - * @retval: A HOB object with matching type; Otherwise NULL. + * @return A HOB object with matching type; Otherwise NULL. */ const struct hob_header *hob_get_next_hob(uint type, const void *hob_list); @@ -208,7 +208,7 @@ const struct hob_header *hob_get_next_hob(uint type, const void *hob_list); * @guid: GUID to search * @hob_list: A pointer to the HOB list * - * @retval: A HOB object with matching GUID; Otherwise NULL. + * @return A HOB object with matching GUID; Otherwise NULL. */ const struct hob_header *hob_get_next_guid_hob(const efi_guid_t *guid, const void *hob_list); @@ -221,8 +221,8 @@ const struct hob_header *hob_get_next_guid_hob(const efi_guid_t *guid, * If the GUID HOB is located, the length will be updated. * @guid A pointer to HOB GUID. * - * @retval NULL: Failed to find the GUID HOB. - * @retval others: GUID HOB data buffer pointer. + * @return NULL: Failed to find the GUID HOB. + * @return others: GUID HOB data buffer pointer. */ void *hob_get_guid_hob_data(const void *hob_list, u32 *len, const efi_guid_t *guid); diff --git a/arch/x86/lib/hob.c b/arch/x86/lib/hob.c index dcee29b04c..f2c47240ee 100644 --- a/arch/x86/lib/hob.c +++ b/arch/x86/lib/hob.c @@ -13,7 +13,7 @@ * @type: HOB type to search * @hob_list: A pointer to the HOB list * - * @retval: A HOB object with matching type; Otherwise NULL. + * @return A HOB object with matching type; Otherwise NULL. */ const struct hob_header *hob_get_next_hob(uint type, const void *hob_list) { @@ -38,7 +38,7 @@ const struct hob_header *hob_get_next_hob(uint type, const void *hob_list) * @guid: GUID to search * @hob_list: A pointer to the HOB list * - * @retval: A HOB object with matching GUID; Otherwise NULL. + * @return A HOB object with matching GUID; Otherwise NULL. */ const struct hob_header *hob_get_next_guid_hob(const efi_guid_t *guid, const void *hob_list) @@ -65,8 +65,8 @@ const struct hob_header *hob_get_next_guid_hob(const efi_guid_t *guid, * If the GUID HOB is located, the length will be updated. * @guid A pointer to HOB GUID. * - * @retval NULL: Failed to find the GUID HOB. - * @retval others: GUID HOB data buffer pointer. + * @return NULL: Failed to find the GUID HOB. + * @return others: GUID HOB data buffer pointer. */ void *hob_get_guid_hob_data(const void *hob_list, u32 *len, const efi_guid_t *guid) -- cgit From e9de4a7cd31a08d7bd2afa842db5aca57b3a37cb Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 24 Aug 2019 14:10:32 -0600 Subject: x86: fsp: Move common dram functions into a common file Most of the DRAM functionality can be shared between FSP1 and FSP2. Move it into a shared file. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng [bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly] Signed-off-by: Bin Meng --- arch/x86/include/asm/fsp/fsp_support.h | 9 ++++ arch/x86/lib/Makefile | 1 + arch/x86/lib/fsp/Makefile | 5 ++ arch/x86/lib/fsp/fsp_dram.c | 90 ++++++++++++++++++++++++++++++++++ arch/x86/lib/fsp1/fsp_dram.c | 83 +++---------------------------- 5 files changed, 111 insertions(+), 77 deletions(-) create mode 100644 arch/x86/lib/fsp/Makefile create mode 100644 arch/x86/lib/fsp/fsp_dram.c (limited to 'arch/x86') diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h index a6b32bf95d..215b0f7c9d 100644 --- a/arch/x86/include/asm/fsp/fsp_support.h +++ b/arch/x86/include/asm/fsp/fsp_support.h @@ -122,4 +122,13 @@ void *fsp_get_graphics_info(const void *hob_list, u32 *len); */ int fsp_init_phase_pci(void); +/** + * fsp_scan_for_ram_size() - Scan the HOB list to find the RAM size + * + * This sets gd->ram_size based on what it finds. + * + * @return 0 if OK, -ve on error + */ +int fsp_scan_for_ram_size(void); + #endif diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index a8c7448ee4..ca0ca1066b 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -43,6 +43,7 @@ ifndef CONFIG_SPL_BUILD obj-$(CONFIG_CMD_ZBOOT) += zimage.o endif obj-$(CONFIG_USE_HOB) += hob.o +obj-$(CONFIG_HAVE_FSP) += fsp/ obj-$(CONFIG_FSP_VERSION1) += fsp1/ obj-$(CONFIG_FSP_VERSION2) += fsp2/ diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile new file mode 100644 index 0000000000..e2160653de --- /dev/null +++ b/arch/x86/lib/fsp/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2019 Google LLC + +obj-y += fsp_dram.o diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c new file mode 100644 index 0000000000..8fe1e0bf73 --- /dev/null +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2014, Bin Meng + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int fsp_scan_for_ram_size(void) +{ + phys_size_t ram_size = 0; + const struct hob_header *hdr; + struct hob_res_desc *res_desc; + + hdr = gd->arch.hob_list; + while (!end_of_hob(hdr)) { + if (hdr->type == HOB_TYPE_RES_DESC) { + res_desc = (struct hob_res_desc *)hdr; + if (res_desc->type == RES_SYS_MEM || + res_desc->type == RES_MEM_RESERVED) + ram_size += res_desc->len; + } + hdr = get_next_hob(hdr); + } + + gd->ram_size = ram_size; + post_code(POST_DRAM); + + return 0; +}; + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = gd->ram_size; + + return 0; +} + +unsigned int install_e820_map(unsigned int max_entries, + struct e820_entry *entries) +{ + unsigned int num_entries = 0; + const struct hob_header *hdr; + struct hob_res_desc *res_desc; + + hdr = gd->arch.hob_list; + + while (!end_of_hob(hdr)) { + if (hdr->type == HOB_TYPE_RES_DESC) { + res_desc = (struct hob_res_desc *)hdr; + entries[num_entries].addr = res_desc->phys_start; + entries[num_entries].size = res_desc->len; + + if (res_desc->type == RES_SYS_MEM) + entries[num_entries].type = E820_RAM; + else if (res_desc->type == RES_MEM_RESERVED) + entries[num_entries].type = E820_RESERVED; + + num_entries++; + } + hdr = get_next_hob(hdr); + } + + /* Mark PCIe ECAM address range as reserved */ + entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE; + entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE; + entries[num_entries].type = E820_RESERVED; + num_entries++; + +#ifdef CONFIG_HAVE_ACPI_RESUME + /* + * Everything between U-Boot's stack and ram top needs to be + * reserved in order for ACPI S3 resume to work. + */ + entries[num_entries].addr = gd->start_addr_sp - CONFIG_STACK_SIZE; + entries[num_entries].size = gd->ram_top - gd->start_addr_sp + + CONFIG_STACK_SIZE; + entries[num_entries].type = E820_RESERVED; + num_entries++; +#endif + + return num_entries; +} diff --git a/arch/x86/lib/fsp1/fsp_dram.c b/arch/x86/lib/fsp1/fsp_dram.c index 75341bc528..6a3349b42a 100644 --- a/arch/x86/lib/fsp1/fsp_dram.c +++ b/arch/x86/lib/fsp1/fsp_dram.c @@ -4,33 +4,16 @@ */ #include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; +#include int dram_init(void) { - phys_size_t ram_size = 0; - const struct hob_header *hdr; - struct hob_res_desc *res_desc; - - hdr = gd->arch.hob_list; - while (!end_of_hob(hdr)) { - if (hdr->type == HOB_TYPE_RES_DESC) { - res_desc = (struct hob_res_desc *)hdr; - if (res_desc->type == RES_SYS_MEM || - res_desc->type == RES_MEM_RESERVED) { - ram_size += res_desc->len; - } - } - hdr = get_next_hob(hdr); - } + int ret; - gd->ram_size = ram_size; - post_code(POST_DRAM); + /* The FSP has already set up DRAM, so grab the info we need */ + ret = fsp_scan_for_ram_size(); + if (ret) + return ret; if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) gd->arch.mrc_output = fsp_get_nvs_data(gd->arch.hob_list, @@ -39,14 +22,6 @@ int dram_init(void) return 0; } -int dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = 0; - gd->bd->bi_dram[0].size = gd->ram_size; - - return 0; -} - /* * This function looks for the highest region of memory lower than 4GB which * has enough space for U-Boot where U-Boot is aligned on a page boundary. @@ -59,49 +34,3 @@ ulong board_get_usable_ram_top(ulong total_size) { return fsp_get_usable_lowmem_top(gd->arch.hob_list); } - -unsigned int install_e820_map(unsigned int max_entries, - struct e820_entry *entries) -{ - unsigned int num_entries = 0; - const struct hob_header *hdr; - struct hob_res_desc *res_desc; - - hdr = gd->arch.hob_list; - - while (!end_of_hob(hdr)) { - if (hdr->type == HOB_TYPE_RES_DESC) { - res_desc = (struct hob_res_desc *)hdr; - entries[num_entries].addr = res_desc->phys_start; - entries[num_entries].size = res_desc->len; - - if (res_desc->type == RES_SYS_MEM) - entries[num_entries].type = E820_RAM; - else if (res_desc->type == RES_MEM_RESERVED) - entries[num_entries].type = E820_RESERVED; - - num_entries++; - } - hdr = get_next_hob(hdr); - } - - /* Mark PCIe ECAM address range as reserved */ - entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE; - entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE; - entries[num_entries].type = E820_RESERVED; - num_entries++; - -#ifdef CONFIG_HAVE_ACPI_RESUME - /* - * Everything between U-Boot's stack and ram top needs to be - * reserved in order for ACPI S3 resume to work. - */ - entries[num_entries].addr = gd->start_addr_sp - CONFIG_STACK_SIZE; - entries[num_entries].size = gd->ram_top - gd->start_addr_sp + \ - CONFIG_STACK_SIZE; - entries[num_entries].type = E820_RESERVED; - num_entries++; -#endif - - return num_entries; -} -- cgit From b2d544a15d2edf8199e45e06c44b3e99ace906bc Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:11:30 -0600 Subject: x86: Move common fsp functions into a common file Some of this file can be shared between FSP1 and FSP2. Move it into a shared file. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/x86/include/asm/fsp/fsp_support.h | 17 ++++++ arch/x86/include/asm/fsp1/fsp_support.h | 10 --- arch/x86/lib/fsp/Makefile | 1 + arch/x86/lib/fsp/fsp_common.c | 104 ++++++++++++++++++++++++++++++++ arch/x86/lib/fsp1/fsp_common.c | 87 -------------------------- 5 files changed, 122 insertions(+), 97 deletions(-) create mode 100644 arch/x86/lib/fsp/fsp_common.c (limited to 'arch/x86') diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h index 215b0f7c9d..8dea2e71ea 100644 --- a/arch/x86/include/asm/fsp/fsp_support.h +++ b/arch/x86/include/asm/fsp/fsp_support.h @@ -131,4 +131,21 @@ int fsp_init_phase_pci(void); */ int fsp_scan_for_ram_size(void); +/** + * fsp_prepare_mrc_cache() - Find the DRAM training data from the MRC cache + * + * @return pointer to data, or NULL if no cache or no data found in the cache + */ +void *fsp_prepare_mrc_cache(void); + +/** + * fsp_notify() - FSP notification wrapper function + * + * @fsp_hdr: Pointer to FSP information header + * @phase: FSP initialization phase defined in enum fsp_phase + * + * @return compatible status code with EFI_STATUS defined in PI spec + */ +u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase); + #endif diff --git a/arch/x86/include/asm/fsp1/fsp_support.h b/arch/x86/include/asm/fsp1/fsp_support.h index 236c167fc8..a44a5504a4 100644 --- a/arch/x86/include/asm/fsp1/fsp_support.h +++ b/arch/x86/include/asm/fsp1/fsp_support.h @@ -46,16 +46,6 @@ void fsp_continue(u32 status, void *hob_list); */ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf); -/** - * fsp_notify() - FSP notification wrapper function - * - * @fsp_hdr: Pointer to FSP information header - * @phase: FSP initialization phase defined in enum fsp_phase - * - * @return compatible status code with EFI_STATUS defined in PI spec - */ -u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase); - /** * fsp_get_bootloader_tmp_mem() - retrieves temporary stack buffer and size * diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile index e2160653de..e7a8427c2e 100644 --- a/arch/x86/lib/fsp/Makefile +++ b/arch/x86/lib/fsp/Makefile @@ -2,4 +2,5 @@ # # Copyright 2019 Google LLC +obj-y += fsp_common.o obj-y += fsp_dram.o diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c new file mode 100644 index 0000000000..6678d75ffd --- /dev/null +++ b/arch/x86/lib/fsp/fsp_common.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2014, Bin Meng + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkcpu(void) +{ + return 0; +} + +int print_cpuinfo(void) +{ + post_code(POST_CPU_INFO); + return default_print_cpuinfo(); +} + +int fsp_init_phase_pci(void) +{ + u32 status; + + /* call into FspNotify */ + debug("Calling into FSP (notify phase INIT_PHASE_PCI): "); + status = fsp_notify(NULL, INIT_PHASE_PCI); + if (status) + debug("fail, error code %x\n", status); + else + debug("OK\n"); + + return status ? -EPERM : 0; +} + +void board_final_cleanup(void) +{ + u32 status; + + /* call into FspNotify */ + debug("Calling into FSP (notify phase INIT_PHASE_BOOT): "); + status = fsp_notify(NULL, INIT_PHASE_BOOT); + if (status) + debug("fail, error code %x\n", status); + else + debug("OK\n"); +} + +void *fsp_prepare_mrc_cache(void) +{ + struct mrc_data_container *cache; + struct mrc_region entry; + int ret; + + ret = mrccache_get_region(NULL, &entry); + if (ret) + return NULL; + + cache = mrccache_find_current(&entry); + if (!cache) + return NULL; + + debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__, + cache->data, cache->data_size, cache->checksum); + + return cache->data; +} + +#ifdef CONFIG_HAVE_ACPI_RESUME +int fsp_save_s3_stack(void) +{ + struct udevice *dev; + int ret; + + if (gd->arch.prev_sleep_state == ACPI_S3) + return 0; + + ret = uclass_get_device(UCLASS_RTC, 0, &dev); + if (ret) { + debug("Cannot find RTC: err=%d\n", ret); + return -ENODEV; + } + + /* Save the stack address to CMOS */ + ret = rtc_write32(dev, CMOS_FSP_STACK_ADDR, gd->start_addr_sp); + if (ret) { + debug("Save stack address to CMOS: err=%d\n", ret); + return -EIO; + } + + return 0; +} +#endif diff --git a/arch/x86/lib/fsp1/fsp_common.c b/arch/x86/lib/fsp1/fsp_common.c index bfd76dccba..285ef72ebf 100644 --- a/arch/x86/lib/fsp1/fsp_common.c +++ b/arch/x86/lib/fsp1/fsp_common.c @@ -18,93 +18,6 @@ DECLARE_GLOBAL_DATA_PTR; -int checkcpu(void) -{ - return 0; -} - -int print_cpuinfo(void) -{ - post_code(POST_CPU_INFO); - return default_print_cpuinfo(); -} - -int fsp_init_phase_pci(void) -{ - u32 status; - - /* call into FspNotify */ - debug("Calling into FSP (notify phase INIT_PHASE_PCI): "); - status = fsp_notify(NULL, INIT_PHASE_PCI); - if (status) - debug("fail, error code %x\n", status); - else - debug("OK\n"); - - return status ? -EPERM : 0; -} - -void board_final_cleanup(void) -{ - u32 status; - - /* call into FspNotify */ - debug("Calling into FSP (notify phase INIT_PHASE_BOOT): "); - status = fsp_notify(NULL, INIT_PHASE_BOOT); - if (status) - debug("fail, error code %x\n", status); - else - debug("OK\n"); - - return; -} - -static __maybe_unused void *fsp_prepare_mrc_cache(void) -{ - struct mrc_data_container *cache; - struct mrc_region entry; - int ret; - - ret = mrccache_get_region(NULL, &entry); - if (ret) - return NULL; - - cache = mrccache_find_current(&entry); - if (!cache) - return NULL; - - debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__, - cache->data, cache->data_size, cache->checksum); - - return cache->data; -} - -#ifdef CONFIG_HAVE_ACPI_RESUME -int fsp_save_s3_stack(void) -{ - struct udevice *dev; - int ret; - - if (gd->arch.prev_sleep_state == ACPI_S3) - return 0; - - ret = uclass_get_device(UCLASS_RTC, 0, &dev); - if (ret) { - debug("Cannot find RTC: err=%d\n", ret); - return -ENODEV; - } - - /* Save the stack address to CMOS */ - ret = rtc_write32(dev, CMOS_FSP_STACK_ADDR, gd->start_addr_sp); - if (ret) { - debug("Save stack address to CMOS: err=%d\n", ret); - return -EIO; - } - - return 0; -} -#endif - int arch_fsp_init(void) { void *nvs; -- cgit From 62888d840fb99d0375dc33ef7b3404377f451bcf Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:11:31 -0600 Subject: x86: fsp: Move common support functions into a common file Some of this file can be shared between FSP1 and FSP2. Move it into a shared file. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/x86/lib/fsp/Makefile | 1 + arch/x86/lib/fsp/fsp_support.c | 176 ++++++++++++++++++++++++++++++++++++++++ arch/x86/lib/fsp1/fsp_support.c | 167 -------------------------------------- 3 files changed, 177 insertions(+), 167 deletions(-) create mode 100644 arch/x86/lib/fsp/fsp_support.c (limited to 'arch/x86') diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile index e7a8427c2e..9e34856473 100644 --- a/arch/x86/lib/fsp/Makefile +++ b/arch/x86/lib/fsp/Makefile @@ -4,3 +4,4 @@ obj-y += fsp_common.o obj-y += fsp_dram.o +obj-y += fsp_support.o diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c new file mode 100644 index 0000000000..014de35e56 --- /dev/null +++ b/arch/x86/lib/fsp/fsp_support.c @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: Intel +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + */ + +#include +#include +#include + +u32 fsp_get_usable_lowmem_top(const void *hob_list) +{ + const struct hob_header *hdr; + struct hob_res_desc *res_desc; + phys_addr_t phys_start; + u32 top; +#ifdef CONFIG_FSP_BROKEN_HOB + struct hob_mem_alloc *res_mem; + phys_addr_t mem_base = 0; +#endif + + /* Get the HOB list for processing */ + hdr = hob_list; + + /* * Collect memory ranges */ + top = FSP_LOWMEM_BASE; + while (!end_of_hob(hdr)) { + if (hdr->type == HOB_TYPE_RES_DESC) { + res_desc = (struct hob_res_desc *)hdr; + if (res_desc->type == RES_SYS_MEM) { + phys_start = res_desc->phys_start; + /* Need memory above 1MB to be collected here */ + if (phys_start >= FSP_LOWMEM_BASE && + phys_start < (phys_addr_t)FSP_HIGHMEM_BASE) + top += (u32)(res_desc->len); + } + } + +#ifdef CONFIG_FSP_BROKEN_HOB + /* + * Find out the lowest memory base address allocated by FSP + * for the boot service data + */ + if (hdr->type == HOB_TYPE_MEM_ALLOC) { + res_mem = (struct hob_mem_alloc *)hdr; + if (!mem_base) + mem_base = res_mem->mem_base; + if (res_mem->mem_base < mem_base) + mem_base = res_mem->mem_base; + } +#endif + + hdr = get_next_hob(hdr); + } + +#ifdef CONFIG_FSP_BROKEN_HOB + /* + * Check whether the memory top address is below the FSP HOB list. + * If not, use the lowest memory base address allocated by FSP as + * the memory top address. This is to prevent U-Boot relocation + * overwrites the important boot service data which is used by FSP, + * otherwise the subsequent call to fsp_notify() will fail. + */ + if (top > (u32)hob_list) { + debug("Adjust memory top address due to a buggy FSP\n"); + top = (u32)mem_base; + } +#endif + + return top; +} + +u64 fsp_get_usable_highmem_top(const void *hob_list) +{ + const struct hob_header *hdr; + struct hob_res_desc *res_desc; + phys_addr_t phys_start; + u64 top; + + /* Get the HOB list for processing */ + hdr = hob_list; + + /* Collect memory ranges */ + top = FSP_HIGHMEM_BASE; + while (!end_of_hob(hdr)) { + if (hdr->type == HOB_TYPE_RES_DESC) { + res_desc = (struct hob_res_desc *)hdr; + if (res_desc->type == RES_SYS_MEM) { + phys_start = res_desc->phys_start; + /* Need memory above 4GB to be collected here */ + if (phys_start >= (phys_addr_t)FSP_HIGHMEM_BASE) + top += (u32)(res_desc->len); + } + } + hdr = get_next_hob(hdr); + } + + return top; +} + +u64 fsp_get_reserved_mem_from_guid(const void *hob_list, u64 *len, + const efi_guid_t *guid) +{ + const struct hob_header *hdr; + struct hob_res_desc *res_desc; + + /* Get the HOB list for processing */ + hdr = hob_list; + + /* Collect memory ranges */ + while (!end_of_hob(hdr)) { + if (hdr->type == HOB_TYPE_RES_DESC) { + res_desc = (struct hob_res_desc *)hdr; + if (res_desc->type == RES_MEM_RESERVED) { + if (!guidcmp(&res_desc->owner, guid)) { + if (len) + *len = (u32)(res_desc->len); + + return (u64)(res_desc->phys_start); + } + } + } + hdr = get_next_hob(hdr); + } + + return 0; +} + +u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len) +{ + const efi_guid_t guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID; + u64 length; + u32 base; + + base = (u32)fsp_get_reserved_mem_from_guid(hob_list, + &length, &guid); + if (len && base) + *len = (u32)length; + + return base; +} + +u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len) +{ + const efi_guid_t guid = FSP_HOB_RESOURCE_OWNER_TSEG_GUID; + u64 length; + u32 base; + + base = (u32)fsp_get_reserved_mem_from_guid(hob_list, + &length, &guid); + if (len && base) + *len = (u32)length; + + return base; +} + +void *fsp_get_nvs_data(const void *hob_list, u32 *len) +{ + const efi_guid_t guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID; + + return hob_get_guid_hob_data(hob_list, len, &guid); +} + +void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len) +{ + const efi_guid_t guid = FSP_BOOTLOADER_TEMP_MEM_HOB_GUID; + + return hob_get_guid_hob_data(hob_list, len, &guid); +} + +void *fsp_get_graphics_info(const void *hob_list, u32 *len) +{ + const efi_guid_t guid = FSP_GRAPHICS_INFO_HOB_GUID; + + return hob_get_guid_hob_data(hob_list, len, &guid); +} diff --git a/arch/x86/lib/fsp1/fsp_support.c b/arch/x86/lib/fsp1/fsp_support.c index b5b7d664a1..c7a2c73846 100644 --- a/arch/x86/lib/fsp1/fsp_support.c +++ b/arch/x86/lib/fsp1/fsp_support.c @@ -197,170 +197,3 @@ u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase) return status; } - -u32 fsp_get_usable_lowmem_top(const void *hob_list) -{ - const struct hob_header *hdr; - struct hob_res_desc *res_desc; - phys_addr_t phys_start; - u32 top; -#ifdef CONFIG_FSP_BROKEN_HOB - struct hob_mem_alloc *res_mem; - phys_addr_t mem_base = 0; -#endif - - /* Get the HOB list for processing */ - hdr = hob_list; - - /* * Collect memory ranges */ - top = FSP_LOWMEM_BASE; - while (!end_of_hob(hdr)) { - if (hdr->type == HOB_TYPE_RES_DESC) { - res_desc = (struct hob_res_desc *)hdr; - if (res_desc->type == RES_SYS_MEM) { - phys_start = res_desc->phys_start; - /* Need memory above 1MB to be collected here */ - if (phys_start >= FSP_LOWMEM_BASE && - phys_start < (phys_addr_t)FSP_HIGHMEM_BASE) - top += (u32)(res_desc->len); - } - } - -#ifdef CONFIG_FSP_BROKEN_HOB - /* - * Find out the lowest memory base address allocated by FSP - * for the boot service data - */ - if (hdr->type == HOB_TYPE_MEM_ALLOC) { - res_mem = (struct hob_mem_alloc *)hdr; - if (!mem_base) - mem_base = res_mem->mem_base; - if (res_mem->mem_base < mem_base) - mem_base = res_mem->mem_base; - } -#endif - - hdr = get_next_hob(hdr); - } - -#ifdef CONFIG_FSP_BROKEN_HOB - /* - * Check whether the memory top address is below the FSP HOB list. - * If not, use the lowest memory base address allocated by FSP as - * the memory top address. This is to prevent U-Boot relocation - * overwrites the important boot service data which is used by FSP, - * otherwise the subsequent call to fsp_notify() will fail. - */ - if (top > (u32)hob_list) { - debug("Adjust memory top address due to a buggy FSP\n"); - top = (u32)mem_base; - } -#endif - - return top; -} - -u64 fsp_get_usable_highmem_top(const void *hob_list) -{ - const struct hob_header *hdr; - struct hob_res_desc *res_desc; - phys_addr_t phys_start; - u64 top; - - /* Get the HOB list for processing */ - hdr = hob_list; - - /* Collect memory ranges */ - top = FSP_HIGHMEM_BASE; - while (!end_of_hob(hdr)) { - if (hdr->type == HOB_TYPE_RES_DESC) { - res_desc = (struct hob_res_desc *)hdr; - if (res_desc->type == RES_SYS_MEM) { - phys_start = res_desc->phys_start; - /* Need memory above 4GB to be collected here */ - if (phys_start >= (phys_addr_t)FSP_HIGHMEM_BASE) - top += (u32)(res_desc->len); - } - } - hdr = get_next_hob(hdr); - } - - return top; -} - -u64 fsp_get_reserved_mem_from_guid(const void *hob_list, u64 *len, - const efi_guid_t *guid) -{ - const struct hob_header *hdr; - struct hob_res_desc *res_desc; - - /* Get the HOB list for processing */ - hdr = hob_list; - - /* Collect memory ranges */ - while (!end_of_hob(hdr)) { - if (hdr->type == HOB_TYPE_RES_DESC) { - res_desc = (struct hob_res_desc *)hdr; - if (res_desc->type == RES_MEM_RESERVED) { - if (!guidcmp(&res_desc->owner, guid)) { - if (len) - *len = (u32)(res_desc->len); - - return (u64)(res_desc->phys_start); - } - } - } - hdr = get_next_hob(hdr); - } - - return 0; -} - -u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len) -{ - const efi_guid_t guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID; - u64 length; - u32 base; - - base = (u32)fsp_get_reserved_mem_from_guid(hob_list, - &length, &guid); - if ((len != 0) && (base != 0)) - *len = (u32)length; - - return base; -} - -u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len) -{ - const efi_guid_t guid = FSP_HOB_RESOURCE_OWNER_TSEG_GUID; - u64 length; - u32 base; - - base = (u32)fsp_get_reserved_mem_from_guid(hob_list, - &length, &guid); - if ((len != 0) && (base != 0)) - *len = (u32)length; - - return base; -} - -void *fsp_get_nvs_data(const void *hob_list, u32 *len) -{ - const efi_guid_t guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID; - - return hob_get_guid_hob_data(hob_list, len, &guid); -} - -void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len) -{ - const efi_guid_t guid = FSP_BOOTLOADER_TEMP_MEM_HOB_GUID; - - return hob_get_guid_hob_data(hob_list, len, &guid); -} - -void *fsp_get_graphics_info(const void *hob_list, u32 *len) -{ - const efi_guid_t guid = FSP_GRAPHICS_INFO_HOB_GUID; - - return hob_get_guid_hob_data(hob_list, len, &guid); -} -- cgit From ceec18491c665bccb6702ac1ba835ca75e5e58a9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:11:33 -0600 Subject: x86: fsp: Add a few more definitions for FSP2 Add definitions for the FSP signature and the FSP init phase. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/include/asm/fsp/fsp_infoheader.h | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'arch/x86') diff --git a/arch/x86/include/asm/fsp/fsp_infoheader.h b/arch/x86/include/asm/fsp/fsp_infoheader.h index 86f78014b7..e72c052ed1 100644 --- a/arch/x86/include/asm/fsp/fsp_infoheader.h +++ b/arch/x86/include/asm/fsp/fsp_infoheader.h @@ -33,6 +33,19 @@ struct __packed fsp_header { #define FSP_HEADER_REVISION_1 1 #define FSP_HEADER_REVISION_2 2 -#define FSP_ATTR_GRAPHICS_SUPPORT (1 << 0) +enum fsp_type { + FSP_ATTR_COMP_TYPE_FSP_T = 1, + FSP_ATTR_COMP_TYPE_FSP_M = 2, + FSP_ATTR_COMP_TYPE_FSP_S = 3, +}; + +enum { + FSP_ATTR_GRAPHICS_SUPPORT = 1 << 0, + FSP_ATTR_COMP_TYPE_SHIFT = 28, + FSP_ATTR_COMP_TYPE_MASK = 0xfU << FSP_ATTR_COMP_TYPE_SHIFT, + +}; + +#define EFI_FSPH_SIGNATURE SIGNATURE_32('F', 'S', 'P', 'H') #endif -- cgit From 46dd41fa5a8f08af903c7f0cfde9abfc16d7efe3 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:11:34 -0600 Subject: x86: fsp: Add access to variable MRC data With FSP2 the non-volatile storage used by the FSP to init memory can be split into a fixed piece (determined at compile time) and a variable piece (determined at run time). Add support for reading the latter. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/include/asm/fsp/fsp_hob.h | 4 ++++ arch/x86/include/asm/fsp/fsp_support.h | 12 ++++++++++++ arch/x86/lib/fsp/fsp_support.c | 7 +++++++ 3 files changed, 23 insertions(+) (limited to 'arch/x86') diff --git a/arch/x86/include/asm/fsp/fsp_hob.h b/arch/x86/include/asm/fsp/fsp_hob.h index 3bb79c4b67..d248520e97 100644 --- a/arch/x86/include/asm/fsp/fsp_hob.h +++ b/arch/x86/include/asm/fsp/fsp_hob.h @@ -69,6 +69,10 @@ struct __packed hob_graphics_info { EFI_GUID(0x721acf02, 0x4d77, 0x4c2a, \ 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0) +#define FSP_VARIABLE_NV_DATA_HOB_GUID \ + EFI_GUID(0xa034147d, 0x690c, 0x4154, \ + 0x8d, 0xe6, 0xc0, 0x44, 0x64, 0x1d, 0xe9, 0x42) + #define FSP_BOOTLOADER_TEMP_MEM_HOB_GUID \ EFI_GUID(0xbbcff46c, 0xc8d3, 0x4113, \ 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e) diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h index 8dea2e71ea..4ac27d26f5 100644 --- a/arch/x86/include/asm/fsp/fsp_support.h +++ b/arch/x86/include/asm/fsp/fsp_support.h @@ -103,6 +103,18 @@ u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len); */ void *fsp_get_nvs_data(const void *hob_list, u32 *len); +/** + * fsp_get_var_nvs_data() - get FSP variable Non-volatile Storage HOB buffer + * + * @hob_list: A HOB list pointer. + * @len: A pointer to the NVS data buffer length. + * If the HOB is located, the length will be updated. + * + * @return NULL: Failed to find the NVS HOB. + * @return others: FSP NVS data buffer pointer. + */ +void *fsp_get_var_nvs_data(const void *hob_list, u32 *len); + /** * fsp_get_graphics_info() - retrieves graphics information. * diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c index 014de35e56..983888fd74 100644 --- a/arch/x86/lib/fsp/fsp_support.c +++ b/arch/x86/lib/fsp/fsp_support.c @@ -161,6 +161,13 @@ void *fsp_get_nvs_data(const void *hob_list, u32 *len) return hob_get_guid_hob_data(hob_list, len, &guid); } +void *fsp_get_var_nvs_data(const void *hob_list, u32 *len) +{ + const efi_guid_t guid = FSP_VARIABLE_NV_DATA_HOB_GUID; + + return hob_get_guid_hob_data(hob_list, len, &guid); +} + void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len) { const efi_guid_t guid = FSP_BOOTLOADER_TEMP_MEM_HOB_GUID; -- cgit From d3abc5d1ee5ffea5647a22ddfff82c01d507f962 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:11:35 -0600 Subject: x86: Move common Intel CPU info code into a function Add cpu_intel_get_info() to find out the CPU info on modern Intel CPUs. Signed-off-by: Simon Glass Reviewed-by: Bin Meng [bmeng: add parameter and return value descriptions] Signed-off-by: Bin Meng --- arch/x86/cpu/broadwell/cpu_full.c | 9 +-------- arch/x86/cpu/intel_common/cpu.c | 13 +++++++++++++ arch/x86/cpu/ivybridge/model_206ax.c | 8 ++------ arch/x86/include/asm/cpu_common.h | 16 ++++++++++++++++ 4 files changed, 32 insertions(+), 14 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/cpu/broadwell/cpu_full.c b/arch/x86/cpu/broadwell/cpu_full.c index c1db184549..d8b8482658 100644 --- a/arch/x86/cpu/broadwell/cpu_full.c +++ b/arch/x86/cpu/broadwell/cpu_full.c @@ -645,14 +645,7 @@ void cpu_set_power_limits(int power_limit_1_time) static int broadwell_get_info(struct udevice *dev, struct cpu_info *info) { - msr_t msr; - - msr = msr_read(IA32_PERF_CTL); - info->cpu_freq = ((msr.lo >> 8) & 0xff) * BROADWELL_BCLK * 1000000; - info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU | - 1 << CPU_FEAT_UCODE | 1 << CPU_FEAT_DEVICE_ID; - - return 0; + return cpu_intel_get_info(info, BROADWELL_BCLK); } static int broadwell_get_count(struct udevice *dev) diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c index d0ac17808c..9357626b5a 100644 --- a/arch/x86/cpu/intel_common/cpu.c +++ b/arch/x86/cpu/intel_common/cpu.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -110,3 +111,15 @@ int cpu_set_flex_ratio_to_tdp_nominal(void) /* Not reached */ return -EINVAL; } + +int cpu_intel_get_info(struct cpu_info *info, int bclk) +{ + msr_t msr; + + msr = msr_read(IA32_PERF_CTL); + info->cpu_freq = ((msr.lo >> 8) & 0xff) * bclk * 1000000; + info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU | + 1 << CPU_FEAT_UCODE | 1 << CPU_FEAT_DEVICE_ID; + + return 0; +} diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index 6edc3e233c..68e78e9478 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -436,12 +437,7 @@ static int model_206ax_init(struct udevice *dev) static int model_206ax_get_info(struct udevice *dev, struct cpu_info *info) { - msr_t msr; - - msr = msr_read(MSR_IA32_PERF_CTL); - info->cpu_freq = ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK * 1000000; - info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU | - 1 << CPU_FEAT_UCODE; + return cpu_intel_get_info(info, SANDYBRIDGE_BCLK); return 0; } diff --git a/arch/x86/include/asm/cpu_common.h b/arch/x86/include/asm/cpu_common.h index 4c91a5dace..5e398bec94 100644 --- a/arch/x86/include/asm/cpu_common.h +++ b/arch/x86/include/asm/cpu_common.h @@ -8,6 +8,8 @@ #define IA32_PERF_CTL 0x199 +struct cpu_info; + /** * cpu_common_init() - Set up common CPU init * @@ -31,4 +33,18 @@ int cpu_common_init(void); */ int cpu_set_flex_ratio_to_tdp_nominal(void); +/** + * cpu_intel_get_info() - Obtain CPU info for Intel CPUs + * + * Most Intel CPUs use the same MSR to obtain the clock speed, and use the same + * features. This function fills in these values, given the value of the base + * clock in MHz (typically this should be set to 100). + * + * @info: cpu_info struct to fill in + * @bclk_mz: the base clock in MHz + * + * @return 0 always + */ +int cpu_intel_get_info(struct cpu_info *info, int bclk_mz); + #endif -- cgit From 1eeb55755f4d50a9954d17cbb6f98b3285a9b976 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:11:36 -0600 Subject: x86: Add binman symbols to the image It is useful in SPL and TPL to access symbols from binman, such as the position and size of an entry in the ROM. Collect these symbols together in the SPL binaries. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/cpu/u-boot-spl.lds | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/x86') diff --git a/arch/x86/cpu/u-boot-spl.lds b/arch/x86/cpu/u-boot-spl.lds index f20c0b810d..c1e9bfbf66 100644 --- a/arch/x86/cpu/u-boot-spl.lds +++ b/arch/x86/cpu/u-boot-spl.lds @@ -35,6 +35,12 @@ SECTIONS . = ALIGN(4); __data_end = .; __init_end = .; + . = ALIGN(4); + .binman_sym_table : { + __binman_sym_start = .; + KEEP(*(SORT(.binman_sym*))); + __binman_sym_end = .; + } _image_binary_end = .; -- cgit From e46d00c77cd5a756e8cf3fae3b34eaa9ec012f0d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:11:37 -0600 Subject: x86: pci: Add a function to clear and set PCI config regs At present the x86 pre-DM equivalent of pci_bus_clrset_config32() does not exist. Add it to simplify PCI init code on x86. Also add the missing functions to this header. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/cpu/pci.c | 19 +++++++++++++++++++ arch/x86/include/asm/pci.h | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) (limited to 'arch/x86') diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c index c6218250e1..0ccde194d9 100644 --- a/arch/x86/cpu/pci.c +++ b/arch/x86/cpu/pci.c @@ -16,6 +16,10 @@ #include #include +/* + * TODO(sjg@chromium.org): Drop the first parameter from each of these + * functions since it is not used. + */ int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong *valuep, enum pci_size_t size) { @@ -54,6 +58,21 @@ int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, return 0; } +int pci_x86_clrset_config(struct udevice *bus, pci_dev_t bdf, uint offset, + ulong clr, ulong set, enum pci_size_t size) +{ + ulong value; + int ret; + + ret = pci_x86_read_config(bus, bdf, offset, &value, size); + if (ret) + return ret; + value &= ~clr; + value |= set; + + return pci_x86_write_config(bus, bdf, offset, value, size); +} + void pci_assign_irqs(int bus, int device, u8 irq[4]) { pci_dev_t bdf; diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index 118ac937d9..fb1edf3df7 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -17,12 +17,52 @@ #ifndef __ASSEMBLY__ +/** + * pci_x86_read_config() - Read a configuration value from a device + * + * This function can be called before PCI is set up in driver model. + * + * @bus: Bus to read from (ignored, can be NULL) + * @bdf: PCI device address: bus, device and function -see PCI_BDF() + * @offset: Register offset to read + * @valuep: Place to put the returned value + * @size: Access size + * @return 0 if OK, -ve on error + */ int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong *valuep, enum pci_size_t size); +/** + * pci_bus_write_config() - Write a configuration value to a device + * + * This function can be called before PCI is set up in driver model. + * + * @bus: Bus to read from (ignored, can be NULL) + * @bdf: PCI device address: bus, device and function -see PCI_BDF() + * @offset: Register offset to write + * @value: Value to write + * @size: Access size + * @return 0 if OK, -ve on error + */ int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong value, enum pci_size_t size); +/** + * pci_bus_clrset_config32() - Update a configuration value for a device + * + * The register at @offset is updated to (oldvalue & ~clr) | set. This function + * can be called before PCI is set up in driver model. + * + * @bus: Bus to read from (ignored, can be NULL) + * @bdf: PCI device address: bus, device and function -see PCI_BDF() + * @offset: Register offset to update + * @clr: Bits to clear + * @set: Bits to set + * @return 0 if OK, -ve on error + */ +int pci_x86_clrset_config(struct udevice *bus, pci_dev_t bdf, uint offset, + ulong clr, ulong set, enum pci_size_t size); + /** * Assign IRQ number to a PCI device * -- cgit From 14dd93beb71727edf0c7ee288f2ee1ceceb6317a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:11:38 -0600 Subject: x86: spl: Use hang() instead of a while() loop Use the standard hang() function when booting fails since this implements the defined U-Boot behaviour for this situation. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/lib/spl.c | 3 +-- arch/x86/lib/tpl.c | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index 5d5d1a9ca7..01a96d294b 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -183,8 +183,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) printf("Jumping to 64-bit U-Boot: Note many features are missing\n"); ret = cpu_jump_to_64bit_uboot(spl_image->entry_point); debug("ret=%d\n", ret); - while (1) - ; + hang(); } #endif diff --git a/arch/x86/lib/tpl.c b/arch/x86/lib/tpl.c index 492a2d6521..3e662a8bda 100644 --- a/arch/x86/lib/tpl.c +++ b/arch/x86/lib/tpl.c @@ -108,8 +108,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) { printf("Jumping to U-Boot SPL at %lx\n", (ulong)spl_image->entry_point); jump_to_spl(spl_image->entry_point); - while (1) - ; + hang(); } void spl_board_init(void) -- cgit From daade119aa4b49d5ff6b1ebbdfeab0a8775c9344 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:11:39 -0600 Subject: x86: spl: Reduce priority of the basic SPL image loader This image loader works on systems where the flash is directly mapped to the last part of the 32-bit address space. On recent Intel systems (such as apollolake) this is not the case. Reduce the priority of this loader so that another one can override it. While we are here, rename the loader to BOOT_DEVICE_SPI_MMAP since BOOT_DEVICE_BOARD is not very descriptive. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/include/asm/spl.h | 3 +-- arch/x86/lib/spl.c | 5 +++-- arch/x86/lib/tpl.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/include/asm/spl.h b/arch/x86/include/asm/spl.h index 27432b2897..1bef4877eb 100644 --- a/arch/x86/include/asm/spl.h +++ b/arch/x86/include/asm/spl.h @@ -10,8 +10,7 @@ #define CONFIG_SPL_BOARD_LOAD_IMAGE enum { - BOOT_DEVICE_SPI = 10, - BOOT_DEVICE_BOARD, + BOOT_DEVICE_SPI_MMAP = 10, BOOT_DEVICE_CROS_VBOOT, }; diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index 01a96d294b..a739491303 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -11,6 +11,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -142,7 +143,7 @@ void board_init_f_r(void) u32 spl_boot_device(void) { - return BOOT_DEVICE_BOARD; + return BOOT_DEVICE_SPI_MMAP; } int spl_start_uboot(void) @@ -168,7 +169,7 @@ static int spl_board_load_image(struct spl_image_info *spl_image, return 0; } -SPL_LOAD_IMAGE_METHOD("SPI", 0, BOOT_DEVICE_BOARD, spl_board_load_image); +SPL_LOAD_IMAGE_METHOD("SPI", 5, BOOT_DEVICE_SPI_MMAP, spl_board_load_image); int spl_spi_load_image(void) { diff --git a/arch/x86/lib/tpl.c b/arch/x86/lib/tpl.c index 3e662a8bda..cfefa78045 100644 --- a/arch/x86/lib/tpl.c +++ b/arch/x86/lib/tpl.c @@ -71,7 +71,7 @@ void board_init_f_r(void) u32 spl_boot_device(void) { return IS_ENABLED(CONFIG_CHROMEOS) ? BOOT_DEVICE_CROS_VBOOT : - BOOT_DEVICE_BOARD; + BOOT_DEVICE_SPI_MMAP; } int spl_start_uboot(void) @@ -97,7 +97,7 @@ static int spl_board_load_image(struct spl_image_info *spl_image, return 0; } -SPL_LOAD_IMAGE_METHOD("SPI", 0, BOOT_DEVICE_BOARD, spl_board_load_image); +SPL_LOAD_IMAGE_METHOD("SPI", 5, BOOT_DEVICE_SPI_MMAP, spl_board_load_image); int spl_spi_load_image(void) { -- cgit From 12c81b2f4196ed7eb9f2d7d377b34280b1ca26c1 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:11:40 -0600 Subject: x86: spl: Move broadwell-specific code out of generic x86 spl When TPL is running, broadwell needs to do different init from SPL. There is no need for this code to be in the generic x86 SPL file, so move it to arch_cpu_init(). Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/cpu/broadwell/cpu.c | 5 +++++ arch/x86/cpu/broadwell/cpu_full.c | 7 +++++++ arch/x86/lib/spl.c | 5 ----- 3 files changed, 12 insertions(+), 5 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c index bb7c361408..bba8cd1e94 100644 --- a/arch/x86/cpu/broadwell/cpu.c +++ b/arch/x86/cpu/broadwell/cpu.c @@ -67,7 +67,12 @@ int arch_cpu_init(void) { post_code(POST_CPU_INIT); +#ifdef CONFIG_TPL + /* Do a mini-init if TPL has already done the full init */ + return x86_cpu_reinit_f(); +#else return x86_cpu_init_f(); +#endif } int checkcpu(void) diff --git a/arch/x86/cpu/broadwell/cpu_full.c b/arch/x86/cpu/broadwell/cpu_full.c index d8b8482658..bd0b2037fa 100644 --- a/arch/x86/cpu/broadwell/cpu_full.c +++ b/arch/x86/cpu/broadwell/cpu_full.c @@ -81,6 +81,13 @@ static const u8 power_limit_time_msr_to_sec[] = { [0x11] = 128, }; +#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) +int arch_cpu_init(void) +{ + return 0; +} +#endif + /* * The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index a739491303..2baac91383 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -40,12 +40,7 @@ static int x86_spl_init(void) debug("%s: spl_init() failed\n", __func__); return ret; } -#ifdef CONFIG_TPL - /* Do a mini-init if TPL has already done the full init */ - ret = x86_cpu_reinit_f(); -#else ret = arch_cpu_init(); -#endif if (ret) { debug("%s: arch_cpu_init() failed\n", __func__); return ret; -- cgit From c3863eadbc60d21b234ac5fb15c525b3cbc4f637 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:11:41 -0600 Subject: x86: fsp: Save usable RAM and hob_list in the handoff area The useable RAM is calculated when the RAM is inited. Save this value so that it can be easily used in U-Boot proper. Also save a pointer to the hob list so that it is accessible (before relocation only) in U-Boot proper. This avoids having to scan it in SPL, for everything U-Boot proper might need later. Signed-off-by: Simon Glass Reviewed-by: Bin Meng [bmeng: guard handoff_arch_save() with IS_ENABLED(CONFIG_USE_HOB)] Signed-off-by: Bin Meng --- arch/x86/cpu/intel_common/cpu_from_spl.c | 6 ++++++ arch/x86/include/asm/handoff.h | 8 ++++++++ arch/x86/lib/fsp/fsp_dram.c | 10 ++++++++++ 3 files changed, 24 insertions(+) (limited to 'arch/x86') diff --git a/arch/x86/cpu/intel_common/cpu_from_spl.c b/arch/x86/cpu/intel_common/cpu_from_spl.c index a6233c75ce..b7bb524162 100644 --- a/arch/x86/cpu/intel_common/cpu_from_spl.c +++ b/arch/x86/cpu/intel_common/cpu_from_spl.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -21,6 +22,11 @@ int arch_cpu_init(void) { int ret; +#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB) + struct spl_handoff *ho = gd->spl_handoff; + + gd->arch.hob_list = ho->arch.hob_list; +#endif ret = x86_cpu_reinit_f(); return ret; diff --git a/arch/x86/include/asm/handoff.h b/arch/x86/include/asm/handoff.h index 4d18d59efe..aec49b9b81 100644 --- a/arch/x86/include/asm/handoff.h +++ b/arch/x86/include/asm/handoff.h @@ -9,7 +9,15 @@ #ifndef __x86_asm_handoff_h #define __x86_asm_handoff_h +/** + * struct arch_spl_handoff - architecture-specific handoff info + * + * @usable_ram_top: Value returned by board_get_usable_ram_top() in SPL + * @hob_list: Start of FSP hand-off blocks (HOBs) + */ struct arch_spl_handoff { + ulong usable_ram_top; + void *hob_list; }; #endif diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 8fe1e0bf73..2d1023068f 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -88,3 +88,13 @@ unsigned int install_e820_map(unsigned int max_entries, return num_entries; } + +#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB) +int handoff_arch_save(struct spl_handoff *ho) +{ + ho->arch.usable_ram_top = fsp_get_usable_lowmem_top(gd->arch.hob_list); + ho->arch.hob_list = gd->arch.hob_list; + + return 0; +} +#endif -- cgit From 6172e94c3c4729347624626d71e4eaf96ff9dcb9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:11:43 -0600 Subject: x86: Change condition for using CAR At present we assume that CAR (Cache-as-RAM) is used if HOBs (Hand-off blocks) are not, since HOBs typically indicate that an FSP is in use, and FSPs handle the CAR init. However this is a bit indirect, and for FSP2 machines which use their own CAR implementation (such as apollolake) but use the FSP for other functions, the logic is wrong. To fix this, add a dedicated Kconfig option to indicate when CAR is used. Signed-off-by: Simon Glass Reviewed-by: Bin Meng [bmeng: fix a typo in the commit message] Signed-off-by: Bin Meng --- arch/x86/Kconfig | 8 ++++++++ arch/x86/cpu/start.S | 4 ++-- 2 files changed, 10 insertions(+), 2 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 314f8def7a..47bf28c434 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -364,6 +364,14 @@ config HAVE_FSP Note: Without this binary U-Boot will not be able to set up its SDRAM so will not boot. +config USE_CAR + bool "Use Cache-As-RAM (CAR) to get temporary RAM at start-up" + default y if !HAVE_FSP + help + Select this option if your board uses CAR init code, typically in a + car.S file, to get some initial memory for code execution. This is + common with Intel CPUs which don't use FSP. + choice prompt "FSP version" depends on HAVE_FSP diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 3c9bdf2a9d..9b76394274 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -90,7 +90,7 @@ early_board_init_ret: jmp car_init .globl car_init_ret car_init_ret: -#ifndef CONFIG_USE_HOB +#ifdef CONFIG_USE_CAR /* * We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM, * or fully initialised SDRAM - we really don't care which) @@ -130,7 +130,7 @@ car_init_ret: /* Get address of global_data */ mov %fs:0, %edx -#ifdef CONFIG_USE_HOB +#if defined(CONFIG_USE_HOB) && !defined(CONFIG_USE_CAR) /* Store the HOB list if we have one */ test %esi, %esi jz skip_hob -- cgit From 08deb6d36f0a830181a3acce5eaece9431a828c0 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:11:44 -0600 Subject: x86: Add more comments to the start-up code The full start-up sequence (TPL->SPL->U-Boot) can be a bit confusing since each phase has its own 'start' file. Add comments to explain this. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/cpu/start.S | 12 ++++++++++++ arch/x86/cpu/start_from_spl.S | 5 +++-- arch/x86/cpu/start_from_tpl.S | 3 ++- 3 files changed, 17 insertions(+), 3 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 9b76394274..01524635e9 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -2,6 +2,18 @@ /* * U-Boot - x86 Startup Code * + * This is always the first code to run from the U-Boot source. To spell it out: + * + * 1. When TPL (Tertiary Program Loader) is enabled, the boot flow is + * TPL->SPL->U-Boot and this file is used for TPL. Then start_from_tpl.S is used + * for SPL and start_from_spl.S is used for U-Boot proper. + * + * 2. When SPL (Secondary Program Loader) is enabled, but not TPL, the boot + * flow is SPL->U-Boot and this file is used for SPL. Then start_from_spl.S is + * used for U-Boot proper. + * + * 3. When neither TPL nor SPL is used, this file is used for U-Boot proper. + * * (C) Copyright 2008-2011 * Graeme Russ, * diff --git a/arch/x86/cpu/start_from_spl.S b/arch/x86/cpu/start_from_spl.S index 4d4e5d0758..a73b4d7c45 100644 --- a/arch/x86/cpu/start_from_spl.S +++ b/arch/x86/cpu/start_from_spl.S @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * 32-bit x86 Startup Code when running from SPL - * + * 32-bit x86 Startup Code when running from SPL. This is the startup code in + * U-Boot proper, when SPL is used. + * Copyright 2018 Google, Inc * Written by Simon Glass */ diff --git a/arch/x86/cpu/start_from_tpl.S b/arch/x86/cpu/start_from_tpl.S index 44b5363a68..9a4974a5f1 100644 --- a/arch/x86/cpu/start_from_tpl.S +++ b/arch/x86/cpu/start_from_tpl.S @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * 32-bit x86 Startup Code when running from TPL + * 32-bit x86 Startup Code when running from TPL. This is the startup code in + * SPL, when TPL is used. * * Copyright 2018 Google, Inc * Written by Simon Glass -- cgit From ebe002cd180c4b9f7f92720acaf13e712a1cce93 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:11:46 -0600 Subject: x86: Add various MTRR indexes and values Add some new MTRRs used by Apollolake as well as a mask for the MTRR type. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/include/asm/msr-index.h | 22 ++++++++++++++++++++++ arch/x86/include/asm/mtrr.h | 1 + 2 files changed, 23 insertions(+) (limited to 'arch/x86') diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 9c1dbe61d5..1a02d8c8fe 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -43,6 +43,12 @@ #define MSR_PIC_MSG_CONTROL 0x2e #define PLATFORM_INFO_SET_TDP (1 << 29) +#define MSR_MTRR_CAP_MSR 0x0fe +#define MSR_MTRR_CAP_SMRR (1 << 11) +#define MSR_MTRR_CAP_WC (1 << 10) +#define MSR_MTRR_CAP_FIX (1 << 8) +#define MSR_MTRR_CAP_VCNT 0xff + #define MSR_IA32_PERFCTR0 0x000000c1 #define MSR_IA32_PERFCTR1 0x000000c2 #define MSR_FSB_FREQ 0x000000cd @@ -67,6 +73,11 @@ #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) #define ENABLE_INDP_AUTOCM_MASK (1 << 3) +#define MSR_EMULATE_PM_TIMER 0x121 +#define EMULATE_DELAY_OFFSET_VALUE 20 +#define EMULATE_PM_TMR_EN (1 << 16) +#define EMULATE_DELAY_VALUE 0x13 + #define MSR_IA32_SYSENTER_CS 0x00000174 #define MSR_IA32_SYSENTER_ESP 0x00000175 #define MSR_IA32_SYSENTER_EIP 0x00000176 @@ -78,9 +89,14 @@ #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) +/* This is burst mode BIT 38 in IA32_MISC_ENABLE MSR at offset 1A0h */ +#define BURST_MODE_DISABLE (1 << 6) #define MSR_IA32_MISC_ENABLES 0x000001a0 #define MSR_TEMPERATURE_TARGET 0x1a2 +#define MSR_PREFETCH_CTL 0x1a4 +#define PREFETCH_L1_DISABLE (1 << 0) +#define PREFETCH_L2_DISABLE (1 << 2) #define MSR_OFFCORE_RSP_0 0x000001a6 #define MSR_OFFCORE_RSP_1 0x000001a7 #define MSR_MISC_PWR_MGMT 0x1aa @@ -600,6 +616,12 @@ #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 #define MSR_IA32_VMX_VMFUNC 0x00000491 +#define MSR_IA32_PQR_ASSOC 0xc8f +/* MSR bits 33:32 encode slot number 0-3 */ +#define MSR_IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1) + +#define MSR_L2_QOS_MASK(reg) (0xd10 + (reg)) + /* VMX_BASIC bits and bitmasks */ #define VMX_BASIC_VMCS_SIZE_SHIFT 32 #define VMX_BASIC_64 0x0001000000000000LLU diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index 2d897f82ef..6f29e75ce6 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -25,6 +25,7 @@ #define MTRR_CAP_FIX (1 << 8) #define MTRR_CAP_VCNT_MASK 0xff +#define MTRR_DEF_TYPE_MASK 0xff #define MTRR_DEF_TYPE_EN (1 << 11) #define MTRR_DEF_TYPE_FIX_EN (1 << 10) -- cgit From bdeb2bccbf40474eca8ef039ab794ba46cd971e5 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:11:47 -0600 Subject: x86: Rename turbo ratio MSR to MSR_TURBO_RATIO_LIMIT This MSR number is used on most modern Intel processors, so drop the confusing NHM prefix (which might mean Nehalem). Signed-off-by: Simon Glass Reviewed-by: Bin Meng [bmeng: drop MSR_IVT_TURBO_RATIO_LIMIT as no code uses it] Signed-off-by: Bin Meng --- arch/x86/cpu/broadwell/cpu_full.c | 2 +- arch/x86/include/asm/msr-index.h | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/cpu/broadwell/cpu_full.c b/arch/x86/cpu/broadwell/cpu_full.c index bd0b2037fa..9686cf5e0e 100644 --- a/arch/x86/cpu/broadwell/cpu_full.c +++ b/arch/x86/cpu/broadwell/cpu_full.c @@ -346,7 +346,7 @@ static void set_max_ratio(void) /* Check for configurable TDP option */ if (turbo_get_state() == TURBO_ENABLED) { - msr = msr_read(MSR_NHM_TURBO_RATIO_LIMIT); + msr = msr_read(MSR_TURBO_RATIO_LIMIT); perf_ctl.lo = (msr.lo & 0xff) << 8; } else if (cpu_config_tdp_levels()) { /* Set to nominal TDP ratio */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 1a02d8c8fe..6cb5870809 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -101,8 +101,7 @@ #define MSR_OFFCORE_RSP_1 0x000001a7 #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) -#define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad -#define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae +#define MSR_TURBO_RATIO_LIMIT 0x000001ad #define MSR_IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 -- cgit From 49a0f8cc964c612164ef101267f90266279409a7 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:56:32 -0600 Subject: x86: Move acpi_s3.h to a common location At present this hedaer is only available on x86. To allow sandbox to use it for testing, move it to a common location. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/cpu/baytrail/acpi.c | 2 +- arch/x86/cpu/cpu.c | 2 +- arch/x86/cpu/wakeup.S | 2 +- arch/x86/include/asm/acpi_s3.h | 130 ----------------------------------------- arch/x86/lib/acpi_s3.c | 2 +- arch/x86/lib/coreboot_table.c | 2 +- arch/x86/lib/fsp/fsp_common.c | 2 +- arch/x86/lib/fsp1/fsp_common.c | 2 +- 8 files changed, 7 insertions(+), 137 deletions(-) delete mode 100644 arch/x86/include/asm/acpi_s3.h (limited to 'arch/x86') diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c index 1e3829a433..f44228e693 100644 --- a/arch/x86/cpu/baytrail/acpi.c +++ b/arch/x86/cpu/baytrail/acpi.c @@ -4,10 +4,10 @@ */ #include +#include #include #include #include -#include #include #include #include diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 290ee084e5..9ee4b0294a 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -19,13 +19,13 @@ */ #include +#include #include #include #include #include #include #include -#include #include #include #include diff --git a/arch/x86/cpu/wakeup.S b/arch/x86/cpu/wakeup.S index 663b02f27d..244ca1276a 100644 --- a/arch/x86/cpu/wakeup.S +++ b/arch/x86/cpu/wakeup.S @@ -5,7 +5,7 @@ * From coreboot src/arch/x86/wakeup.S */ -#include +#include #include #include diff --git a/arch/x86/include/asm/acpi_s3.h b/arch/x86/include/asm/acpi_s3.h deleted file mode 100644 index baa848dcd1..0000000000 --- a/arch/x86/include/asm/acpi_s3.h +++ /dev/null @@ -1,130 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017, Bin Meng - */ - -#ifndef __ASM_ACPI_S3_H__ -#define __ASM_ACPI_S3_H__ - -#define WAKEUP_BASE 0x600 - -/* PM1_STATUS register */ -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define RTC_STS (1 << 10) -#define SLPBTN_STS (1 << 9) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define BM_STS (1 << 4) -#define TMR_STS (1 << 0) - -/* PM1_CNT register */ -#define SLP_EN (1 << 13) -#define SLP_TYP_SHIFT 10 -#define SLP_TYP (7 << SLP_TYP_SHIFT) -#define SLP_TYP_S0 0 -#define SLP_TYP_S1 1 -#define SLP_TYP_S3 5 -#define SLP_TYP_S4 6 -#define SLP_TYP_S5 7 - -/* Memory size reserved for S3 resume */ -#define S3_RESERVE_SIZE 0x1000 - -#ifndef __ASSEMBLY__ - -extern char __wakeup[]; -extern int __wakeup_size; - -enum acpi_sleep_state { - ACPI_S0, - ACPI_S1, - ACPI_S2, - ACPI_S3, - ACPI_S4, - ACPI_S5, -}; - -/** - * acpi_ss_string() - get ACPI-defined sleep state string - * - * @pm1_cnt: ACPI-defined sleep state - * @return: a pointer to the sleep state string. - */ -static inline char *acpi_ss_string(enum acpi_sleep_state state) -{ - char *ss_string[] = { "S0", "S1", "S2", "S3", "S4", "S5"}; - - return ss_string[state]; -} - -/** - * acpi_sleep_from_pm1() - get ACPI-defined sleep state from PM1_CNT register - * - * @pm1_cnt: PM1_CNT register value - * @return: ACPI-defined sleep state if given valid PM1_CNT register value, - * -EINVAL otherwise. - */ -static inline enum acpi_sleep_state acpi_sleep_from_pm1(u32 pm1_cnt) -{ - switch ((pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { - case SLP_TYP_S0: - return ACPI_S0; - case SLP_TYP_S1: - return ACPI_S1; - case SLP_TYP_S3: - return ACPI_S3; - case SLP_TYP_S4: - return ACPI_S4; - case SLP_TYP_S5: - return ACPI_S5; - } - - return -EINVAL; -} - -/** - * chipset_prev_sleep_state() - Get chipset previous sleep state - * - * This returns chipset previous sleep state from ACPI registers. - * Platform codes must supply this routine in order to support ACPI S3. - * - * @return ACPI_S0/S1/S2/S3/S4/S5. - */ -enum acpi_sleep_state chipset_prev_sleep_state(void); - -/** - * chipset_clear_sleep_state() - Clear chipset sleep state - * - * This clears chipset sleep state in ACPI registers. - * Platform codes must supply this routine in order to support ACPI S3. - */ -void chipset_clear_sleep_state(void); - -struct acpi_fadt; -/** - * acpi_resume() - Do ACPI S3 resume - * - * This calls U-Boot wake up assembly stub and jumps to OS's wake up vector. - * - * @fadt: FADT table pointer in the ACPI table - * @return: Never returns - */ -void acpi_resume(struct acpi_fadt *fadt); - -/** - * acpi_s3_reserve() - Reserve memory for ACPI S3 resume - * - * This copies memory where real mode interrupt handler stubs reside to the - * reserved place on the stack. - * - * This routine should be called by reserve_arch() before U-Boot is relocated - * when ACPI S3 resume is enabled. - * - * @return: 0 always - */ -int acpi_s3_reserve(void); - -#endif /* __ASSEMBLY__ */ - -#endif /* __ASM_ACPI_S3_H__ */ diff --git a/arch/x86/lib/acpi_s3.c b/arch/x86/lib/acpi_s3.c index 03917188a9..197636c4b5 100644 --- a/arch/x86/lib/acpi_s3.c +++ b/arch/x86/lib/acpi_s3.c @@ -4,8 +4,8 @@ */ #include +#include #include -#include #include #include #include diff --git a/arch/x86/lib/coreboot_table.c b/arch/x86/lib/coreboot_table.c index 2d08a2db0d..8685aa3046 100644 --- a/arch/x86/lib/coreboot_table.c +++ b/arch/x86/lib/coreboot_table.c @@ -4,8 +4,8 @@ */ #include +#include #include -#include #include #include diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index 6678d75ffd..40ba866d77 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -4,10 +4,10 @@ */ #include +#include #include #include #include -#include #include #include #include diff --git a/arch/x86/lib/fsp1/fsp_common.c b/arch/x86/lib/fsp1/fsp_common.c index 285ef72ebf..e8066d8de3 100644 --- a/arch/x86/lib/fsp1/fsp_common.c +++ b/arch/x86/lib/fsp1/fsp_common.c @@ -4,10 +4,10 @@ */ #include +#include #include #include #include -#include #include #include #include -- cgit From a827ba910cdbcae6d0a1c2ce7b91b41d00218a4c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 31 Aug 2019 21:23:18 -0600 Subject: x86: pci: Drop the first parameter in pci_x86_r/w_config() This parameter is needed by the PCI driver-mode interface but is always NULL on x86. There are a number of calls to this function so it makes sense to minimise the parameters. Adjust the x86 function to omit the first parameter, and introduce stub functions to handle the conversion. Signed-off-by: Simon Glass Reviewed-by: Bin Meng [bmeng: rebase the patch against u-boot-x86/next to get it applied cleanly] Signed-off-by: Bin Meng --- arch/x86/cpu/broadwell/cpu.c | 7 ++----- arch/x86/cpu/ivybridge/cpu.c | 3 +-- arch/x86/cpu/pci.c | 20 ++++++++------------ arch/x86/include/asm/pci.h | 15 ++++++--------- 4 files changed, 17 insertions(+), 28 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c index bba8cd1e94..297f1e0b68 100644 --- a/arch/x86/cpu/broadwell/cpu.c +++ b/arch/x86/cpu/broadwell/cpu.c @@ -103,11 +103,8 @@ int print_cpuinfo(void) void board_debug_uart_init(void) { - struct udevice *bus = NULL; - /* com1 / com2 decode range */ - pci_x86_write_config(bus, PCH_DEV_LPC, LPC_IO_DEC, 1 << 4, PCI_SIZE_16); + pci_x86_write_config(PCH_DEV_LPC, LPC_IO_DEC, 1 << 4, PCI_SIZE_16); - pci_x86_write_config(bus, PCH_DEV_LPC, LPC_EN, COMA_LPC_EN, - PCI_SIZE_16); + pci_x86_write_config(PCH_DEV_LPC, LPC_EN, COMA_LPC_EN, PCI_SIZE_16); } diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index c8b16e32c0..6db9da81b7 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -199,6 +199,5 @@ int print_cpuinfo(void) void board_debug_uart_init(void) { /* This enables the debug UART */ - pci_x86_write_config(NULL, PCH_LPC_DEV, LPC_EN, COMA_LPC_EN, - PCI_SIZE_16); + pci_x86_write_config(PCH_LPC_DEV, LPC_EN, COMA_LPC_EN, PCI_SIZE_16); } diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c index 0ccde194d9..e1aae158ce 100644 --- a/arch/x86/cpu/pci.c +++ b/arch/x86/cpu/pci.c @@ -16,12 +16,8 @@ #include #include -/* - * TODO(sjg@chromium.org): Drop the first parameter from each of these - * functions since it is not used. - */ -int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset, - ulong *valuep, enum pci_size_t size) +int pci_x86_read_config(pci_dev_t bdf, uint offset, ulong *valuep, + enum pci_size_t size) { outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR); switch (size) { @@ -39,8 +35,8 @@ int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset, return 0; } -int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, - ulong value, enum pci_size_t size) +int pci_x86_write_config(pci_dev_t bdf, uint offset, ulong value, + enum pci_size_t size) { outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR); switch (size) { @@ -58,19 +54,19 @@ int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, return 0; } -int pci_x86_clrset_config(struct udevice *bus, pci_dev_t bdf, uint offset, - ulong clr, ulong set, enum pci_size_t size) +int pci_x86_clrset_config(pci_dev_t bdf, uint offset, ulong clr, ulong set, + enum pci_size_t size) { ulong value; int ret; - ret = pci_x86_read_config(bus, bdf, offset, &value, size); + ret = pci_x86_read_config(bdf, offset, &value, size); if (ret) return ret; value &= ~clr; value |= set; - return pci_x86_write_config(bus, bdf, offset, value, size); + return pci_x86_write_config(bdf, offset, value, size); } void pci_assign_irqs(int bus, int device, u8 irq[4]) diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index fb1edf3df7..2a72073572 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -22,30 +22,28 @@ * * This function can be called before PCI is set up in driver model. * - * @bus: Bus to read from (ignored, can be NULL) * @bdf: PCI device address: bus, device and function -see PCI_BDF() * @offset: Register offset to read * @valuep: Place to put the returned value * @size: Access size * @return 0 if OK, -ve on error */ -int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset, - ulong *valuep, enum pci_size_t size); +int pci_x86_read_config(pci_dev_t bdf, uint offset, ulong *valuep, + enum pci_size_t size); /** * pci_bus_write_config() - Write a configuration value to a device * * This function can be called before PCI is set up in driver model. * - * @bus: Bus to read from (ignored, can be NULL) * @bdf: PCI device address: bus, device and function -see PCI_BDF() * @offset: Register offset to write * @value: Value to write * @size: Access size * @return 0 if OK, -ve on error */ -int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, - ulong value, enum pci_size_t size); +int pci_x86_write_config(pci_dev_t bdf, uint offset, ulong value, + enum pci_size_t size); /** * pci_bus_clrset_config32() - Update a configuration value for a device @@ -53,15 +51,14 @@ int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, * The register at @offset is updated to (oldvalue & ~clr) | set. This function * can be called before PCI is set up in driver model. * - * @bus: Bus to read from (ignored, can be NULL) * @bdf: PCI device address: bus, device and function -see PCI_BDF() * @offset: Register offset to update * @clr: Bits to clear * @set: Bits to set * @return 0 if OK, -ve on error */ -int pci_x86_clrset_config(struct udevice *bus, pci_dev_t bdf, uint offset, - ulong clr, ulong set, enum pci_size_t size); +int pci_x86_clrset_config(pci_dev_t bdf, uint offset, ulong clr, ulong set, + enum pci_size_t size); /** * Assign IRQ number to a PCI device -- cgit From e2493a7f5a06854d45175a4aa356ba3a2d810300 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:56:35 -0600 Subject: x86: Use a common definition of MSR_IA32_PERF_CTL Remove the duplicate definition as it is not needed. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/cpu/broadwell/cpu.c | 2 +- arch/x86/cpu/broadwell/cpu_full.c | 2 +- arch/x86/cpu/intel_common/cpu.c | 2 +- arch/x86/include/asm/cpu_common.h | 2 -- 4 files changed, 3 insertions(+), 5 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c index 297f1e0b68..61003a6d68 100644 --- a/arch/x86/cpu/broadwell/cpu.c +++ b/arch/x86/cpu/broadwell/cpu.c @@ -57,7 +57,7 @@ void set_max_freq(void) } perf_ctl.hi = 0; - msr_write(IA32_PERF_CTL, perf_ctl); + msr_write(MSR_IA32_PERF_CTL, perf_ctl); debug("CPU: frequency set to %d MHz\n", ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); diff --git a/arch/x86/cpu/broadwell/cpu_full.c b/arch/x86/cpu/broadwell/cpu_full.c index 9686cf5e0e..0e3d878139 100644 --- a/arch/x86/cpu/broadwell/cpu_full.c +++ b/arch/x86/cpu/broadwell/cpu_full.c @@ -357,7 +357,7 @@ static void set_max_ratio(void) msr = msr_read(MSR_PLATFORM_INFO); perf_ctl.lo = msr.lo & 0xff00; } - msr_write(IA32_PERF_CTL, perf_ctl); + msr_write(MSR_IA32_PERF_CTL, perf_ctl); debug("cpu: frequency set to %d\n", ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c index 9357626b5a..3a0d505a32 100644 --- a/arch/x86/cpu/intel_common/cpu.c +++ b/arch/x86/cpu/intel_common/cpu.c @@ -116,7 +116,7 @@ int cpu_intel_get_info(struct cpu_info *info, int bclk) { msr_t msr; - msr = msr_read(IA32_PERF_CTL); + msr = msr_read(MSR_IA32_PERF_CTL); info->cpu_freq = ((msr.lo >> 8) & 0xff) * bclk * 1000000; info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU | 1 << CPU_FEAT_UCODE | 1 << CPU_FEAT_DEVICE_ID; diff --git a/arch/x86/include/asm/cpu_common.h b/arch/x86/include/asm/cpu_common.h index 5e398bec94..7ae3bd1c53 100644 --- a/arch/x86/include/asm/cpu_common.h +++ b/arch/x86/include/asm/cpu_common.h @@ -6,8 +6,6 @@ #ifndef __ASM_CPU_COMMON_H #define __ASM_CPU_COMMON_H -#define IA32_PERF_CTL 0x199 - struct cpu_info; /** -- cgit From 246ac08b037befab08805750049df75044ab7f6c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:56:36 -0600 Subject: x86: Add a common function to set CPU thermal target This code appears in a few places, so move it to a common file. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/cpu/broadwell/cpu_full.c | 20 +------------------- arch/x86/cpu/intel_common/cpu.c | 22 ++++++++++++++++++++++ arch/x86/cpu/ivybridge/model_206ax.c | 25 +++---------------------- arch/x86/include/asm/cpu_common.h | 11 +++++++++++ 4 files changed, 37 insertions(+), 41 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/cpu/broadwell/cpu_full.c b/arch/x86/cpu/broadwell/cpu_full.c index 0e3d878139..d1f3c07109 100644 --- a/arch/x86/cpu/broadwell/cpu_full.c +++ b/arch/x86/cpu/broadwell/cpu_full.c @@ -495,24 +495,6 @@ static void configure_misc(void) msr_write(MSR_IA32_PACKAGE_THERM_INTERRUPT, msr); } -static void configure_thermal_target(struct udevice *dev) -{ - int tcc_offset; - msr_t msr; - - tcc_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "intel,tcc-offset", 0); - - /* Set TCC activaiton offset if supported */ - msr = msr_read(MSR_PLATFORM_INFO); - if ((msr.lo & (1 << 30)) && tcc_offset) { - msr = msr_read(MSR_TEMPERATURE_TARGET); - msr.lo &= ~(0xf << 24); /* Bits 27:24 */ - msr.lo |= (tcc_offset & 0xf) << 24; - msr_write(MSR_TEMPERATURE_TARGET, msr); - } -} - static void configure_dca_cap(void) { struct cpuid_result cpuid_regs; @@ -562,7 +544,7 @@ static void cpu_core_init(struct udevice *dev) configure_misc(); /* Thermal throttle activation offset */ - configure_thermal_target(dev); + cpu_configure_thermal_target(dev); /* Enable Direct Cache Access */ configure_dca_cap(); diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c index 3a0d505a32..7d0ed73b4b 100644 --- a/arch/x86/cpu/intel_common/cpu.c +++ b/arch/x86/cpu/intel_common/cpu.c @@ -123,3 +123,25 @@ int cpu_intel_get_info(struct cpu_info *info, int bclk) return 0; } + +int cpu_configure_thermal_target(struct udevice *dev) +{ + u32 tcc_offset; + msr_t msr; + int ret; + + ret = dev_read_u32(dev, "tcc-offset", &tcc_offset); + if (!ret) + return -ENOENT; + + /* Set TCC activaiton offset if supported */ + msr = msr_read(MSR_PLATFORM_INFO); + if (msr.lo & (1 << 30)) { + msr = msr_read(MSR_TEMPERATURE_TARGET); + msr.lo &= ~(0xf << 24); /* Bits 27:24 */ + msr.lo |= (tcc_offset & 0xf) << 24; + msr_write(MSR_TEMPERATURE_TARGET, msr); + } + + return 0; +} diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index 68e78e9478..ed66d2dd8d 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -283,26 +283,6 @@ static void configure_c_states(void) msr_write(MSR_PP1_CURRENT_CONFIG, msr); } -static int configure_thermal_target(struct udevice *dev) -{ - int tcc_offset; - msr_t msr; - - tcc_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "tcc-offset", 0); - - /* Set TCC activaiton offset if supported */ - msr = msr_read(MSR_PLATFORM_INFO); - if ((msr.lo & (1 << 30)) && tcc_offset) { - msr = msr_read(MSR_TEMPERATURE_TARGET); - msr.lo &= ~(0xf << 24); /* Bits 27:24 */ - msr.lo |= (tcc_offset & 0xf) << 24; - msr_write(MSR_TEMPERATURE_TARGET, msr); - } - - return 0; -} - static void configure_misc(void) { msr_t msr; @@ -414,10 +394,11 @@ static int model_206ax_init(struct udevice *dev) configure_misc(); /* Thermal throttle activation offset */ - ret = configure_thermal_target(dev); + ret = cpu_configure_thermal_target(dev); if (ret) { debug("Cannot set thermal target\n"); - return ret; + if (ret != -ENOENT) + return ret; } /* Enable Direct Cache Access */ diff --git a/arch/x86/include/asm/cpu_common.h b/arch/x86/include/asm/cpu_common.h index 7ae3bd1c53..e158c96ce6 100644 --- a/arch/x86/include/asm/cpu_common.h +++ b/arch/x86/include/asm/cpu_common.h @@ -45,4 +45,15 @@ int cpu_set_flex_ratio_to_tdp_nominal(void); */ int cpu_intel_get_info(struct cpu_info *info, int bclk_mz); +/** + * cpu_configure_thermal_target() - Set the thermal target for a CPU + * + * This looks up the tcc-offset property and uses it to set the + * MSR_TEMPERATURE_TARGET value. + * + * @dev: CPU device + * @return 0 if OK, -ENOENT if no target is given in device tree + */ +int cpu_configure_thermal_target(struct udevice *dev); + #endif -- cgit From 55a6b13a75276fbdf7186b34b4ad72238a7ec16b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:56:37 -0600 Subject: x86: Use a common bus clock for Intel CPUs Modern Intel CPUs use a standard bus clock value of 100MHz, so put this in a common file and tidy up the copies. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/cpu/broadwell/cpu.c | 2 +- arch/x86/cpu/broadwell/cpu_full.c | 4 ++-- arch/x86/cpu/ivybridge/model_206ax.c | 4 ++-- arch/x86/include/asm/arch-broadwell/cpu.h | 3 --- arch/x86/include/asm/arch-broadwell/pch.h | 3 --- arch/x86/include/asm/arch-ivybridge/model_206ax.h | 3 --- arch/x86/include/asm/cpu_common.h | 5 +++++ 7 files changed, 10 insertions(+), 14 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c index 61003a6d68..586a2e8f05 100644 --- a/arch/x86/cpu/broadwell/cpu.c +++ b/arch/x86/cpu/broadwell/cpu.c @@ -60,7 +60,7 @@ void set_max_freq(void) msr_write(MSR_IA32_PERF_CTL, perf_ctl); debug("CPU: frequency set to %d MHz\n", - ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); + ((perf_ctl.lo >> 8) & 0xff) * INTEL_BCLK_MHZ); } int arch_cpu_init(void) diff --git a/arch/x86/cpu/broadwell/cpu_full.c b/arch/x86/cpu/broadwell/cpu_full.c index d1f3c07109..58cc2f362c 100644 --- a/arch/x86/cpu/broadwell/cpu_full.c +++ b/arch/x86/cpu/broadwell/cpu_full.c @@ -360,7 +360,7 @@ static void set_max_ratio(void) msr_write(MSR_IA32_PERF_CTL, perf_ctl); debug("cpu: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); + ((perf_ctl.lo >> 8) & 0xff) * INTEL_BCLK_MHZ); } int broadwell_init(struct udevice *dev) @@ -634,7 +634,7 @@ void cpu_set_power_limits(int power_limit_1_time) static int broadwell_get_info(struct udevice *dev, struct cpu_info *info) { - return cpu_intel_get_info(info, BROADWELL_BCLK); + return cpu_intel_get_info(info, INTEL_BCLK_MHZ); } static int broadwell_get_count(struct udevice *dev) diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index ed66d2dd8d..3177ba3297 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -346,7 +346,7 @@ static void set_max_ratio(void) msr_write(MSR_IA32_PERF_CTL, perf_ctl); debug("model_x06ax: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK); + ((perf_ctl.lo >> 8) & 0xff) * INTEL_BCLK_MHZ); } static void set_energy_perf_bias(u8 policy) @@ -418,7 +418,7 @@ static int model_206ax_init(struct udevice *dev) static int model_206ax_get_info(struct udevice *dev, struct cpu_info *info) { - return cpu_intel_get_info(info, SANDYBRIDGE_BCLK); + return cpu_intel_get_info(info, INTEL_BCLK_MHZ); return 0; } diff --git a/arch/x86/include/asm/arch-broadwell/cpu.h b/arch/x86/include/asm/arch-broadwell/cpu.h index ca22a79996..3bc3bd6609 100644 --- a/arch/x86/include/asm/arch-broadwell/cpu.h +++ b/arch/x86/include/asm/arch-broadwell/cpu.h @@ -21,9 +21,6 @@ #define CPUID_BROADWELL_D0 0x306d3 #define CPUID_BROADWELL_E0 0x306d4 -/* Broadwell bus clock is fixed at 100MHz */ -#define BROADWELL_BCLK 100 - #define BROADWELL_FAMILY_ULT 0x306d0 #define CORE_THREAD_COUNT_MSR 0x35 diff --git a/arch/x86/include/asm/arch-broadwell/pch.h b/arch/x86/include/asm/arch-broadwell/pch.h index 23153a040f..ecdf6d16f9 100644 --- a/arch/x86/include/asm/arch-broadwell/pch.h +++ b/arch/x86/include/asm/arch-broadwell/pch.h @@ -6,9 +6,6 @@ #ifndef __ASM_ARCH_PCH_H #define __ASM_ARCH_PCH_H -/* CPU bus clock is fixed at 100MHz */ -#define CPU_BCLK 100 - #define PMBASE 0x40 #define ACPI_CNTL 0x44 #define ACPI_EN (1 << 7) diff --git a/arch/x86/include/asm/arch-ivybridge/model_206ax.h b/arch/x86/include/asm/arch-ivybridge/model_206ax.h index 850d96bdd9..10caaa2422 100644 --- a/arch/x86/include/asm/arch-ivybridge/model_206ax.h +++ b/arch/x86/include/asm/arch-ivybridge/model_206ax.h @@ -8,9 +8,6 @@ #ifndef _ASM_ARCH_MODEL_206AX_H #define _ASM_ARCH_MODEL_206AX_H -/* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ -#define SANDYBRIDGE_BCLK 100 - #define CPUID_VMX (1 << 5) #define CPUID_SMX (1 << 6) #define MSR_FEATURE_CONFIG 0x13c diff --git a/arch/x86/include/asm/cpu_common.h b/arch/x86/include/asm/cpu_common.h index e158c96ce6..f42eb32308 100644 --- a/arch/x86/include/asm/cpu_common.h +++ b/arch/x86/include/asm/cpu_common.h @@ -6,6 +6,11 @@ #ifndef __ASM_CPU_COMMON_H #define __ASM_CPU_COMMON_H +/* Standard Intel bus clock is fixed at 100MHz */ +enum { + INTEL_BCLK_MHZ = 100 +}; + struct cpu_info; /** -- cgit From 2f0c2f03e71a68d7e5d8770c10d0154ead6dd104 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:56:38 -0600 Subject: x86: Add common functions for TDP and perf control These functions are the same on modern Intel CPUs, so use common code to set them. Signed-off-by: Simon Glass Reviewed-by: Bin Meng [bmeng: return false instead of 0 in cpu_ivybridge_config_tdp_levels(); fix 'muiltiplier' and 'desgn' typos] Signed-off-by: Bin Meng --- arch/x86/cpu/broadwell/cpu.c | 7 ++---- arch/x86/cpu/broadwell/cpu_full.c | 9 -------- arch/x86/cpu/intel_common/cpu.c | 20 +++++++++++++++++ arch/x86/cpu/ivybridge/model_206ax.c | 27 +++++++++-------------- arch/x86/cpu/ivybridge/northbridge.c | 2 +- arch/x86/include/asm/arch-ivybridge/model_206ax.h | 2 +- arch/x86/include/asm/cpu_common.h | 18 +++++++++++++++ 7 files changed, 52 insertions(+), 33 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c index 586a2e8f05..55a7439f1c 100644 --- a/arch/x86/cpu/broadwell/cpu.c +++ b/arch/x86/cpu/broadwell/cpu.c @@ -41,12 +41,9 @@ int arch_cpu_init_dm(void) void set_max_freq(void) { - msr_t msr, perf_ctl, platform_info; + msr_t msr, perf_ctl; - /* Check for configurable TDP option */ - platform_info = msr_read(MSR_PLATFORM_INFO); - - if ((platform_info.hi >> 1) & 3) { + if (cpu_config_tdp_levels()) { /* Set to nominal TDP ratio */ msr = msr_read(MSR_CONFIG_TDP_NOMINAL); perf_ctl.lo = (msr.lo & 0xff) << 8; diff --git a/arch/x86/cpu/broadwell/cpu_full.c b/arch/x86/cpu/broadwell/cpu_full.c index 58cc2f362c..169b5b02a6 100644 --- a/arch/x86/cpu/broadwell/cpu_full.c +++ b/arch/x86/cpu/broadwell/cpu_full.c @@ -329,15 +329,6 @@ static int bsp_init_before_ap_bringup(struct udevice *dev) return 0; } -static int cpu_config_tdp_levels(void) -{ - msr_t platform_info; - - /* Bits 34:33 indicate how many levels supported */ - platform_info = msr_read(MSR_PLATFORM_INFO); - return (platform_info.hi >> 1) & 3; -} - static void set_max_ratio(void) { msr_t msr, perf_ctl; diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c index 7d0ed73b4b..1898903853 100644 --- a/arch/x86/cpu/intel_common/cpu.c +++ b/arch/x86/cpu/intel_common/cpu.c @@ -145,3 +145,23 @@ int cpu_configure_thermal_target(struct udevice *dev) return 0; } + +void cpu_set_perf_control(uint clk_ratio) +{ + msr_t perf_ctl; + + perf_ctl.lo = (clk_ratio & 0xff) << 8; + perf_ctl.hi = 0; + msr_write(MSR_IA32_PERF_CTL, perf_ctl); + debug("CPU: frequency set to %d MHz\n", clk_ratio * INTEL_BCLK_MHZ); +} + +bool cpu_config_tdp_levels(void) +{ + msr_t platform_info; + + /* Bits 34:33 indicate how many levels supported */ + platform_info = msr_read(MSR_PLATFORM_INFO); + + return ((platform_info.hi >> 1) & 3) != 0; +} diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index 3177ba3297..56ab6bf4ac 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -140,19 +140,16 @@ static const u8 power_limit_time_msr_to_sec[] = { [0x11] = 128, }; -int cpu_config_tdp_levels(void) +bool cpu_ivybridge_config_tdp_levels(void) { struct cpuid_result result; - msr_t platform_info; /* Minimum CPU revision */ result = cpuid(1); if (result.eax < IVB_CONFIG_TDP_MIN_CPUID) - return 0; + return false; - /* Bits 34:33 indicate how many levels supported */ - platform_info = msr_read(MSR_PLATFORM_INFO); - return (platform_info.hi >> 1) & 3; + return cpu_config_tdp_levels(); } /* @@ -213,7 +210,7 @@ void set_power_limits(u8 power_limit_1_time) msr_write(MSR_PKG_POWER_LIMIT, limit); /* Use nominal TDP values for CPUs with configurable TDP */ - if (cpu_config_tdp_levels()) { + if (cpu_ivybridge_config_tdp_levels()) { msr = msr_read(MSR_CONFIG_TDP_NOMINAL); limit.hi = 0; limit.lo = msr.lo & 0xff; @@ -329,24 +326,20 @@ static void configure_dca_cap(void) static void set_max_ratio(void) { - msr_t msr, perf_ctl; - - perf_ctl.hi = 0; + msr_t msr; + uint ratio; /* Check for configurable TDP option */ - if (cpu_config_tdp_levels()) { + if (cpu_ivybridge_config_tdp_levels()) { /* Set to nominal TDP ratio */ msr = msr_read(MSR_CONFIG_TDP_NOMINAL); - perf_ctl.lo = (msr.lo & 0xff) << 8; + ratio = msr.lo & 0xff; } else { /* Platform Info bits 15:8 give max ratio */ msr = msr_read(MSR_PLATFORM_INFO); - perf_ctl.lo = msr.lo & 0xff00; + ratio = (msr.lo & 0xff00) >> 8; } - msr_write(MSR_IA32_PERF_CTL, perf_ctl); - - debug("model_x06ax: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * INTEL_BCLK_MHZ); + cpu_set_perf_control(ratio); } static void set_energy_perf_bias(u8 policy) diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index a809b823b3..0f427afcb8 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -141,7 +141,7 @@ static void northbridge_init(struct udevice *dev, int rev) * CPUs with configurable TDP also need power limits set * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT. */ - if (cpu_config_tdp_levels()) { + if (cpu_ivybridge_config_tdp_levels()) { msr_t msr = msr_read(MSR_PKG_POWER_LIMIT); writel(msr.lo, MCHBAR_REG(0x59A0)); diff --git a/arch/x86/include/asm/arch-ivybridge/model_206ax.h b/arch/x86/include/asm/arch-ivybridge/model_206ax.h index 10caaa2422..4839ebc312 100644 --- a/arch/x86/include/asm/arch-ivybridge/model_206ax.h +++ b/arch/x86/include/asm/arch-ivybridge/model_206ax.h @@ -58,6 +58,6 @@ /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); -int cpu_config_tdp_levels(void); +bool cpu_ivybridge_config_tdp_levels(void); #endif diff --git a/arch/x86/include/asm/cpu_common.h b/arch/x86/include/asm/cpu_common.h index f42eb32308..c61d74e4a0 100644 --- a/arch/x86/include/asm/cpu_common.h +++ b/arch/x86/include/asm/cpu_common.h @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* + * Common code for Intel CPUs + * * Copyright (c) 2016 Google, Inc */ @@ -61,4 +63,20 @@ int cpu_intel_get_info(struct cpu_info *info, int bclk_mz); */ int cpu_configure_thermal_target(struct udevice *dev); +/** + * cpu_set_perf_control() - Set the nominal CPU clock speed + * + * This sets the clock speed as a multiplier of BCLK + * + * @clk_ratio: Ratio to use + */ +void cpu_set_perf_control(uint clk_ratio); + +/** + * cpu_config_tdp_levels() - Check for configurable TDP option + * + * @return true if the CPU has configurable TDP (Thermal-design power) + */ +bool cpu_config_tdp_levels(void); + #endif -- cgit From f6d00da459694a42c1de1e42b159595e2f5ad56f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:56:39 -0600 Subject: x86: Tidy up some duplicate MSR defines Some MSR registers are defined twice in different parts of the file. Move them together and remove the duplicates. Also drop some thermal defines which are not used. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/cpu/baytrail/cpu.c | 6 +-- arch/x86/cpu/broadwell/cpu_full.c | 6 +-- arch/x86/cpu/turbo.c | 10 ++-- arch/x86/include/asm/msr-index.h | 106 ++++++++++++++++---------------------- 4 files changed, 54 insertions(+), 74 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c index 2eb917283b..9394eab956 100644 --- a/arch/x86/cpu/baytrail/cpu.c +++ b/arch/x86/cpu/baytrail/cpu.c @@ -68,9 +68,9 @@ static void set_max_freq(void) msr_t msr; /* Enable speed step */ - msr = msr_read(MSR_IA32_MISC_ENABLES); - msr.lo |= (1 << 16); - msr_write(MSR_IA32_MISC_ENABLES, msr); + msr = msr_read(MSR_IA32_MISC_ENABLE); + msr.lo |= MISC_ENABLE_ENHANCED_SPEEDSTEP; + msr_write(MSR_IA32_MISC_ENABLE, msr); /* * Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of diff --git a/arch/x86/cpu/broadwell/cpu_full.c b/arch/x86/cpu/broadwell/cpu_full.c index 169b5b02a6..895edeb4bc 100644 --- a/arch/x86/cpu/broadwell/cpu_full.c +++ b/arch/x86/cpu/broadwell/cpu_full.c @@ -470,9 +470,9 @@ static void configure_misc(void) msr_t msr; msr = msr_read(MSR_IA32_MISC_ENABLE); - msr.lo |= (1 << 0); /* Fast String enable */ - msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= MISC_ENABLE_FAST_STRING; + msr.lo |= MISC_ENABLE_TM1; + msr.lo |= MISC_ENABLE_ENHANCED_SPEEDSTEP; msr_write(MSR_IA32_MISC_ENABLE, msr); /* Disable thermal interrupts */ diff --git a/arch/x86/cpu/turbo.c b/arch/x86/cpu/turbo.c index a41d511238..be468d2b2c 100644 --- a/arch/x86/cpu/turbo.c +++ b/arch/x86/cpu/turbo.c @@ -60,8 +60,8 @@ int turbo_get_state(void) cpuid_regs = cpuid(CPUID_LEAF_PM); turbo_cap = !!(cpuid_regs.eax & PM_CAP_TURBO_MODE); - msr = msr_read(MSR_IA32_MISC_ENABLES); - turbo_en = !(msr.hi & H_MISC_DISABLE_TURBO); + msr = msr_read(MSR_IA32_MISC_ENABLE); + turbo_en = !(msr.hi & MISC_DISABLE_TURBO); if (!turbo_cap && turbo_en) { /* Unavailable */ @@ -86,9 +86,9 @@ void turbo_enable(void) /* Only possible if turbo is available but hidden */ if (turbo_get_state() == TURBO_DISABLED) { /* Clear Turbo Disable bit in Misc Enables */ - msr = msr_read(MSR_IA32_MISC_ENABLES); - msr.hi &= ~H_MISC_DISABLE_TURBO; - msr_write(MSR_IA32_MISC_ENABLES, msr); + msr = msr_read(MSR_IA32_MISC_ENABLE); + msr.hi &= ~MISC_DISABLE_TURBO; + msr_write(MSR_IA32_MISC_ENABLE, msr); /* Update cached turbo state */ set_global_turbo_state(TURBO_ENABLED); diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 6cb5870809..5bc8b6c22c 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -92,7 +92,38 @@ /* This is burst mode BIT 38 in IA32_MISC_ENABLE MSR at offset 1A0h */ #define BURST_MODE_DISABLE (1 << 6) -#define MSR_IA32_MISC_ENABLES 0x000001a0 +#define MSR_IA32_MISC_ENABLE 0x000001a0 + +/* MISC_ENABLE bits: architectural */ +#define MISC_ENABLE_FAST_STRING BIT_ULL(0) +#define MISC_ENABLE_TCC BIT_ULL(1) +#define MISC_DISABLE_TURBO BIT_ULL(6) +#define MISC_ENABLE_EMON BIT_ULL(7) +#define MISC_ENABLE_BTS_UNAVAIL BIT_ULL(11) +#define MISC_ENABLE_PEBS_UNAVAIL BIT_ULL(12) +#define MISC_ENABLE_ENHANCED_SPEEDSTEP BIT_ULL(16) +#define MISC_ENABLE_MWAIT BIT_ULL(18) +#define MISC_ENABLE_LIMIT_CPUID BIT_ULL(22) +#define MISC_ENABLE_XTPR_DISABLE BIT_ULL(23) +#define MISC_ENABLE_XD_DISABLE BIT_ULL(34) + +/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ +#define MISC_ENABLE_X87_COMPAT BIT_ULL(2) +#define MISC_ENABLE_TM1 BIT_ULL(3) +#define MISC_ENABLE_SPLIT_LOCK_DISABLE BIT_ULL(4) +#define MISC_ENABLE_L3CACHE_DISABLE BIT_ULL(6) +#define MISC_ENABLE_SUPPRESS_LOCK BIT_ULL(8) +#define MISC_ENABLE_PREFETCH_DISABLE BIT_ULL(9) +#define MISC_ENABLE_FERR BIT_ULL(10) +#define MISC_ENABLE_FERR_MULTIPLEX BIT_ULL(10) +#define MISC_ENABLE_TM2 BIT_ULL(13) +#define MISC_ENABLE_ADJ_PREF_DISABLE BIT_ULL(19) +#define MISC_ENABLE_SPEEDSTEP_LOCK BIT_ULL(20) +#define MISC_ENABLE_L1D_CONTEXT BIT_ULL(24) +#define MISC_ENABLE_DCU_PREF_DISABLE BIT_ULL(37) +#define MISC_ENABLE_TURBO_DISABLE BIT_ULL(38) +#define MISC_ENABLE_IP_PREF_DISABLE BIT_ULL(39) + #define MSR_TEMPERATURE_TARGET 0x1a2 #define MSR_PREFETCH_CTL 0x1a4 #define PREFETCH_L1_DISABLE (1 << 0) @@ -108,6 +139,17 @@ #define ENERGY_POLICY_NORMAL 6 #define ENERGY_POLICY_POWERSAVE 15 +#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 + +#define PACKAGE_THERM_STATUS_PROCHOT BIT(0) +#define PACKAGE_THERM_STATUS_POWER_LIMIT BIT(10) + +#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 + +#define PACKAGE_THERM_INT_HIGH_ENABLE BIT(0) +#define PACKAGE_THERM_INT_LOW_ENABLE BIT(1) +#define PACKAGE_THERM_INT_PLN_ENABLE BIT(24) + #define MSR_LBR_SELECT 0x000001c8 #define MSR_LBR_TOS 0x000001c9 #define MSR_IA32_PLATFORM_DCA_CAP 0x1f8 @@ -419,68 +461,6 @@ #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) -#define MSR_IA32_MISC_ENABLE 0x000001a0 -#define H_MISC_DISABLE_TURBO (1 << 6) - -#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 - -#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 -#define ENERGY_PERF_BIAS_PERFORMANCE 0 -#define ENERGY_PERF_BIAS_NORMAL 6 -#define ENERGY_PERF_BIAS_POWERSAVE 15 - -#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 - -#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) -#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) - -#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 - -#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) -#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) -#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) - -/* Thermal Thresholds Support */ -#define THERM_INT_THRESHOLD0_ENABLE (1 << 15) -#define THERM_SHIFT_THRESHOLD0 8 -#define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) -#define THERM_INT_THRESHOLD1_ENABLE (1 << 23) -#define THERM_SHIFT_THRESHOLD1 16 -#define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) -#define THERM_STATUS_THRESHOLD0 (1 << 6) -#define THERM_LOG_THRESHOLD0 (1 << 7) -#define THERM_STATUS_THRESHOLD1 (1 << 8) -#define THERM_LOG_THRESHOLD1 (1 << 9) - -/* MISC_ENABLE bits: architectural */ -#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) -#define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) -#define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7) -#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) -#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) -#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16) -#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) -#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22) -#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23) -#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) - -/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ -#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2) -#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3) -#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4) -#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6) -#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8) -#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9) -#define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10) -#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10) -#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13) -#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19) -#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20) -#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24) -#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37) -#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) -#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) - #define MSR_IA32_TSC_DEADLINE 0x000006E0 /* P4/Xeon+ specific */ -- cgit From a27520904f54643c9e55f5672f005a207c911f32 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:56:40 -0600 Subject: x86: Add new common CPU functions for turbo/burst mode Add a few more CPU functions that are common on Intel CPUs. Also add attribution for the code source. Signed-off-by: Simon Glass Reviewed-by: Bin Meng [bmeng: add missing MSR_IA32_MISC_ENABLE write back in cpu_set_eist(); fix 2 typos in cpu_get_burst_mode_state() comments] Signed-off-by: Bin Meng --- arch/x86/cpu/intel_common/cpu.c | 61 +++++++++++++++++++++++++++++++++++++++ arch/x86/include/asm/cpu_common.h | 49 +++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+) (limited to 'arch/x86') diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c index 1898903853..4d093a5391 100644 --- a/arch/x86/cpu/intel_common/cpu.c +++ b/arch/x86/cpu/intel_common/cpu.c @@ -1,12 +1,17 @@ // SPDX-License-Identifier: GPL-2.0 /* + * Copyright (C) 2014 Google Inc. * Copyright (c) 2016 Google, Inc + * Copyright (C) 2015-2018 Intel Corporation. + * Copyright (C) 2018 Siemens AG + * Some code taken from coreboot cpulib.c */ #include #include #include #include +#include #include #include #include @@ -165,3 +170,59 @@ bool cpu_config_tdp_levels(void) return ((platform_info.hi >> 1) & 3) != 0; } + +void cpu_set_p_state_to_turbo_ratio(void) +{ + msr_t msr; + + msr = msr_read(MSR_TURBO_RATIO_LIMIT); + cpu_set_perf_control(msr.lo); +} + +enum burst_mode_t cpu_get_burst_mode_state(void) +{ + enum burst_mode_t state; + int burst_en, burst_cap; + msr_t msr; + uint eax; + + eax = cpuid_eax(0x6); + burst_cap = eax & 0x2; + msr = msr_read(MSR_IA32_MISC_ENABLE); + burst_en = !(msr.hi & BURST_MODE_DISABLE); + + if (!burst_cap && burst_en) + state = BURST_MODE_UNAVAILABLE; + else if (burst_cap && !burst_en) + state = BURST_MODE_DISABLED; + else if (burst_cap && burst_en) + state = BURST_MODE_ENABLED; + else + state = BURST_MODE_UNKNOWN; + + return state; +} + +void cpu_set_burst_mode(bool burst_mode) +{ + msr_t msr; + + msr = msr_read(MSR_IA32_MISC_ENABLE); + if (burst_mode) + msr.hi &= ~BURST_MODE_DISABLE; + else + msr.hi |= BURST_MODE_DISABLE; + msr_write(MSR_IA32_MISC_ENABLE, msr); +} + +void cpu_set_eist(bool eist_status) +{ + msr_t msr; + + msr = msr_read(MSR_IA32_MISC_ENABLE); + if (eist_status) + msr.lo |= MISC_ENABLE_ENHANCED_SPEEDSTEP; + else + msr.lo &= ~MISC_ENABLE_ENHANCED_SPEEDSTEP; + msr_write(MSR_IA32_MISC_ENABLE, msr); +} diff --git a/arch/x86/include/asm/cpu_common.h b/arch/x86/include/asm/cpu_common.h index c61d74e4a0..cdd99a90b7 100644 --- a/arch/x86/include/asm/cpu_common.h +++ b/arch/x86/include/asm/cpu_common.h @@ -79,4 +79,53 @@ void cpu_set_perf_control(uint clk_ratio); */ bool cpu_config_tdp_levels(void); +/** enum burst_mode_t - Burst-mode states */ +enum burst_mode_t { + BURST_MODE_UNKNOWN, + BURST_MODE_UNAVAILABLE, + BURST_MODE_DISABLED, + BURST_MODE_ENABLED +}; + +/* + * cpu_get_burst_mode_state() - Get the Burst/Turbo Mode State + * + * This reads MSR IA32_MISC_ENABLE 0x1A0 + * Bit 38 - TURBO_MODE_DISABLE Bit to get state ENABLED / DISABLED. + * Also checks cpuid 0x6 to see whether burst mode is supported. + * + * @return current burst mode status + */ +enum burst_mode_t cpu_get_burst_mode_state(void); + +/** + * cpu_set_burst_mode() - Set CPU burst mode + * + * @burst_mode: true to enable burst mode, false to disable + */ +void cpu_set_burst_mode(bool burst_mode); + +/** + * cpu_set_eist() - Enable Enhanced Intel Speed Step Technology + * + * @eist_status: true to enable EIST, false to disable + */ +void cpu_set_eist(bool eist_status); + +/** + * cpu_set_p_state_to_turbo_ratio() - Set turbo ratio + * + * TURBO_RATIO_LIMIT MSR (0x1AD) Bits 31:0 indicates the + * factory configured values for of 1-core, 2-core, 3-core + * and 4-core turbo ratio limits for all processors. + * + * 7:0 - MAX_TURBO_1_CORE + * 15:8 - MAX_TURBO_2_CORES + * 23:16 - MAX_TURBO_3_CORES + * 31:24 - MAX_TURBO_4_CORES + * + * Set PERF_CTL MSR (0x199) P_Req with that value. + */ +void cpu_set_p_state_to_turbo_ratio(void); + #endif -- cgit From 12e927b0a842408467fe7dbe627ca350d2300348 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:56:43 -0600 Subject: x86: Allow the PCH and LPC uclasses to work with of-platdata At present these uclasses assumes that they are used with a device tree. Update them to support of-platdata as well. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/lib/lpc-uclass.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/x86') diff --git a/arch/x86/lib/lpc-uclass.c b/arch/x86/lib/lpc-uclass.c index 505d7a943d..1302a6e34a 100644 --- a/arch/x86/lib/lpc-uclass.c +++ b/arch/x86/lib/lpc-uclass.c @@ -10,5 +10,7 @@ UCLASS_DRIVER(lpc) = { .id = UCLASS_LPC, .name = "lpc", +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) .post_bind = dm_scan_fdt_dev, +#endif }; -- cgit From 6ccb2f890bb5bfdd6aed4a99294fd77508436c40 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:56:45 -0600 Subject: x86: Refactor mtrr_commit() to allow for shared code Move the code that actually sets up the MTRR into another function so it can be used elsewhere in the file. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/cpu/mtrr.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c index 0939736164..6218d149e3 100644 --- a/arch/x86/cpu/mtrr.c +++ b/arch/x86/cpu/mtrr.c @@ -50,11 +50,20 @@ void mtrr_close(struct mtrr_state *state, bool do_caches) enable_caches(); } +static void set_var_mtrr(uint reg, uint type, uint64_t start, uint64_t size) +{ + u64 mask; + + wrmsrl(MTRR_PHYS_BASE_MSR(reg), start | type); + mask = ~(size - 1); + mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1; + wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask | MTRR_PHYS_MASK_VALID); +} + int mtrr_commit(bool do_caches) { struct mtrr_request *req = gd->arch.mtrr_req; struct mtrr_state state; - uint64_t mask; int i; debug("%s: enabled=%d, count=%d\n", __func__, gd->arch.has_mtrr, @@ -65,12 +74,8 @@ int mtrr_commit(bool do_caches) debug("open\n"); mtrr_open(&state, do_caches); debug("open done\n"); - for (i = 0; i < gd->arch.mtrr_req_count; i++, req++) { - mask = ~(req->size - 1); - mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1; - wrmsrl(MTRR_PHYS_BASE_MSR(i), req->start | req->type); - wrmsrl(MTRR_PHYS_MASK_MSR(i), mask | MTRR_PHYS_MASK_VALID); - } + for (i = 0; i < gd->arch.mtrr_req_count; i++, req++) + set_var_mtrr(i, req->type, req->start, req->size); /* Clear the ones that are unused */ debug("clear\n"); -- cgit From add3f4c9186fbd94b6e89c1d277b544a7a6ad404 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:56:46 -0600 Subject: x86: Add a function to set variable MTRRs Normally U-Boot handles MTRRs through an add/commit process which overwrites all MTRRs. But in very early boot it is not desirable to clear the existing MTRRs since they may be in use and it can cause a hang. Add a new mtrr_set_next_var() function which sets up the next available MTRR to the required region. Signed-off-by: Simon Glass Reviewed-by: Bin Meng [bmeng: pass 'type' to set_var_mtrr() in mtrr_set_next_var()] Signed-off-by: Bin Meng --- arch/x86/cpu/mtrr.c | 38 ++++++++++++++++++++++++++++++++++++++ arch/x86/include/asm/mtrr.h | 12 ++++++++++++ 2 files changed, 50 insertions(+) (limited to 'arch/x86') diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c index 6218d149e3..a00db422e7 100644 --- a/arch/x86/cpu/mtrr.c +++ b/arch/x86/cpu/mtrr.c @@ -112,3 +112,41 @@ int mtrr_add_request(int type, uint64_t start, uint64_t size) return 0; } + +static int get_var_mtrr_count(void) +{ + return msr_read(MSR_MTRR_CAP_MSR).lo & MSR_MTRR_CAP_VCNT; +} + +static int get_free_var_mtrr(void) +{ + struct msr_t maskm; + int vcnt; + int i; + + vcnt = get_var_mtrr_count(); + + /* Identify the first var mtrr which is not valid */ + for (i = 0; i < vcnt; i++) { + maskm = msr_read(MTRR_PHYS_MASK_MSR(i)); + if ((maskm.lo & MTRR_PHYS_MASK_VALID) == 0) + return i; + } + + /* No free var mtrr */ + return -ENOSPC; +} + +int mtrr_set_next_var(uint type, uint64_t start, uint64_t size) +{ + int mtrr; + + mtrr = get_free_var_mtrr(); + if (mtrr < 0) + return mtrr; + + set_var_mtrr(mtrr, type, start, size); + debug("MTRR %x: start=%x, size=%x\n", mtrr, (uint)start, (uint)size); + + return 0; +} diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index 6f29e75ce6..672617256e 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -117,6 +117,18 @@ int mtrr_add_request(int type, uint64_t start, uint64_t size); */ int mtrr_commit(bool do_caches); +/** + * mtrr_set_next_var() - set up a variable MTRR + * + * This finds the first free variable MTRR and sets to the given area + * + * @type: Requested type (MTRR_TYPE_) + * @start: Start address + * @size: Size + * @return 0 on success, -ENOSPC if there are no more MTRRs + */ +int mtrr_set_next_var(uint type, uint64_t base, uint64_t size); + #endif #if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0) -- cgit From b377ebbd5b8fc371b0b27dd3551f2cc3718757dc Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:56:48 -0600 Subject: x86: cpu: Don't include the cpu driver in TPL We don't need this driver very early in boot and it adds code size. Drop it. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/cpu/Makefile | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/x86') diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 3f1f62da2b..6296b55ff8 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -26,7 +26,10 @@ endif extra-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += resetvec.o start16.o -obj-y += cpu.o cpu_x86.o +obj-y += cpu.o +ifndef CONFIG_TPL_BUILD +obj-y += cpu_x86.o +endif ifndef CONFIG_$(SPL_)X86_64 AFLAGS_REMOVE_call32.o := -mregparm=3 \ -- cgit From cc2d27dcdc3e1c76d09d54015e3992380bd7e0fa Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 25 Sep 2019 08:56:49 -0600 Subject: x86: Use mtrr_commit() with FSP2 With FSP2 we use MTRRs in U-Boot proper even though the 32-bit init happens in TPL. Enable this, using a variable to try to make the conditions more palatable. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/lib/init_helpers.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) (limited to 'arch/x86') diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index 4774a9bdb7..3e3a11ac2f 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -12,15 +12,23 @@ DECLARE_GLOBAL_DATA_PTR; int init_cache_f_r(void) { -#if CONFIG_IS_ENABLED(X86_32BIT_INIT) && !defined(CONFIG_HAVE_FSP) && \ - !defined(CONFIG_SYS_SLIMBOOTLOADER) + bool do_mtrr = CONFIG_IS_ENABLED(X86_32BIT_INIT) || + IS_ENABLED(CONFIG_FSP_VERSION2); int ret; - ret = mtrr_commit(false); - /* If MTRR MSR is not implemented by the processor, just ignore it */ - if (ret && ret != -ENOSYS) - return ret; -#endif + do_mtrr &= !IS_ENABLED(CONFIG_FSP_VERSION1) && + !IS_ENABLED(CONFIG_SYS_SLIMBOOTLOADER); + + if (do_mtrr) { + ret = mtrr_commit(false); + /* + * If MTRR MSR is not implemented by the processor, just ignore + * it + */ + if (ret && ret != -ENOSYS) + return ret; + } + /* Initialise the CPU cache(s) */ return init_cache(); } -- cgit