From 22a1b99a1dd82cb06d05de81a8bc3c52f8b0b5bb Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 1 Dec 2016 18:37:55 -0800 Subject: powerpc: cyrus: Separate P5020/P5040 config options Instead of using EXTRA options in defconfig, use two targets in Kconfig to select correct SoC. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc85xx/Kconfig | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 3ee7d2f0c5..9a5cd85399 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -309,8 +309,14 @@ config TARGET_UCP1020 bool "Support uCP1020" select ARCH_P1020 -config TARGET_CYRUS - bool "Support Varisys Cyrus" +config TARGET_CYRUS_P5020 + bool "Support Varisys Cyrus P5020" + select ARCH_P5020 + select PHYS_64BIT + +config TARGET_CYRUS_P5040 + bool "Support Varisys Cyrus P5040" + select ARCH_P5040 select PHYS_64BIT endchoice -- cgit From 830fc1bfe7c0c735c479804ce66c1c6a705260ee Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 1 Dec 2016 13:26:06 -0800 Subject: powerpc: mpc85xx: Convert CONFIG_SYS_CCSRBAR_DEFAULT to Kconfig option Move default value definitions to to Kconfig SYS_CCSRBAR_DEFAULT. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc85xx/Kconfig | 50 +++++++++++++++++++++++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 41 ------------------------- 2 files changed, 50 insertions(+), 41 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 9a5cd85399..1d2e027b78 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -471,6 +471,56 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores. +config SYS_CCSRBAR_DEFAULT + hex "Default CCSRBAR address" + default 0xff700000 if ARCH_BSC9131 || \ + ARCH_BSC9132 || \ + ARCH_C29X || \ + ARCH_MPC8536 || \ + ARCH_MPC8540 || \ + ARCH_MPC8541 || \ + ARCH_MPC8544 || \ + ARCH_MPC8548 || \ + ARCH_MPC8555 || \ + ARCH_MPC8560 || \ + ARCH_MPC8568 || \ + ARCH_MPC8569 || \ + ARCH_MPC8572 || \ + ARCH_P1010 || \ + ARCH_P1011 || \ + ARCH_P1020 || \ + ARCH_P1021 || \ + ARCH_P1022 || \ + ARCH_P1024 || \ + ARCH_P1025 || \ + ARCH_P2020 + default 0xff600000 if ARCH_P1023 + default 0xfe000000 if ARCH_B4420 || \ + ARCH_B4860 || \ + ARCH_P2041 || \ + ARCH_P3041 || \ + ARCH_P4080 || \ + ARCH_P5020 || \ + ARCH_P5040 || \ + ARCH_T1013 || \ + ARCH_T1014 || \ + ARCH_T1020 || \ + ARCH_T1022 || \ + ARCH_T1023 || \ + ARCH_T1024 || \ + ARCH_T1040 || \ + ARCH_T1042 || \ + ARCH_T2080 || \ + ARCH_T2081 || \ + ARCH_T4160 || \ + ARCH_T4240 + default 0xe0000000 if ARCH_QEMU_E500 + help + Default value of CCSRBAR comes from power-on-reset. It + is fixed on each SoC. Some SoCs can have different value + if changed by pre-boot regime. The value here must match + the current value in SoC. If not sure, do not change. + source "board/freescale/b4860qds/Kconfig" source "board/freescale/bsc9131rdb/Kconfig" source "board/freescale/bsc9132qds/Kconfig" diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index c92bc1ec40..474fd1af7d 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -9,10 +9,6 @@ /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ -#ifdef CONFIG_SYS_CCSRBAR_DEFAULT -#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." -#endif - /* * This macro should be removed when we no longer care about backwards * compatibility with older operating systems. @@ -39,27 +35,23 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_ARCH_MPC8540) #define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_DDRC_GEN1 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_ARCH_MPC8541) #define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_DDRC_GEN1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_ARCH_MPC8544) #define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 #define CONFIG_SYS_FSL_SEC_COMPAT 2 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_ARCH_MPC8548) @@ -67,7 +59,6 @@ #define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 #define CONFIG_SYS_FSL_SEC_COMPAT 2 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 @@ -84,12 +75,10 @@ #define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_DDRC_GEN1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_ARCH_MPC8560) #define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_DDRC_GEN1 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_ARCH_MPC8568) #define CONFIG_SYS_FSL_NUM_LAWS 10 @@ -98,7 +87,6 @@ #define QE_MURAM_SIZE 0x10000UL #define MAX_QE_RISC 2 #define QE_NUM_OF_SNUM 28 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -111,7 +99,6 @@ #define QE_MURAM_SIZE 0x20000UL #define MAX_QE_RISC 4 #define QE_NUM_OF_SNUM 46 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -124,7 +111,6 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 #define CONFIG_SYS_FSL_ERRATUM_A004508 @@ -140,7 +126,6 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 @@ -165,7 +150,6 @@ #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_A004508 @@ -177,7 +161,6 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_A004508 @@ -192,7 +175,6 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define QE_MURAM_SIZE 0x6000UL @@ -208,7 +190,6 @@ #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_FSL_SATA_ERRATUM_A001 @@ -227,7 +208,6 @@ #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 @@ -241,7 +221,6 @@ #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_A004508 @@ -255,7 +234,6 @@ #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define QE_MURAM_SIZE 0x6000UL @@ -268,7 +246,6 @@ #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 @@ -295,7 +272,6 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY @@ -332,7 +308,6 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY @@ -374,7 +349,6 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 @@ -423,7 +397,6 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY @@ -460,7 +433,6 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY @@ -486,7 +458,6 @@ #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_NAND_FSL_IFC #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_A005125 @@ -507,7 +478,6 @@ #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_NAND_FSL_IFC #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK @@ -575,7 +545,6 @@ #define CONFIG_SYS_FSL_ERRATUM_A007186 #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_FSL_ERRATUM_A007798 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_PCI_VER_3_X @@ -618,7 +587,6 @@ #define CONFIG_SYS_FSL_ERRATUM_A006384 #define CONFIG_SYS_FSL_ERRATUM_A007212 #define CONFIG_SYS_FSL_ERRATUM_A004477 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_SFP_VER_3_0 #ifdef CONFIG_ARCH_B4860 @@ -681,7 +649,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define QE_MURAM_SIZE 0x6000UL @@ -725,7 +692,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define QE_MURAM_SIZE 0x6000UL @@ -778,7 +744,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_A007212 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_ISBC_VER 2 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -799,22 +764,16 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000 #elif defined(CONFIG_ARCH_QEMU_E500) -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000 #else #error Processor type not defined for this platform #endif -#ifndef CONFIG_SYS_CCSRBAR_DEFAULT -#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." -#endif - #ifdef CONFIG_E6500 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 #else -- cgit From 4a1e6810a2c0e7879583cf4cca53476219dc5203 Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 1 Dec 2016 13:32:46 -0800 Subject: powerpc: mpc86xx: Convert CONFIG_SYS_CCSRBAR_DEFAULT to Kconfig option Move default value definitions to Kconfig SYS_CCSRBAR_DEFAULT. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc86xx/Kconfig | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig index 98fb702e86..57e7476ca7 100644 --- a/arch/powerpc/cpu/mpc86xx/Kconfig +++ b/arch/powerpc/cpu/mpc86xx/Kconfig @@ -32,6 +32,15 @@ config ARCH_MPC8610 config ARCH_MPC8641 bool +config SYS_CCSRBAR_DEFAULT + hex "Default CCSRBAR address" + default 0xff700000 if ARCH_MPC8610 || ARCH_MPC8641 + help + Default value of CCSRBAR comes from power-on-reset. It + is fixed on each SoC. Some SoCs can have different value + if changed by pre-boot regime. The value here must match + the current value in SoC. If not sure, do not change. + source "board/freescale/mpc8610hpcd/Kconfig" source "board/freescale/mpc8641hpcn/Kconfig" source "board/sbc8641d/Kconfig" -- cgit From 86d8000f105c7a2d0846dbf60831bcfa0967d079 Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 1 Dec 2016 13:43:06 -0800 Subject: script: remove CONFIG_SYS_CCSRBAR_DEFAULT from white list Now all mpc85xx and mpc86xx have converted to use SYS_CCSRBAR_DEFAULT in Kconfig. Drop this macro for LSCH2 and remove from white list. Signed-off-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 - arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 4 ++-- 2 files changed, 2 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 6c3ba494f8..c50894a618 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -138,7 +138,6 @@ #define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000 #define CONFIG_SYS_FSL_CCSR_SCFG_BE #define CONFIG_SYS_FSL_ESDHC_BE diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index d88543d063..d684a07730 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -120,7 +120,7 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." #endif #ifndef CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT +#define CONFIG_SYS_CCSRBAR 0x01000000 #endif #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH @@ -128,7 +128,7 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." #endif #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT +#define CONFIG_SYS_CCSRBAR_PHYS_LOW 0x01000000 #endif #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ -- cgit From 72ccd31e644dcbcc889cfc83b191b33c43db5379 Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 2 Dec 2016 09:31:43 -0800 Subject: armv7: ls1021a: Move SECURE_BOOT option to Kconfig Move from CONFIG_SYS_EXTRA_OPTIONS to Kconfig option. Signed-off-by: York Sun --- arch/arm/cpu/armv7/ls102xa/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 28bf778d9c..f94568a2e4 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -28,6 +28,12 @@ config NUM_DDR_CONTROLLERS int "Maximum DDR controllers" default 1 +config SECURE_BOOT + bool "Secure Boot" + help + Enable Freescale Secure Boot feature. Normally selected + by defconfig. If unsure, do not change. + config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315" -- cgit From 01f65d974a3f4a05ea258269e52834bed3547bdf Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 2 Dec 2016 09:32:35 -0800 Subject: armv8: fsl-layerscape: Move SECURE_BOOT to Kconfig Move from CONFIG_SYS_EXTRA_OPTIONS to Kconfig option. Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 94ec8d502b..ed1c4eeb03 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -71,6 +71,11 @@ config NUM_DDR_CONTROLLERS default 3 if ARCH_LS2080A default 1 +config SECURE_BOOT + bool + help + Enable Freescale Secure Boot feature + config SYS_FSL_IFC_BANK_COUNT int "Maximum banks of Integrated flash controller" depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A -- cgit From c6e6bda3a873fe036b30746195b59339d10e3cdf Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 2 Dec 2016 09:33:14 -0800 Subject: powerpc: mpc85xx: Move SECURE_BOOT to Kconfig Move from CONFIG_SYS_EXTRA_OPTIONS to Kconfig option. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc85xx/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 1d2e027b78..f782695274 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -435,6 +435,12 @@ config ARCH_T4160 config ARCH_T4240 bool +config SECURE_BOOT + bool "Secure Boot" + help + Enable Freescale Secure Boot feature. Normally selected + by defconfig. If unsure, do not change. + config MAX_CPUS int "Maximum number of CPUs permitted for MPC85xx" default 12 if ARCH_T4240 -- cgit From 05cb79a72cc3b99a0238e8b8eeec6d3ffd8b0674 Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 2 Dec 2016 10:44:34 -0800 Subject: powerpc: mpc85xx: Move CONFIG_FSL_LAW to Kconfig Some header files have this macro defined conditionally and redefined unconditionally. Remove all existing definitions. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc85xx/Kconfig | 42 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index f782695274..ec58cd12fc 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -323,117 +323,159 @@ endchoice config ARCH_B4420 bool + select FSL_LAW config ARCH_B4860 bool + select FSL_LAW config ARCH_BSC9131 bool + select FSL_LAW config ARCH_BSC9132 bool + select FSL_LAW config ARCH_C29X bool + select FSL_LAW config ARCH_MPC8536 bool + select FSL_LAW config ARCH_MPC8540 bool + select FSL_LAW config ARCH_MPC8541 bool + select FSL_LAW config ARCH_MPC8544 bool + select FSL_LAW config ARCH_MPC8548 bool + select FSL_LAW config ARCH_MPC8555 bool + select FSL_LAW config ARCH_MPC8560 bool + select FSL_LAW config ARCH_MPC8568 bool + select FSL_LAW config ARCH_MPC8569 bool + select FSL_LAW config ARCH_MPC8572 bool + select FSL_LAW config ARCH_P1010 bool + select FSL_LAW config ARCH_P1011 bool + select FSL_LAW config ARCH_P1020 bool + select FSL_LAW config ARCH_P1021 bool + select FSL_LAW config ARCH_P1022 bool + select FSL_LAW config ARCH_P1023 bool + select FSL_LAW config ARCH_P1024 bool + select FSL_LAW config ARCH_P1025 bool + select FSL_LAW config ARCH_P2020 bool + select FSL_LAW config ARCH_P2041 bool + select FSL_LAW config ARCH_P3041 bool + select FSL_LAW config ARCH_P4080 bool + select FSL_LAW config ARCH_P5020 bool + select FSL_LAW config ARCH_P5040 bool + select FSL_LAW config ARCH_QEMU_E500 bool config ARCH_T1023 bool + select FSL_LAW config ARCH_T1024 bool + select FSL_LAW config ARCH_T1040 bool + select FSL_LAW config ARCH_T1042 bool + select FSL_LAW config ARCH_T2080 bool + select FSL_LAW config ARCH_T2081 bool + select FSL_LAW config ARCH_T4160 bool + select FSL_LAW config ARCH_T4240 bool + select FSL_LAW + +config FSL_LAW + bool + help + Use Freescale common code for Local Access Window config SECURE_BOOT bool "Secure Boot" -- cgit From f4325b47a8e79676c94b85c0a75f14626bb6d9c3 Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 2 Dec 2016 10:45:23 -0800 Subject: powerpc: mpc86xx: Move CONFIG_FSL_LAW to Kconfig Clean up existing definitions and drop from white list. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc86xx/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig index 57e7476ca7..42b2ed2666 100644 --- a/arch/powerpc/cpu/mpc86xx/Kconfig +++ b/arch/powerpc/cpu/mpc86xx/Kconfig @@ -28,9 +28,16 @@ endchoice config ARCH_MPC8610 bool + select FSL_LAW config ARCH_MPC8641 bool + select FSL_LAW + +config FSL_LAW + bool + help + Use Freescale common code for Local Access Window config SYS_CCSRBAR_DEFAULT hex "Default CCSRBAR address" -- cgit From 8303acbce8269048b29ee72b33ebbfadef41b6f2 Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 1 Dec 2016 14:05:02 -0800 Subject: powerpc: mpc85xx: Convert CONFIG_SYS_FSL_NUM_LAWS to Kconfig option Move the macro to Kconfig SYS_FSL_NUM_LAWS. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc85xx/Kconfig | 48 +++++++++++++++++++++++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 32 --------------------- 2 files changed, 48 insertions(+), 32 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index ec58cd12fc..e4873f5e82 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -569,6 +569,54 @@ config SYS_CCSRBAR_DEFAULT if changed by pre-boot regime. The value here must match the current value in SoC. If not sure, do not change. +config SYS_FSL_NUM_LAWS + int "Number of local access windows" + depends on FSL_LAW + default 32 if ARCH_B4420 || \ + ARCH_B4860 || \ + ARCH_P2041 || \ + ARCH_P3041 || \ + ARCH_P4080 || \ + ARCH_P5020 || \ + ARCH_P5040 || \ + ARCH_T2080 || \ + ARCH_T2081 || \ + ARCH_T4160 || \ + ARCH_T4240 + default 16 if ARCH_T1013 || \ + ARCH_T1014 || \ + ARCH_T1020 || \ + ARCH_T1022 || \ + ARCH_T1023 || \ + ARCH_T1024 || \ + ARCH_T1040 || \ + ARCH_T1042 + default 12 if ARCH_BSC9131 || \ + ARCH_BSC9132 || \ + ARCH_C29X || \ + ARCH_MPC8536 || \ + ARCH_MPC8572 || \ + ARCH_P1010 || \ + ARCH_P1011 || \ + ARCH_P1020 || \ + ARCH_P1021 || \ + ARCH_P1022 || \ + ARCH_P1023 || \ + ARCH_P1024 || \ + ARCH_P1025 || \ + ARCH_P2020 + default 10 if ARCH_MPC8544 || \ + ARCH_MPC8548 || \ + ARCH_MPC8568 || \ + ARCH_MPC8569 + default 8 if ARCH_MPC8540 || \ + ARCH_MPC8541 || \ + ARCH_MPC8555 || \ + ARCH_MPC8560 + help + Number of local access windows. This is fixed per SoC. + If not sure, do not change. + source "board/freescale/b4860qds/Kconfig" source "board/freescale/bsc9131rdb/Kconfig" source "board/freescale/bsc9132qds/Kconfig" diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 474fd1af7d..4877b75981 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -32,30 +32,25 @@ #endif #if defined(CONFIG_ARCH_MPC8536) -#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_ARCH_MPC8540) -#define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_DDRC_GEN1 #elif defined(CONFIG_ARCH_MPC8541) -#define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_DDRC_GEN1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #elif defined(CONFIG_ARCH_MPC8544) -#define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_ARCH_MPC8548) -#define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -72,16 +67,13 @@ #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 #elif defined(CONFIG_ARCH_MPC8555) -#define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_DDRC_GEN1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #elif defined(CONFIG_ARCH_MPC8560) -#define CONFIG_SYS_FSL_NUM_LAWS 8 #define CONFIG_SYS_FSL_DDRC_GEN1 #elif defined(CONFIG_ARCH_MPC8568) -#define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define QE_MURAM_SIZE 0x10000UL @@ -94,7 +86,6 @@ #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 #elif defined(CONFIG_ARCH_MPC8569) -#define CONFIG_SYS_FSL_NUM_LAWS 10 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define QE_MURAM_SIZE 0x20000UL #define MAX_QE_RISC 4 @@ -108,7 +99,6 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_ARCH_MPC8572) -#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 @@ -118,7 +108,6 @@ #elif defined(CONFIG_ARCH_P1010) #define CONFIG_FSL_SDHC_V2_3 -#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 @@ -144,7 +133,6 @@ /* P1011 is single core version of P1020 */ #elif defined(CONFIG_ARCH_P1011) -#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM @@ -156,7 +144,6 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_ARCH_P1020) -#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM @@ -170,7 +157,6 @@ #endif #elif defined(CONFIG_ARCH_P1021) -#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM @@ -185,7 +171,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #elif defined(CONFIG_ARCH_P1022) -#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -198,7 +183,6 @@ #define CONFIG_SYS_FSL_ERRATUM_A004477 #elif defined(CONFIG_ARCH_P1023) -#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 2 @@ -215,7 +199,6 @@ /* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_ARCH_P1024) -#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM @@ -228,7 +211,6 @@ /* P1025 is lower end variant of P1021 */ #elif defined(CONFIG_ARCH_P1025) -#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 @@ -243,7 +225,6 @@ #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_ARCH_P2020) -#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -262,7 +243,6 @@ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 -#define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 @@ -298,7 +278,6 @@ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 -#define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 @@ -336,7 +315,6 @@ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 -#define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 2 #define CONFIG_SYS_NUM_FM1_DTSEC 4 @@ -386,7 +364,6 @@ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 -#define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 @@ -420,7 +397,6 @@ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 -#define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 2 #define CONFIG_SYS_NUM_FM1_DTSEC 5 @@ -449,7 +425,6 @@ #elif defined(CONFIG_ARCH_BSC9131) #define CONFIG_FSL_SDHC_V2_3 -#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_NUM_DDR_CONTROLLERS 1 @@ -467,7 +442,6 @@ #elif defined(CONFIG_ARCH_BSC9132) #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 #define CONFIG_FSL_SDHC_V2_3 -#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_NUM_DDR_CONTROLLERS 2 @@ -515,7 +489,6 @@ #endif #endif #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 -#define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 #define CONFIG_SYS_FSL_SRDS_3 @@ -557,7 +530,6 @@ #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */ #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/ #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/ -#define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 #define CONFIG_SYS_MAPLE @@ -625,7 +597,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #endif #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } -#define CONFIG_SYS_FSL_NUM_LAWS 16 #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_SYS_NUM_FMAN 1 @@ -671,7 +642,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #endif #define CONFIG_SYS_FSL_NUM_CC_PLL 2 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } -#define CONFIG_SYS_FSL_NUM_LAWS 16 #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_SYS_NUM_FMAN 1 @@ -709,7 +679,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_QMAN_V3 -#define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } @@ -756,7 +725,6 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #elif defined(CONFIG_ARCH_C29X) #define CONFIG_FSL_SDHC_V2_3 -#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 #define CONFIG_TSECV2_1 #define CONFIG_SYS_FSL_SEC_COMPAT 6 -- cgit From 54db3c20bdc43c458854446939b706b4adee46cf Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 1 Dec 2016 14:10:47 -0800 Subject: powerpc: mpc86xx: Convert CONFIG_SYS_FSL_NUM_LAWS to Kconfig option Use Kconfig instead of defining this macro in header file. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc86xx/Kconfig | 6 ++++++ arch/powerpc/include/asm/config_mpc86xx.h | 12 ------------ 2 files changed, 6 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig index 42b2ed2666..11afffa830 100644 --- a/arch/powerpc/cpu/mpc86xx/Kconfig +++ b/arch/powerpc/cpu/mpc86xx/Kconfig @@ -47,6 +47,12 @@ config SYS_CCSRBAR_DEFAULT is fixed on each SoC. Some SoCs can have different value if changed by pre-boot regime. The value here must match the current value in SoC. If not sure, do not change. +config SYS_FSL_NUM_LAWS + int "Number of local access windows" + default 10 if ARCH_MPC8610 || ARCH_MPC8641 + help + Number of local access windows. This is fixed per SoC. + If not sure, do not change. source "board/freescale/mpc8610hpcd/Kconfig" source "board/freescale/mpc8641hpcn/Kconfig" diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h index c41dc99681..f053b9cf5e 100644 --- a/arch/powerpc/include/asm/config_mpc86xx.h +++ b/arch/powerpc/include/asm/config_mpc86xx.h @@ -9,16 +9,4 @@ #define CONFIG_SYS_FSL_DDR_86XX -/* SoC specific defines for Freescale MPC86xx processors */ - -#if defined(CONFIG_ARCH_MPC8610) -#define CONFIG_SYS_FSL_NUM_LAWS 10 - -#elif defined(CONFIG_ARCH_MPC8641) -#define CONFIG_SYS_FSL_NUM_LAWS 10 - -#else -#error Processor type not defined for this platform -#endif - #endif /* _ASM_MPC85xx_CONFIG_H_ */ -- cgit