From f6cb427fdc1d2c4236f0a9bc97068c30ca228282 Mon Sep 17 00:00:00 2001 From: Marcus Comstedt Date: Sun, 11 Aug 2019 14:45:29 +0200 Subject: riscv: update fix_rela_dyn The addend is now added for RELOC_TYPE relocs. Also, changed the loop structure so that all the R_RISCV_RELATIVE relocs are not required to be at the beginning of the list. Signed-off-by: Marcus Comstedt Cc: Rick Chen --- arch/riscv/cpu/start.S | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index b15209d623..0a2ce6d691 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -269,7 +269,7 @@ fix_rela_dyn: /* * skip first reserved entry: address, type, addend */ - bne t1, t2, 7f + j 10f 6: LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */ @@ -280,9 +280,7 @@ fix_rela_dyn: add t5, t5, t6 /* t5 <-- location to fix up in RAM */ add t3, t3, t6 /* t3 <-- location to fix up in RAM */ SREG t5, 0(t3) -7: - addi t1, t1, (REGBYTES*3) - ble t1, t2, 6b + j 10f 8: la t4, __dyn_sym_start @@ -299,13 +297,15 @@ fix_rela_dyn: li t5, SYM_SIZE mul t0, t0, t5 add s5, t4, t0 + LREG t0, -(REGBYTES)(t1) /* t0 <-- addend */ LREG t5, REGBYTES(s5) + add t5, t5, t0 add t5, t5, t6 /* t5 <-- location to fix up in RAM */ add t3, t3, t6 /* t3 <-- location to fix up in RAM */ SREG t5, 0(t3) 10: addi t1, t1, (REGBYTES*3) - ble t1, t2, 9b + ble t1, t2, 6b /* * trap update -- cgit From d58b0a6ee10710b259412fdeaf0eb24474af8401 Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Wed, 21 Aug 2019 11:26:50 +0800 Subject: riscv: andes_plic: init plic by scanning each cpu node Initialize plic driver by ofnode_for_each_subnode() instead of cpu_get_count(). This way can support to skip some harts which maybe marked as unavailable, but the cpu node exists indeed. Signed-off-by: Rick Chen Cc: KC Lin Reviewed-by: Bin Meng --- arch/riscv/lib/andes_plic.c | 36 +++++++++++++++++++++++++----------- 1 file changed, 25 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c index 2ffe49ac90..28568e4e2b 100644 --- a/arch/riscv/lib/andes_plic.c +++ b/arch/riscv/lib/andes_plic.c @@ -44,15 +44,12 @@ static int init_plic(void); } \ } while (0) -static int enable_ipi(int harts) +static int enable_ipi(int hart) { - int i; - int en = ENABLE_HART_IPI; + int en; - for (i = 0; i < harts; i++) { - en = en >> i; - writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, i)); - } + en = ENABLE_HART_IPI >> hart; + writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); return 0; } @@ -60,18 +57,35 @@ static int enable_ipi(int harts) static int init_plic(void) { struct udevice *dev; + ofnode node; int ret; + u32 reg; ret = uclass_find_first_device(UCLASS_CPU, &dev); if (ret) return ret; if (ret == 0 && dev) { - ret = cpu_get_count(dev); - if (ret < 0) - return ret; + ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) { + const char *device_type; + + device_type = ofnode_read_string(node, "device_type"); + if (!device_type) + continue; + + if (strcmp(device_type, "cpu")) + continue; + + /* skip if hart is marked as not available */ + if (!ofnode_is_available(node)) + continue; + + /* read hart ID of CPU */ + ret = ofnode_read_u32(node, "reg", ®); + if (ret == 0) + enable_ipi(reg); + } - enable_ipi(ret); return 0; } -- cgit From a8323d1816c978c012ea2fbbc844f0cbd5c82bdc Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Thu, 29 Aug 2019 10:30:13 +0800 Subject: riscv: ax25: add imply v5l2 cache controller Select the v5l2 UCLASS_CACHE driver for ax25. Signed-off-by: Rick Chen Cc: KC Lin Reviewed-by: Bin Meng --- arch/riscv/cpu/ax25/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index f4b59cb71d..d411a79c21 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/ax25/Kconfig @@ -6,6 +6,7 @@ config RISCV_NDS imply RISCV_TIMER imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE) imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE) + imply V5L2_CACHE help Run U-Boot on AndeStar V5 platforms and use some specific features which are provided by Andes Technology AndeStar V5 families. -- cgit From 7045ed9f1ad9bb2b8d19f3b5d39d7e1be8da36a6 Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Wed, 28 Aug 2019 18:46:09 +0800 Subject: riscv: cache: Flush L2 cache before jump to linux Flush and disable L2 cache in dcache_disable() which will be called in cleanup_before_linux() before jump to linux. The sequence will be preferred as below: L1 flush -> L1 disable -> L2 flush -> L2 disable Signed-off-by: Rick Chen Cc: KC Lin Reviewed-by: Bin Meng --- arch/riscv/cpu/ax25/cache.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch') diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index cd95058d9d..8f5455e519 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/ax25/cache.c @@ -5,6 +5,9 @@ */ #include +#include +#include +#include void flush_dcache_all(void) { @@ -59,11 +62,18 @@ void dcache_enable(void) { #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE + struct udevice *dev = NULL; + asm volatile ( "csrr t1, mcache_ctl\n\t" "ori t0, t1, 0x2\n\t" "csrw mcache_ctl, t0\n\t" ); + + uclass_find_first_device(UCLASS_CACHE, &dev); + + if (dev) + cache_enable(dev); #endif #endif } @@ -72,12 +82,19 @@ void dcache_disable(void) { #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE + struct udevice *dev = NULL; + asm volatile ( "fence\n\t" "csrr t1, mcache_ctl\n\t" "andi t0, t1, ~0x2\n\t" "csrw mcache_ctl, t0\n\t" ); + + uclass_find_first_device(UCLASS_CACHE, &dev); + + if (dev) + cache_disable(dev); #endif #endif } -- cgit From cf6ee112d802bc378172cfa5db3a430509cc82d8 Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Wed, 28 Aug 2019 18:46:10 +0800 Subject: riscv: dts: move out AE350 L2 node from cpus node When L2 node exists inside cpus node, uclass_get_device can not parse L2 node successfully. So move it outside from cpus node. Also add tag-ram-ctl and data-ram-ctl attributes for v5l2 cache controller driver. This can adjust timing by requirement from dtb to improve performance. Signed-off-by: Rick Chen Cc: KC Lin Reviewed-by: Bin Meng --- arch/riscv/dts/ae350_32.dts | 17 +++++++++++------ arch/riscv/dts/ae350_64.dts | 17 +++++++++++------ 2 files changed, 22 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts index cb6ee13f16..97b7cee983 100644 --- a/arch/riscv/dts/ae350_32.dts +++ b/arch/riscv/dts/ae350_32.dts @@ -62,13 +62,18 @@ compatible = "riscv,cpu-intc"; }; }; + }; - L2: l2-cache@e0500000 { - compatible = "cache"; - cache-level = <2>; - cache-size = <0x40000>; - reg = <0x0 0xe0500000 0x0 0x40000>; - }; + L2: l2-cache@e0500000 { + compatible = "v5l2cache"; + cache-level = <2>; + cache-size = <0x40000>; + reg = <0xe0500000 0x40000>; + andes,inst-prefetch = <3>; + andes,data-prefetch = <3>; + /* The value format is */ + andes,tag-ram-ctl = <0 0>; + andes,data-ram-ctl = <0 0>; }; memory@0 { diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts index 705491a8e4..d8f00f8d3a 100644 --- a/arch/riscv/dts/ae350_64.dts +++ b/arch/riscv/dts/ae350_64.dts @@ -62,13 +62,18 @@ compatible = "riscv,cpu-intc"; }; }; + }; - L2: l2-cache@e0500000 { - compatible = "cache"; - cache-level = <2>; - cache-size = <0x40000>; - reg = <0x0 0xe0500000 0x0 0x40000>; - }; + L2: l2-cache@e0500000 { + compatible = "v5l2cache"; + cache-level = <2>; + cache-size = <0x40000>; + reg = <0x0 0xe0500000 0x0 0x40000>; + andes,inst-prefetch = <3>; + andes,data-prefetch = <3>; + /* The value format is */ + andes,tag-ram-ctl = <0 0>; + andes,data-ram-ctl = <0 0>; }; memory@0 { -- cgit From 61ce84b2cf1a6672c8e402ce8174554b25629692 Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Wed, 28 Aug 2019 18:46:11 +0800 Subject: riscv: cache: use CCTL to flush d-cache Use CCTL command to do d-cache write back and invalidate instead of fence. Signed-off-by: Rick Chen Cc: KC Lin Reviewed-by: Bin Meng --- arch/riscv/cpu/ax25/cache.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index 8f5455e519..41de30cc02 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/ax25/cache.c @@ -8,17 +8,21 @@ #include #include #include +#include + +#ifdef CONFIG_RISCV_NDS_CACHE +/* mcctlcommand */ +#define CCTL_REG_MCCTLCOMMAND_NUM 0x7cc + +/* D-cache operation */ +#define CCTL_L1D_WBINVAL_ALL 6 +#endif void flush_dcache_all(void) { - /* - * Andes' AX25 does not have a coherence agent. U-Boot must use data - * cache flush and invalidate functions to keep data in the system - * coherent. - * The implementation of the fence instruction in the AX25 flushes the - * data cache and is used for this purpose. - */ - asm volatile ("fence" ::: "memory"); +#ifdef CONFIG_RISCV_NDS_CACHE + csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL); +#endif } void flush_dcache_range(unsigned long start, unsigned long end) @@ -84,8 +88,8 @@ void dcache_disable(void) #ifdef CONFIG_RISCV_NDS_CACHE struct udevice *dev = NULL; + csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL); asm volatile ( - "fence\n\t" "csrr t1, mcache_ctl\n\t" "andi t0, t1, ~0x2\n\t" "csrw mcache_ctl, t0\n\t" -- cgit