From a8483505e88e9e90bf4e166093dca5f99acbe2b2 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 22 Oct 2018 14:21:17 +0200 Subject: arm: mvebu: Move PCI(e) MBUS window to end of RAM With patch 49b23e035d96 (pci: mvebu: Increase size of PCIe default mapping) the mapping size for each PCI(e) controller was increased from 32MiB to 128MiB. This leads to problems on boards with multiple PCIe slots / ports which are unable to map all PCIe ports, e.g. the Armada-XP theadorable: DRAM: 2 GiB (667 MHz, 64-bit, ECC not enabled) SF: Detected m25p128 with page size 256 Bytes, erase size 256 KiB, total 16 MiB Cannot add window '4:f8', conflicts with another window PCIe unable to add mbus window for mem at f0000000+08000000 Model: Marvell Armada XP theadorable This patch moves the base address for the PCI(e) memory spaces from 0xe8000000 to the end of SDRAM (clipped to a max of 0xc0000000 right now). This gives move room and flexibility for PCI(e) mappings. Signed-off-by: Stefan Roese Cc: VlaoMao Tested-by: VlaoMao --- arch/arm/mach-mvebu/dram.c | 10 ++++++---- arch/arm/mach-mvebu/include/mach/cpu.h | 4 +++- 2 files changed, 9 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mvebu/dram.c b/arch/arm/mach-mvebu/dram.c index 68383d06a2..fa8c799a46 100644 --- a/arch/arm/mach-mvebu/dram.c +++ b/arch/arm/mach-mvebu/dram.c @@ -33,7 +33,9 @@ struct sdram_addr_dec { #define REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2) #define REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24) -#define SDRAM_SIZE_MAX 0xc0000000 +#ifndef MVEBU_SDRAM_SIZE_MAX +#define MVEBU_SDRAM_SIZE_MAX 0xc0000000 +#endif #define SCRUB_MAGIC 0xbeefdead @@ -275,8 +277,8 @@ int dram_init(void) * address space left for the internal registers etc. */ size += mvebu_sdram_bs(i); - if (size > SDRAM_SIZE_MAX) - size = SDRAM_SIZE_MAX; + if (size > MVEBU_SDRAM_SIZE_MAX) + size = MVEBU_SDRAM_SIZE_MAX; } for (; i < CONFIG_NR_DRAM_BANKS; i++) { @@ -312,7 +314,7 @@ int dram_init_banksize(void) /* Clip the banksize to 1GiB if it exceeds the max size */ size += gd->bd->bi_dram[i].size; - if (size > SDRAM_SIZE_MAX) + if (size > MVEBU_SDRAM_SIZE_MAX) mvebu_sdram_bs_set(i, 0x40000000); } diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index d1042100a8..85d7dd1610 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -68,10 +68,12 @@ enum { MVEBU_SOC_UNKNOWN, }; +#define MVEBU_SDRAM_SIZE_MAX 0xc0000000 + /* * Default Device Address MAP BAR values */ -#define MBUS_PCI_MEM_BASE 0xE8000000 +#define MBUS_PCI_MEM_BASE MVEBU_SDRAM_SIZE_MAX #define MBUS_PCI_MEM_SIZE (128 << 20) #define MBUS_PCI_IO_BASE 0xF1100000 #define MBUS_PCI_IO_SIZE (64 << 10) -- cgit From 6843db99224e1e94ef7ef4c1d7bce5615cd3589d Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 23 Oct 2018 12:25:15 +0200 Subject: arm: mvebu: armada-xp-theadorable.dts: Add "spi-flash" compatible property Add the "spi-flash" compatible string so that the generic sf_probe driver can probe the SPI flash on the theadorable Armada-XP board. Signed-off-by: Stefan Roese --- arch/arm/dts/armada-xp-theadorable.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/dts/armada-xp-theadorable.dts b/arch/arm/dts/armada-xp-theadorable.dts index 7087ccfc2f..065e443417 100644 --- a/arch/arm/dts/armada-xp-theadorable.dts +++ b/arch/arm/dts/armada-xp-theadorable.dts @@ -134,7 +134,7 @@ u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; - compatible = "n25q128a13", "jedec,spi-nor"; + compatible = "n25q128a13", "jedec,spi-nor", "spi-flash"; reg = <0>; /* Chip select 0 */ spi-max-frequency = <27777777>; }; -- cgit From ae4c38a5384033c7f5584e33cce1adc511fff333 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 23 Oct 2018 12:25:16 +0200 Subject: arm: mvebu: armada-xp-theadorable.dts: Change CS# for 2nd FPGA The new board version has the 2nd FPGA connected via CS# 0 instead of 2 on SPI bus 1. Change this setup in the DT accordingly. Please note that this change does still work on the old board version because the CS signal is not used on this board. Signed-off-by: Stefan Roese --- arch/arm/dts/armada-xp-theadorable.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/armada-xp-theadorable.dts b/arch/arm/dts/armada-xp-theadorable.dts index 065e443417..965c38426c 100644 --- a/arch/arm/dts/armada-xp-theadorable.dts +++ b/arch/arm/dts/armada-xp-theadorable.dts @@ -151,11 +151,11 @@ spi1: spi@10680 { status = "okay"; - fpga@2 { + fpga@0 { #address-cells = <1>; #size-cells = <1>; compatible = "spi-generic-device"; - reg = <2>; /* Chip select 2 */ + reg = <0>; /* Chip select 0 */ spi-max-frequency = <27777777>; }; }; -- cgit