From 5be3b44cd4ce88adf5f43f38b24c6019945756ec Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Thu, 28 May 2015 14:53:59 +0530 Subject: armv8/ls2085a: call ft_pcie_setup() to change dts status call ft_pci_setup() to disable PCIe dts node if corresponding PCIe controller is disabled according to RCW Signed-off-by: Minghuan Lian Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/fdt.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c index d37002333c..b9fd559356 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c @@ -69,6 +69,10 @@ void ft_cpu_setup(void *blob, bd_t *bd) "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif + #if defined(CONFIG_FSL_ESDHC) fdt_fixup_esdhc(blob, bd); #endif -- cgit From d4c711f0ad20f30ee299f3d100366e9029d17c24 Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 28 May 2015 14:54:05 +0530 Subject: armv8/fsl-lsch3: Fix DDR speed message DDR speed should be in MT/s, not MHz. Signed-off-by: York Sun Signed-off-by: Prabhakar Kushwaha --- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 67145778b9..19c3995fdf 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -394,8 +394,8 @@ int print_cpuinfo(void) } printf("\n Bus: %-4s MHz ", strmhz(buf, sysinfo.freq_systembus)); - printf("DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus)); - printf(" DP-DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus2)); + printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus)); + printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2)); puts("\n"); /* Display the RCW, so that no one gets confused as to what RCW -- cgit From 226296656c6efe4eb2b26dbbebc417455bdfd99d Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Thu, 28 May 2015 14:54:06 +0530 Subject: armv8/fsl-ch3: Add support to print SoC personality This patch adds support to print out the SoC personality. Freescale LS20xx SoCs (compliant to Chassis-3 specifications) can have 6 personalities: LS2045AE, LS2045A, LS2080AE, LS2080A, LS2085AE and LS2085A Signed-off-by: Bhupesh Sharma Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 37 +++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-lsch3/soc.h | 20 +++++++++++++++++ 2 files changed, 57 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 19c3995fdf..52bc73177f 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -22,6 +23,35 @@ DECLARE_GLOBAL_DATA_PTR; +static struct cpu_type cpu_type_list[] = { +#ifdef CONFIG_LS2085A + CPU_TYPE_ENTRY(LS2085, LS2085, 8), + CPU_TYPE_ENTRY(LS2080, LS2080, 8), + CPU_TYPE_ENTRY(LS2045, LS2045, 4), +#endif +}; + +void cpu_name(char *name) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int i, svr, ver; + + svr = in_le32(&gur->svr); + ver = SVR_SOC_VER(svr); + + for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) + if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) { + strcpy(name, cpu_type_list[i].name); + + if (IS_E_PROCESSOR(svr)) + strcat(name, "E"); + break; + } + + if (i == ARRAY_SIZE(cpu_type_list)) + strcpy(name, "unknown"); +} + #ifndef CONFIG_SYS_DCACHE_OFF /* * To start MMU before DDR is available, we create MMU table in SRAM. @@ -380,6 +410,13 @@ int print_cpuinfo(void) unsigned int i, core; u32 type; + puts("SoC: "); + + cpu_name(buf); + printf(" %s (0x%x)\n", buf, in_le32(&gur->svr)); + + memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); + get_sys_info(&sysinfo); puts("Clock Configuration:"); for_each_cpu(i, core, cpu_numcores(), cpu_mask()) { diff --git a/arch/arm/include/asm/arch-fsl-lsch3/soc.h b/arch/arm/include/asm/arch-fsl-lsch3/soc.h index 16b723d600..9a29272072 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/soc.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/soc.h @@ -4,5 +4,25 @@ * SPDX-License-Identifier: GPL-2.0+ */ +struct cpu_type { + char name[15]; + u32 soc_ver; + u32 num_cores; +}; + +#define CPU_TYPE_ENTRY(n, v, nc) \ + { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} + +#define SVR_WO_E 0xFFFFFE +#define SVR_LS2045 0x870120 +#define SVR_LS2080 0x870110 +#define SVR_LS2085 0x870100 + +#define SVR_MAJ(svr) (((svr) >> 4) & 0xf) +#define SVR_MIN(svr) (((svr) >> 0) & 0xf) +#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) +#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) + void fsl_lsch3_early_init_f(void); +void cpu_name(char *name); -- cgit From 092da485c7e685745b6e6f9ab5540fb002046201 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Thu, 28 May 2015 14:54:11 +0530 Subject: armv8/ls2085a: Update SoC README for DDR layout Update SoC README to provide details of - Memory regions - Memory used by MC and Debug server Signed-off-by: Bhupesh Sharma Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/README | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README index 37f07fbb76..3c15479315 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/README +++ b/arch/arm/cpu/armv8/fsl-lsch3/README @@ -9,6 +9,31 @@ Freescale LayerScape with Chassis Generation 3 This architecture supports Freescale ARMv8 SoCs with Chassis generation 3, for example LS2085A. +DDR Layout +============ +Entire DDR region splits into two regions. + - Region 1 is at address 0x8000_0000 to 0xffff_ffff. + - Region 2 is at 0x80_8000_0000 to the top of total memory, + for example 16GB, 0x83_ffff_ffff. + +All DDR memory is marked as cache-enabled. + +When MC and Debug server is enabled, they carve 512MB away from the high +end of DDR. For example, if the total DDR is 16GB, it shrinks to 15.5GB +with MC and Debug server enabled. Linux only sees 15.5GB. + +The reserved 512MB layout looks like + + +---------------+ <-- top/end of memory + | 256MB | debug server + +---------------+ + | 256MB | MC + +---------------+ + | ... | + +MC requires the memory to be aligned with 512MB, so even debug server is +not enabled, 512MB is reserved, not 256MB. + Flash Layout ============ -- cgit From f299b5b0d244b7c4ef4820acb83fc562ff099413 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Thu, 28 May 2015 14:54:13 +0530 Subject: arm/errata: Update required bits for A57 cores erratas This patch updates the setting of required bits for A57 cores erratas - 828024 and 826974 Signed-off-by: Bhupesh Sharma Signed-off-by: Dai Haruki Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- arch/arm/cpu/armv8/start.S | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index e5f2766a4a..e70bed462a 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -115,18 +115,18 @@ apply_a57_core_errata: #ifdef CONFIG_ARM_ERRATA_828024 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ /* Disable non-allocate hint of w-b-n-a memory type */ - mov x0, #0x1 << 49 + orr x0, x0, #1 << 49 /* Disable write streaming no L1-allocate threshold */ - mov x0, #0x3 << 25 + orr x0, x0, #3 << 25 /* Disable write streaming no-allocate threshold */ - mov x0, #0x3 << 27 + orr x0, x0, #3 << 27 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ #endif #ifdef CONFIG_ARM_ERRATA_826974 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ /* Disable speculative load execution ahead of a DMB */ - mov x0, #0x1 << 59 + orr x0, x0, #1 << 59 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ #endif -- cgit From 39da644ea86beb8786c09bd536a184a8642c9e10 Mon Sep 17 00:00:00 2001 From: Stuart Yoder Date: Thu, 2 Jul 2015 11:29:02 +0530 Subject: armv8/fsl-lsch3: partition stream IDs Stream IDs on ls2085a devices are not hardwired and are programmed by sw. There are a limited number of stream IDs available, and the partitioning of them is scenario dependent. This header defines the partitioning between legacy, PCI, and DPAA2 devices. Signed-off-by: Stuart Yoder Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- .../include/asm/arch-fsl-lsch3/ls2085a_stream_id.h | 64 ++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h (limited to 'arch') diff --git a/arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h b/arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h new file mode 100644 index 0000000000..5c945309a9 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h @@ -0,0 +1,64 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ +#ifndef __FSL_STREAM_ID_H +#define __FSL_STREAM_ID_H + +/* Stream IDs on ls2085a devices are not hardwired and are + * programmed by sw. There are a limited number of stream IDs + * available, and the partitioning of them is scenario dependent. + * This header defines the partitioning between legacy, PCI, + * and DPAA2 devices. + * + * This partitiong can be customized in this file depending + * on the specific hardware config-- e.g. perhaps not all + * PEX controllers are in use. + * + * On LS2085 stream IDs are programmed in AMQ registers (32-bits) for + * each of the different bus masters. The relationship between + * the AMQ registers and stream IDs is defined in the table below: + * AMQ bit streamID bit + * --------------------------- + * PL[18] 9 + * BMT[17] 8 + * VA[16] 7 + * [15] - + * ICID[14:7] - + * ICID[6:0] 6-0 + * ---------------------------- + */ + +#define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */ +#define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */ + +#define FSL_INVALID_STREAM_ID 0 + +#define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK) + +/* legacy devices */ +#define FSL_USB1_STREAM_ID 1 +#define FSL_USB2_STREAM_ID 2 +#define FSL_SDMMC_STREAM_ID 3 +#define FSL_SATA1_STREAM_ID 4 +#define FSL_SATA2_STREAM_ID 5 +#define FSL_DMA_STREAM_ID 6 + +/* PCI - programmed in PEXn_LUT by OS */ +/* 4 IDs per controller */ +#define FSL_PEX1_STREAM_ID_START 7 +#define FSL_PEX1_STREAM_ID_END 10 +#define FSL_PEX2_STREAM_ID_START 11 +#define FSL_PEX2_STREAM_ID_END 14 +#define FSL_PEX3_STREAM_ID_START 15 +#define FSL_PEX3_STREAM_ID_END 18 +#define FSL_PEX4_STREAM_ID_START 19 +#define FSL_PEX4_STREAM_ID_END 22 + +/* DPAA2 - set in MC DPC and alloced by MC */ +#define FSL_DPAA2_STREAM_ID_START 23 +#define FSL_DPAA2_STREAM_ID_END 63 + +#endif -- cgit From 70e52d211533c45f0d26c4d87cbeee31560fbe04 Mon Sep 17 00:00:00 2001 From: Stuart Yoder Date: Thu, 2 Jul 2015 11:29:04 +0530 Subject: armv8/fsl-lsch3: device tree fixups for PCI stream IDs This patch adds the infrastructure to update device tree nodes to convey SMMU stream IDs in the device tree. Fixups are implemented for PCI controllers initially. Signed-off-by: Stuart Yoder Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/fdt.c | 110 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-lsch3/fdt.h | 10 +++ 2 files changed, 120 insertions(+) create mode 100644 arch/arm/include/asm/arch-fsl-lsch3/fdt.h (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c index b9fd559356..567c41927a 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c @@ -7,6 +7,7 @@ #include #include #include +#include #ifdef CONFIG_FSL_ESDHC #include #endif @@ -58,6 +59,113 @@ void ft_fixup_cpu(void *blob) } #endif +/* + * the burden is on the the caller to not request a count + * exceeding the bounds of the stream_ids[] array + */ +void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt) +{ + int i; + + if (count > max_cnt) { + printf("\n%s: ERROR: max per-device stream ID count exceed\n", + __func__); + return; + } + + for (i = 0; i < count; i++) + stream_ids[i] = start_id++; +} + +/* + * This function updates the mmu-masters property on the SMMU + * node as per the SMMU binding-- phandle and list of stream IDs + * for each MMU master. + */ +void append_mmu_masters(void *blob, const char *smmu_path, + const char *master_name, u32 *stream_ids, int count) +{ + u32 phandle; + int smmu_nodeoffset; + int master_nodeoffset; + int i; + + /* get phandle of mmu master device */ + master_nodeoffset = fdt_path_offset(blob, master_name); + if (master_nodeoffset < 0) { + printf("\n%s: ERROR: master not found\n", __func__); + return; + } + phandle = fdt_get_phandle(blob, master_nodeoffset); + if (!phandle) { /* if master has no phandle, create one */ + phandle = fdt_create_phandle(blob, master_nodeoffset); + if (!phandle) { + printf("\n%s: ERROR: unable to create phandle\n", + __func__); + return; + } + } + + /* append it to mmu-masters */ + smmu_nodeoffset = fdt_path_offset(blob, smmu_path); + if (fdt_appendprop_u32(blob, smmu_nodeoffset, "mmu-masters", + phandle) < 0) { + printf("\n%s: ERROR: unable to update SMMU node\n", __func__); + return; + } + + /* for each stream ID, append to mmu-masters */ + for (i = 0; i < count; i++) { + fdt_appendprop_u32(blob, smmu_nodeoffset, "mmu-masters", + stream_ids[i]); + } + + /* fix up #stream-id-cells with stream ID count */ + if (fdt_setprop_u32(blob, master_nodeoffset, "#stream-id-cells", + count) < 0) + printf("\n%s: ERROR: unable to update #stream-id-cells\n", + __func__); +} + + +/* + * The info below summarizes how streamID partitioning works + * for ls2085a and how it is conveyed to the OS via the device tree. + * + * -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA) + * -all legacy devices get a unique ICID assigned and programmed in + * their AMQR registers by u-boot + * -u-boot updates the hardware device tree with streamID properties + * for each platform/legacy device (smmu-masters property) + * + * -PCIe + * -for each PCI controller that is active (as per RCW settings), + * u-boot will allocate a range of ICID and convey that to Linux via + * the device tree (smmu-masters property) + * + * -DPAA2 + * -u-boot will allocate a range of ICIDs to be used by the Management + * Complex for containers and will set these values in the MC DPC image. + * -the MC is responsible for allocating and setting up ICIDs + * for all DPAA2 devices. + * + */ +static void fdt_fixup_smmu(void *blob) +{ + int nodeoffset; + + nodeoffset = fdt_path_offset(blob, "/iommu@5000000"); + if (nodeoffset < 0) { + printf("\n%s: WARNING: no SMMU node found\n", __func__); + return; + } + + /* fixup for all PCI controllers */ +#ifdef CONFIG_PCI + fdt_fixup_smmu_pcie(blob); +#endif +} + void ft_cpu_setup(void *blob, bd_t *bd) { #ifdef CONFIG_MP @@ -76,4 +184,6 @@ void ft_cpu_setup(void *blob, bd_t *bd) #if defined(CONFIG_FSL_ESDHC) fdt_fixup_esdhc(blob, bd); #endif + + fdt_fixup_smmu(blob); } diff --git a/arch/arm/include/asm/arch-fsl-lsch3/fdt.h b/arch/arm/include/asm/arch-fsl-lsch3/fdt.h new file mode 100644 index 0000000000..21d20fba21 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-lsch3/fdt.h @@ -0,0 +1,10 @@ +/* + * Copyright 2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt); +void append_mmu_masters(void *blob, const char *smmu_path, + const char *master_name, u32 *stream_ids, int count); +void fdt_fixup_smmu_pcie(void *blob); -- cgit From 49a5e42a780dadf69fcac177143b0c8619ec467b Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Mon, 11 May 2015 15:39:47 +0800 Subject: arm: ls1021a: Remove the inappropriate use of the function 'sprintf' As the function 'sprintf' does not check buffer boundaries but outputs to the buffer 'enet' of fixed size (16), this patch removes the function 'sprintf', and uses 'strcpy' instead. It will assign the character arrays 'enet' and 'phy' the corresponding character strings. Signed-off-by: Alison Wang Reviewed-by: Joe Hershberger Reviewed-by: York Sun --- arch/arm/cpu/armv7/ls102xa/fdt.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index 71a175392f..e01d911780 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -29,29 +29,30 @@ void ft_fixup_enet_phy_connect_type(void *fdt) char phy[16]; int phy_node; int i = 0; - int enet_id = 0; uint32_t ph; while ((dev = eth_get_dev_by_index(i++)) != NULL) { - if (strstr(dev->name, "eTSEC1")) - enet_id = 0; - else if (strstr(dev->name, "eTSEC2")) - enet_id = 1; - else if (strstr(dev->name, "eTSEC3")) - enet_id = 2; - else + if (strstr(dev->name, "eTSEC1")) { + strcpy(enet, "ethernet0"); + strcpy(phy, "enet0_rgmii_phy"); + } else if (strstr(dev->name, "eTSEC2")) { + strcpy(enet, "ethernet1"); + strcpy(phy, "enet1_rgmii_phy"); + } else if (strstr(dev->name, "eTSEC3")) { + strcpy(enet, "ethernet2"); + strcpy(phy, "enet2_rgmii_phy"); + } else { continue; + } priv = dev->priv; if (priv->flags & TSEC_SGMII) continue; - sprintf(enet, "ethernet%d", enet_id); enet_path = fdt_get_alias(fdt, enet); if (!enet_path) continue; - sprintf(phy, "enet%d_rgmii_phy", enet_id); phy_path = fdt_get_alias(fdt, phy); if (!phy_path) continue; -- cgit From 972af2ab515fe0d0a39271966c9c6df0d9349f37 Mon Sep 17 00:00:00 2001 From: Wang Dongsheng Date: Thu, 4 Jun 2015 12:01:08 +0800 Subject: ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.S timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted completely into a reusable armv7 generic timer. LS1021A will use it as well. Signed-off-by: Wang Dongsheng Reviewed-by: Hans de Goede Reviewed-by: York Sun --- arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 22 ++---------- arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 22 ++---------- arch/arm/include/asm/arch-armv7/generictimer.h | 50 ++++++++++++++++++++++++++ 3 files changed, 54 insertions(+), 40 deletions(-) create mode 100644 arch/arm/include/asm/arch-armv7/generictimer.h (limited to 'arch') diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S index d4cb51e044..4ff46e4fc0 100644 --- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S +++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S @@ -18,6 +18,8 @@ */ #include + +#include #include #include #include @@ -43,26 +45,6 @@ #define GICD_BASE 0x1c81000 #define GICC_BASE 0x1c82000 -.macro timer_wait reg, ticks - @ Program CNTP_TVAL - movw \reg, #(\ticks & 0xffff) - movt \reg, #(\ticks >> 16) - mcr p15, 0, \reg, c14, c2, 0 - isb - @ Enable physical timer, mask interrupt - mov \reg, #3 - mcr p15, 0, \reg, c14, c2, 1 - @ Poll physical timer until ISTATUS is on -1: isb - mrc p15, 0, \reg, c14, c2, 1 - ands \reg, \reg, #4 - bne 1b - @ Disable timer - mov \reg, #0 - mcr p15, 0, \reg, c14, c2, 1 - isb -.endm - .globl psci_fiq_enter psci_fiq_enter: push {r0-r12} diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S index bbfeec8ba8..e15d587f29 100644 --- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S +++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S @@ -18,6 +18,8 @@ */ #include + +#include #include #include #include @@ -43,26 +45,6 @@ #define GICD_BASE 0x1c81000 #define GICC_BASE 0x1c82000 -.macro timer_wait reg, ticks - @ Program CNTP_TVAL - movw \reg, #(\ticks & 0xffff) - movt \reg, #(\ticks >> 16) - mcr p15, 0, \reg, c14, c2, 0 - isb - @ Enable physical timer, mask interrupt - mov \reg, #3 - mcr p15, 0, \reg, c14, c2, 1 - @ Poll physical timer until ISTATUS is on -1: isb - mrc p15, 0, \reg, c14, c2, 1 - ands \reg, \reg, #4 - bne 1b - @ Disable timer - mov \reg, #0 - mcr p15, 0, \reg, c14, c2, 1 - isb -.endm - .globl psci_fiq_enter psci_fiq_enter: push {r0-r12} diff --git a/arch/arm/include/asm/arch-armv7/generictimer.h b/arch/arm/include/asm/arch-armv7/generictimer.h new file mode 100644 index 0000000000..f402686092 --- /dev/null +++ b/arch/arm/include/asm/arch-armv7/generictimer.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2013 - ARM Ltd + * Author: Marc Zyngier + * + * Based on code by Carl van Schaik . + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef _GENERICTIMER_H_ +#define _GENERICTIMER_H_ + +#ifdef __ASSEMBLY__ + +/* + * This macro provide a physical timer that can be used for delay in the code. + * The macro is moved from sunxi/psci_sun7i.S + * + * reg: is used in this macro. + * ticks: The freq is based on generic timer. + */ +.macro timer_wait reg, ticks + movw \reg, #(\ticks & 0xffff) + movt \reg, #(\ticks >> 16) + mcr p15, 0, \reg, c14, c2, 0 + isb + mov \reg, #3 + mcr p15, 0, \reg, c14, c2, 1 +1 : isb + mrc p15, 0, \reg, c14, c2, 1 + ands \reg, \reg, #4 + bne 1b + mov \reg, #0 + mcr p15, 0, \reg, c14, c2, 1 + isb +.endm + +#endif /* __ASSEMBLY__ */ + +#endif /* _GENERICTIMER_H_ */ -- cgit From 340848b1853fde95991cb76fee78a69eafd83335 Mon Sep 17 00:00:00 2001 From: Wang Dongsheng Date: Thu, 4 Jun 2015 12:01:09 +0800 Subject: arm/ls102xa: Add PSCI support for ls102xa Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform. Tested on LS1021AQDS, LS1021ATWR. Test CPU hotplug times: 60K Test kernel boot times: 1.2K Signed-off-by: Wang Dongsheng Acked-by: Alison Wang Reviewed-by: York Sun --- arch/arm/cpu/armv7/ls102xa/Makefile | 4 ++ arch/arm/cpu/armv7/ls102xa/psci.S | 126 ++++++++++++++++++++++++++++++++++++ 2 files changed, 130 insertions(+) create mode 100644 arch/arm/cpu/armv7/ls102xa/psci.S (limited to 'arch') diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile index 2e6a20757f..2d55782749 100644 --- a/arch/arm/cpu/armv7/ls102xa/Makefile +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -12,3 +12,7 @@ obj-y += fsl_epu.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o obj-$(CONFIG_SPL) += spl.o + +ifdef CONFIG_ARMV7_PSCI +obj-y += psci.o +endif diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S new file mode 100644 index 0000000000..cf5cd48bcb --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/psci.S @@ -0,0 +1,126 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * Author: Wang Dongsheng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include +#include +#include + +#define SCFG_CORE0_SFT_RST 0x130 +#define SCFG_CORESRENCR 0x204 + +#define DCFG_CCSR_BRR 0x0E4 +#define DCFG_CCSR_SCRATCHRW1 0x200 + + .pushsection ._secure.text, "ax" + + .arch_extension sec + +#define ONE_MS (GENERIC_TIMER_CLK / 1000) +#define RESET_WAIT (30 * ONE_MS) + + @ r1 = target CPU + @ r2 = target PC +.globl psci_cpu_on +psci_cpu_on: + push {lr} + + @ Clear and Get the correct CPU number + @ r1 = 0xf01 + and r1, r1, #0xff + + mov r0, r1 + bl psci_get_cpu_stack_top + str r2, [r0] + dsb + + @ Get DCFG base address + movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff) + movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16) + + @ Detect target CPU state + ldr r2, [r4, #DCFG_CCSR_BRR] + rev r2, r2 + lsr r2, r2, r1 + ands r2, r2, #1 + beq holdoff_release + + @ Reset target CPU + @ Get SCFG base address + movw r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff) + movt r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16) + + @ Enable CORE Soft Reset + movw r5, #0 + movt r5, #(1 << 15) + rev r5, r5 + str r5, [r0, #SCFG_CORESRENCR] + + @ Get CPUx offset register + mov r6, #0x4 + mul r6, r6, r1 + add r2, r0, r6 + + @ Do reset on target CPU + movw r5, #0 + movt r5, #(1 << 15) + rev r5, r5 + str r5, [r2, #SCFG_CORE0_SFT_RST] + + @ Wait target CPU up + timer_wait r2, RESET_WAIT + + @ Disable CORE soft reset + mov r5, #0 + str r5, [r0, #SCFG_CORESRENCR] + +holdoff_release: + @ Release on target CPU + ldr r2, [r4, #DCFG_CCSR_BRR] + mov r6, #1 + lsl r6, r6, r1 @ 32 bytes per CPU + + rev r6, r6 + orr r2, r2, r6 + str r2, [r4, #DCFG_CCSR_BRR] + + @ Set secondary boot entry + ldr r6, =psci_cpu_entry + rev r6, r6 + str r6, [r4, #DCFG_CCSR_SCRATCHRW1] + + isb + dsb + + @ Return + mov r0, #ARM_PSCI_RET_SUCCESS + + pop {lr} + bx lr + +.globl psci_cpu_off +psci_cpu_off: + bl psci_cpu_off_common + +1: wfi + b 1b + +.globl psci_arch_init +psci_arch_init: + mov r6, lr + + bl psci_get_cpu_id + bl psci_get_cpu_stack_top + mov sp, r0 + + bx r6 + + .globl psci_text_end +psci_text_end: + .popsection -- cgit From 88c857df8cf4956195b10afbbe08cc3912d45429 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 9 Jun 2015 16:07:49 +0800 Subject: arm/ls102xa: Add little-endian mode support for audio IPs As SCFG_ENDIANCR register is added to choose little-endian or big-endian for audio IPs on Rev2.0 silion, little-endian mode is selected. Signed-off-by: Alison Wang Reviewed-by: York Sun --- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index ee547fbcee..6a330cc2af 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -149,6 +149,7 @@ struct ccsr_gur { #define SCFG_ETSECCMCR_GE1_CLK125 0x08000000 #define SCFG_PIXCLKCR_PXCKEN 0x80000000 #define SCFG_QSPI_CLKSEL 0xc0100000 +#define SCFG_ENDIANCR_LE 0x80000000 /* Supplemental Configuration Unit */ struct ccsr_scfg { @@ -207,7 +208,7 @@ struct ccsr_scfg { u32 qos2; u32 qos3; u32 cci_cfg; - u32 resv8[1]; + u32 endiancr; u32 etsecdmamcr; u32 usb3prm3cr; u32 resv9[1]; -- cgit From d941f71084aab787228a2a8bad614f8770e6f384 Mon Sep 17 00:00:00 2001 From: Haikun Wang Date: Fri, 26 Jun 2015 19:48:36 +0800 Subject: arm/dts/ls2085a: Bring in ls2085a dts files from linux kernel Bring in required device tree files for ls2085a from Linux. These are initially unchanged and have a number of pieces not needed by U-Boot. Signed-off-by: Haikun Wang Reviewed-by: York Sun --- arch/arm/dts/fsl-ls2085a.dtsi | 120 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 arch/arm/dts/fsl-ls2085a.dtsi (limited to 'arch') diff --git a/arch/arm/dts/fsl-ls2085a.dtsi b/arch/arm/dts/fsl-ls2085a.dtsi new file mode 100644 index 0000000000..f0679a8561 --- /dev/null +++ b/arch/arm/dts/fsl-ls2085a.dtsi @@ -0,0 +1,120 @@ +/* + * Freescale ls2085a SOC common device tree source + * + * Copyright 2013-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/ { + compatible = "fsl,ls2085a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + /* + * We expect the enable-method for cpu's to be "psci", but this + * is dependent on the SoC FW, which will fill this in. + * + * Currently supported enable-method is psci v0.2 + */ + + /* We have 4 clusters having 2 Cortex-A57 cores each */ + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x1>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x100>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x101>; + }; + + cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x200>; + }; + + cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x201>; + }; + + cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x300>; + }; + + cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a57"; + reg = <0x0 0x301>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x80000000>; + /* DRAM space - 1, size : 2 GB DRAM */ + }; + + gic: interrupt-controller@6000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ + <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <1 9 0x4>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ + <1 14 0x8>, /* Physical Non-Secure PPI, active-low */ + <1 11 0x8>, /* Virtual PPI, active-low */ + <1 10 0x8>; /* Hypervisor PPI, active-low */ + }; + + serial0: serial@21c0500 { + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21c0500 0x0 0x100>; + clock-frequency = <0>; /* Updated by bootloader */ + interrupts = <0 32 0x1>; /* edge triggered */ + }; + + serial1: serial@21c0600 { + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21c0600 0x0 0x100>; + clock-frequency = <0>; /* Updated by bootloader */ + interrupts = <0 32 0x1>; /* edge triggered */ + }; + + fsl_mc: fsl-mc@80c000000 { + compatible = "fsl,qoriq-mc"; + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ + <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ + }; +}; -- cgit From fe69a0e86bc714ce8d7d8251ec31b77b89c96db5 Mon Sep 17 00:00:00 2001 From: Haikun Wang Date: Fri, 26 Jun 2015 19:48:45 +0800 Subject: arm/dts/ls2085a: Add DSPI dts node Add DSPI controller dts node in fsl-ls2085a.dtsi Signed-off-by: Haikun Wang Reviewed-by: York Sun --- arch/arm/dts/fsl-ls2085a.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/arm/dts/fsl-ls2085a.dtsi b/arch/arm/dts/fsl-ls2085a.dtsi index f0679a8561..96404c5d65 100644 --- a/arch/arm/dts/fsl-ls2085a.dtsi +++ b/arch/arm/dts/fsl-ls2085a.dtsi @@ -117,4 +117,13 @@ reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ }; + + dspi: dspi@2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <0 26 0x4>; /* Level high type */ + num-cs = <6>; + }; }; -- cgit From 193e7e5a8e93fa3076a80fa6c7b687401f08108b Mon Sep 17 00:00:00 2001 From: Haikun Wang Date: Fri, 26 Jun 2015 19:48:58 +0800 Subject: arm/dts/ls2085a: Add dts files for LS2085AQDS and LS2085ARDB Add dts source files for LS2085AQDS and LS2085ARDB boards. Signed-off-by: Haikun Wang Reviewed-by: York Sun --- arch/arm/dts/Makefile | 2 ++ arch/arm/dts/fsl-ls2085a-qds.dts | 53 ++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/fsl-ls2085a-rdb.dts | 35 ++++++++++++++++++++++++++ 3 files changed, 90 insertions(+) create mode 100644 arch/arm/dts/fsl-ls2085a-qds.dts create mode 100644 arch/arm/dts/fsl-ls2085a-rdb.dts (limited to 'arch') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 19e1de67a0..8ebd693432 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -57,6 +57,8 @@ dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \ ls1021a-twr.dtb +dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2085a-qds.dtb \ + fsl-ls2085a-rdb.dtb dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ diff --git a/arch/arm/dts/fsl-ls2085a-qds.dts b/arch/arm/dts/fsl-ls2085a-qds.dts new file mode 100644 index 0000000000..4477e54154 --- /dev/null +++ b/arch/arm/dts/fsl-ls2085a-qds.dts @@ -0,0 +1,53 @@ +/* + * Freescale ls2085a QDS board device tree source + * + * Copyright 2013-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "fsl-ls2085a.dtsi" + +/ { + model = "Freescale Layerscape 2085a QDS Board"; + compatible = "fsl,ls2085a-qds", "fsl,ls2085a"; + + aliases { + spi1 = &dspi; + }; +}; + +&dspi { + bus-num = <0>; + status = "okay"; + + dflash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; + dflash1: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <1>; + }; + dflash2: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <2>; + }; +}; diff --git a/arch/arm/dts/fsl-ls2085a-rdb.dts b/arch/arm/dts/fsl-ls2085a-rdb.dts new file mode 100644 index 0000000000..25278dfaf8 --- /dev/null +++ b/arch/arm/dts/fsl-ls2085a-rdb.dts @@ -0,0 +1,35 @@ +/* + * Freescale ls2085a RDB board device tree source + * + * Copyright 2013-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "fsl-ls2085a.dtsi" + +/ { + model = "Freescale Layerscape 2085a RDB Board"; + compatible = "fsl,ls2085a-rdb", "fsl,ls2085a"; + + aliases { + spi1 = &dspi; + }; +}; + +&dspi { + bus-num = <0>; + status = "okay"; + + dflash0: n25q512a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; -- cgit From b0e209dc636d76afa90e330c37d29cea6deeea33 Mon Sep 17 00:00:00 2001 From: Haikun Wang Date: Fri, 26 Jun 2015 19:56:11 +0800 Subject: armv8/ls2085a: Enable DSPI get input clk form 'mxc_get_clock' Signed-off-by: Haikun Wang Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/speed.c | 2 ++ arch/arm/include/asm/arch-fsl-lsch3/clock.h | 1 + 2 files changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c b/arch/arm/cpu/armv8/fsl-lsch3/speed.c index cac4f925a4..d9f137cc2d 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/speed.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/speed.c @@ -180,6 +180,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk) switch (clk) { case MXC_I2C_CLK: return get_bus_freq(0) / 2; + case MXC_DSPI_CLK: + return get_bus_freq(0) / 2; default: printf("Unsupported clock\n"); } diff --git a/arch/arm/include/asm/arch-fsl-lsch3/clock.h b/arch/arm/include/asm/arch-fsl-lsch3/clock.h index 831af0bda3..62bc53c2fe 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/clock.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/clock.h @@ -16,6 +16,7 @@ enum mxc_clock { MXC_UART_CLK, MXC_ESDHC_CLK, MXC_I2C_CLK, + MXC_DSPI_CLK, }; unsigned int mxc_get_clock(enum mxc_clock clk); -- cgit From e71a980a4d4eb01bc3eb7624fc59cd8f999bf4b2 Mon Sep 17 00:00:00 2001 From: Haikun Wang Date: Fri, 26 Jun 2015 19:58:12 +0800 Subject: armv8/ls2085aqds: DSPI pin muxing configure through QIXIS DSPI has pin muxing with SDHC and other IPs, this patch check the value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check the "hwconfig" variable. If those pins are configured to DSPI and "hwconfig" enable DSPI, set the BRDCFG5 of QIXIS FPGA to configure the routing to on-board SPI memory. Otherwise will configure to SDHC. DSPI is enabled in "hwconfig" by appending "dspi", eg. setenv hwconfig "$hwconfig;dspi" Signed-off-by: Haikun Wang Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-lsch3/config.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index ca8d38cf78..8675e91fca 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -137,6 +137,8 @@ #define DCFG_PORSR1 0x000 #define DCFG_PORSR1_RCW_SRC 0xff800000 #define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000 +#define DCFG_RCWSR13 0x130 +#define DCFG_RCWSR13_DSPI (0 << 8) #define DCFG_DCSR_BASE 0X700100000ULL #define DCFG_DCSR_PORCR1 0x000 -- cgit From 21a257b9b3b29ddb1445fdafe12e05727080a198 Mon Sep 17 00:00:00 2001 From: Zhichun Hua Date: Mon, 29 Jun 2015 15:49:37 +0800 Subject: armv8: Fix TCR macros for shareability attribute For ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bit position [13:12] of TCR_ELx register. Signed-off-by: Zhichun Hua Signed-off-by: York Sun --- arch/arm/include/asm/armv8/mmu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 4b9cb52965..04fa0be64c 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -93,8 +93,8 @@ #define TCR_ORGN_WBNWA (3 << 10) #define TCR_ORGN_MASK (3 << 10) #define TCR_SHARED_NON (0 << 12) -#define TCR_SHARED_OUTER (1 << 12) -#define TCR_SHARED_INNER (2 << 12) +#define TCR_SHARED_OUTER (2 << 12) +#define TCR_SHARED_INNER (3 << 12) #define TCR_TG0_4K (0 << 14) #define TCR_TG0_64K (1 << 14) #define TCR_TG0_16K (2 << 14) -- cgit From db14f11dfe348550d8c10c6609277488d9f500d6 Mon Sep 17 00:00:00 2001 From: Zhichun Hua Date: Mon, 29 Jun 2015 15:50:42 +0800 Subject: armv8/fsl-lsch3: Fix TCR_EL3 for the final MMU setup. When final MMU table is setup in DDR, TCR attributes must match those of the memroy for cacheability and shareability. Signed-off-by: Zhichun Hua Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 52bc73177f..d02c0beef9 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -82,6 +82,12 @@ void cpu_name(char *name) TCR_ORGN_NC | \ TCR_IRGN_NC | \ TCR_T0SZ(LSCH3_VA_BITS)) +#define LSCH3_TCR_FINAL (TCR_TG0_4K | \ + TCR_EL2_PS_40BIT | \ + TCR_SHARED_OUTER | \ + TCR_ORGN_WBWA | \ + TCR_IRGN_WBWA | \ + TCR_T0SZ(LSCH3_VA_BITS)) /* * Final MMU @@ -266,21 +272,8 @@ static inline void final_mmu_setup(void) /* point TTBR to the new table */ el = current_el(); - asm volatile("dsb sy"); - if (el == 1) { - asm volatile("msr ttbr0_el1, %0" - : : "r" ((u64)level0_table) : "memory"); - } else if (el == 2) { - asm volatile("msr ttbr0_el2, %0" - : : "r" ((u64)level0_table) : "memory"); - } else if (el == 3) { - asm volatile("msr ttbr0_el3, %0" - : : "r" ((u64)level0_table) : "memory"); - } else { - hang(); - } - asm volatile("isb"); - + set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR_FINAL, + MEMORY_ATTRIBUTES); /* * MMU is already enabled, just need to invalidate TLB to load the * new table. The new table is compatible with the current table, if -- cgit