From b6055945d66d0f4e3b1ecb82af476232067a4ee4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 22 Aug 2020 22:45:25 +0200 Subject: ARM: dts: stm32: Adjust PLL4 settings on AV96 again PLL4Q is supplying both FDCAN and LTDC. In case HDMI is in use, the 50 MHz generated from PLL4Q cannot be divided well enough to produce accurate clock for HDMI pixel clock. Adjust it to generate 74.25 MHz instead. The PLL4P/PLL4R are generating 99 MHz instead of 100 MHz, which is in tolerance for the SDMMC. Signed-off-by: Marek Vasut Cc: Gerald Baeza Cc: Patrick Delaunay Cc: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi index 7529068c51..c73318488d 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi @@ -132,11 +132,11 @@ u-boot,dm-pre-reloc; }; - /* VCO = 600.0 MHz => P = 100, Q = 50, R = 100 */ + /* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */ pll4: st,pll@3 { compatible = "st,stm32mp1-pll"; reg = <3>; - cfg = < 1 49 5 11 5 PQR(1,1,1) >; + cfg = < 3 98 5 7 5 PQR(1,1,1) >; u-boot,dm-pre-reloc; }; }; -- cgit