From 933f84cab9027788c31f4a8772f0c31176dde1aa Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 18 Feb 2019 22:46:25 +0100 Subject: ARM:dts: stm32: sort nodes by alphabetical order in f4 u-boot files Sort nodes alphabetically to be coherent with all others STM32 DT files. Signed-off-by: Patrice Chotard --- arch/arm/dts/stm32f429-disco-u-boot.dtsi | 18 ++++++------- arch/arm/dts/stm32f469-disco-u-boot.dtsi | 46 ++++++++++++++++---------------- 2 files changed, 32 insertions(+), 32 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/stm32f429-disco-u-boot.dtsi b/arch/arm/dts/stm32f429-disco-u-boot.dtsi index 10e09508aa..0cc3100440 100644 --- a/arch/arm/dts/stm32f429-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f429-disco-u-boot.dtsi @@ -70,19 +70,11 @@ u-boot,dm-pre-reloc; }; -&clk_lse { - u-boot,dm-pre-reloc; -}; - &clk_i2s_ckin { u-boot,dm-pre-reloc; }; -&pwrcfg { - u-boot,dm-pre-reloc; -}; - -&rcc { +&clk_lse { u-boot,dm-pre-reloc; }; @@ -203,3 +195,11 @@ }; }; }; + +&pwrcfg { + u-boot,dm-pre-reloc; +}; + +&rcc { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/stm32f469-disco-u-boot.dtsi b/arch/arm/dts/stm32f469-disco-u-boot.dtsi index 774f1b5e65..a980ac46f5 100644 --- a/arch/arm/dts/stm32f469-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f469-disco-u-boot.dtsi @@ -71,23 +71,11 @@ u-boot,dm-pre-reloc; }; -&clk_lse { - u-boot,dm-pre-reloc; -}; - &clk_i2s_ckin { u-boot,dm-pre-reloc; }; -&pwrcfg { - u-boot,dm-pre-reloc; -}; - -&syscfg { - u-boot,dm-pre-reloc; -}; - -&rcc { +&clk_lse { u-boot,dm-pre-reloc; }; @@ -147,16 +135,6 @@ }; &pinctrl { - usart3_pins_a: usart3@0 { - u-boot,dm-pre-reloc; - pins1 { - u-boot,dm-pre-reloc; - }; - pins2 { - u-boot,dm-pre-reloc; - }; - }; - fmc_pins_d32: fmc_d32@0 { u-boot,dm-pre-reloc; pins @@ -226,4 +204,26 @@ u-boot,dm-pre-reloc; }; }; + + usart3_pins_a: usart3@0 { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + }; + }; +}; + +&pwrcfg { + u-boot,dm-pre-reloc; +}; + +&rcc { + u-boot,dm-pre-reloc; +}; + +&syscfg { + u-boot,dm-pre-reloc; }; -- cgit From 71dfd5f3f5267259b1e7b465bc07e49c67acaf45 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 18 Feb 2019 22:54:35 +0100 Subject: ARM: dts: stm32: Sync DT files with v4.20 kernel for stm32f4 Synchronize stm32f7 device tree with kernel v4.20. Signed-off-by: Patrice Chotard --- arch/arm/dts/stm32f4-pinctrl.dtsi | 27 ++++++------ arch/arm/dts/stm32f429-disco.dts | 4 +- arch/arm/dts/stm32f429-pinctrl.dtsi | 3 +- arch/arm/dts/stm32f429.dtsi | 33 +++++++------- arch/arm/dts/stm32f469-disco.dts | 86 ++++++++++++++++++++++++++++++++++++- arch/arm/dts/stm32f469-pinctrl.dtsi | 3 +- arch/arm/dts/stm32f469.dtsi | 19 ++++++++ 7 files changed, 138 insertions(+), 37 deletions(-) create mode 100644 arch/arm/dts/stm32f469.dtsi (limited to 'arch') diff --git a/arch/arm/dts/stm32f4-pinctrl.dtsi b/arch/arm/dts/stm32f4-pinctrl.dtsi index 736bca738d..35202896c0 100644 --- a/arch/arm/dts/stm32f4-pinctrl.dtsi +++ b/arch/arm/dts/stm32f4-pinctrl.dtsi @@ -1,6 +1,5 @@ /* - * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Alexandre Torgue for STMicroelectronics. + * Copyright 2017 - Alexandre Torgue * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -342,12 +341,12 @@ sdio_pins: sdio_pins@0 { pins { - pinmux = , - , - , - , - , - ; + pinmux = , /* SDIO_D0 */ + , /* SDIO_D1 */ + , /* SDIO_D2 */ + , /* SDIO_D3 */ + , /* SDIO_CK */ + ; /* SDIO_CMD */ drive-push-pull; slew-rate = <2>; }; @@ -355,17 +354,17 @@ sdio_pins_od: sdio_pins_od@0 { pins1 { - pinmux = , - , - , - , - ; + pinmux = , /* SDIO_D0 */ + , /* SDIO_D1 */ + , /* SDIO_D2 */ + , /* SDIO_D3 */ + ; /* SDIO_CK */ drive-push-pull; slew-rate = <2>; }; pins2 { - pinmux = ; + pinmux = ; /* SDIO_CMD */ drive-open-drain; slew-rate = <2>; }; diff --git a/arch/arm/dts/stm32f429-disco.dts b/arch/arm/dts/stm32f429-disco.dts index 106db68b5b..d99f47aa72 100644 --- a/arch/arm/dts/stm32f429-disco.dts +++ b/arch/arm/dts/stm32f429-disco.dts @@ -1,6 +1,5 @@ /* - * Copyright (C) 2015, STMicroelectronics - All Rights Reserved - * Author(s): Maxime Coquelin for STMicroelectronics. + * Copyright 2015 - Maxime Coquelin * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -76,6 +75,7 @@ gpio_keys { compatible = "gpio-keys"; + #address-cells = <1>; #size-cells = <0>; autorepeat; button@0 { diff --git a/arch/arm/dts/stm32f429-pinctrl.dtsi b/arch/arm/dts/stm32f429-pinctrl.dtsi index 77246b3d79..3e7a17d911 100644 --- a/arch/arm/dts/stm32f429-pinctrl.dtsi +++ b/arch/arm/dts/stm32f429-pinctrl.dtsi @@ -1,6 +1,5 @@ /* - * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Alexandre Torgue for STMicroelectronics. + * Copyright 2017 - Alexandre Torgue * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual diff --git a/arch/arm/dts/stm32f429.dtsi b/arch/arm/dts/stm32f429.dtsi index 046aeff7cc..c5c029b9e3 100644 --- a/arch/arm/dts/stm32f429.dtsi +++ b/arch/arm/dts/stm32f429.dtsi @@ -1,6 +1,5 @@ /* - * Copyright (C) 2015, STMicroelectronics - All Rights Reserved - * Author(s): Maxime Coquelin for STMicroelectronics. + * Copyright 2015 - Maxime Coquelin * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -259,6 +258,7 @@ }; timers13: timers@40001c00 { + #address-cells = <1>; #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40001C00 0x400>; @@ -273,6 +273,7 @@ }; timers14: timers@40002000 { + #address-cells = <1>; #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40002000 0x400>; @@ -296,7 +297,7 @@ interrupt-parent = <&exti>; interrupts = <17 1>; interrupt-names = "alarm"; - st,syscfg = <&pwrcfg>; + st,syscfg = <&pwrcfg 0x00 0x100>; status = "disabled"; }; @@ -304,6 +305,7 @@ compatible = "st,stm32-iwdg"; reg = <0x40003000 0x400>; clocks = <&clk_lsi>; + clock-names = "lsi"; status = "disabled"; }; @@ -505,6 +507,17 @@ }; }; + sdio: sdio@40012c00 { + compatible = "arm,pl180", "arm,primecell"; + arm,primecell-periphid = <0x00880180>; + reg = <0x40012c00 0x400>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>; + clock-names = "apb_pclk"; + interrupts = <49>; + max-frequency = <48000000>; + status = "disabled"; + }; + syscfg: system-config@40013800 { compatible = "syscon"; reg = <0x40013800 0x400>; @@ -540,6 +553,7 @@ }; timers10: timers@40014400 { + #address-cells = <1>; #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40014400 0x400>; @@ -554,6 +568,7 @@ }; timers11: timers@40014800 { + #address-cells = <1>; #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40014800 0x400>; @@ -572,18 +587,6 @@ reg = <0x40007000 0x400>; }; - sdio: sdio@40012c00 { - compatible = "st,stm32f4xx-sdio"; - reg = <0x40012c00 0x400>; - clocks = <&rcc 0 171>; - interrupts = <49>; - status = "disabled"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_pins_od>; - pinctrl-names = "default", "opendrain"; - max-frequency = <48000000>; - }; - ltdc: display-controller@40016800 { compatible = "st,stm32-ltdc"; reg = <0x40016800 0x200>; diff --git a/arch/arm/dts/stm32f469-disco.dts b/arch/arm/dts/stm32f469-disco.dts index 3ecef28673..3ceb84d8ba 100644 --- a/arch/arm/dts/stm32f469-disco.dts +++ b/arch/arm/dts/stm32f469-disco.dts @@ -41,8 +41,10 @@ */ /dts-v1/; -#include "stm32f429.dtsi" +#include "stm32f469.dtsi" #include "stm32f469-pinctrl.dtsi" +#include +#include / { model = "STMicroelectronics STM32F469i-DISCO board"; @@ -72,11 +74,40 @@ dma-ranges = <0xc0000000 0x0 0x10000000>; }; + leds { + compatible = "gpio-leds"; + green { + gpios = <&gpiog 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + orange { + gpios = <&gpiod 4 GPIO_ACTIVE_LOW>; + }; + red { + gpios = <&gpiod 5 GPIO_ACTIVE_LOW>; + }; + blue { + gpios = <&gpiok 3 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + button@0 { + label = "User"; + linux,code = ; + gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; + }; + }; + /* This turns on vbus for otg for host mode (dwc2) */ vcc5v_otg: vcc5v-otg-regulator { compatible = "regulator-fixed"; enable-active-high; - gpio = <&gpiob 2 0>; + gpio = <&gpiob 2 GPIO_ACTIVE_HIGH>; regulator-name = "vcc5_host1"; regulator-always-on; }; @@ -90,6 +121,55 @@ clock-frequency = <8000000>; }; +&dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&dsi_panel_in>; + }; + }; + }; + + panel-dsi@0 { + compatible = "orisetech,otm8009a"; + reg = <0>; /* dsi virtual channel (0..3) */ + reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>; + status = "okay"; + + port { + dsi_panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +<dc { + dma-ranges; + status = "okay"; + + port { + ltdc_out_dsi: endpoint@0 { + remote-endpoint = <&dsi_in>; + }; + }; +}; + &rtc { status = "okay"; }; @@ -125,6 +205,8 @@ &sdio { status = "okay"; vmmc-supply = <&mmc_vcard>; + cd-gpios = <&gpiog 2 GPIO_ACTIVE_LOW>; + broken-cd; pinctrl-names = "default", "opendrain"; pinctrl-0 = <&sdio_pins>; pinctrl-1 = <&sdio_pins_od>; diff --git a/arch/arm/dts/stm32f469-pinctrl.dtsi b/arch/arm/dts/stm32f469-pinctrl.dtsi index dd641580c9..fff542662e 100644 --- a/arch/arm/dts/stm32f469-pinctrl.dtsi +++ b/arch/arm/dts/stm32f469-pinctrl.dtsi @@ -1,6 +1,5 @@ /* - * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Alexandre Torgue for STMicroelectronics. + * Copyright 2017 - Alexandre Torgue * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual diff --git a/arch/arm/dts/stm32f469.dtsi b/arch/arm/dts/stm32f469.dtsi new file mode 100644 index 0000000000..0d58d40649 --- /dev/null +++ b/arch/arm/dts/stm32f469.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright (C) STMicroelectronics 2017 - All Rights Reserved */ + +#include "stm32f429.dtsi" + +/ { + soc { + dsi: dsi@40016c00 { + compatible = "st,stm32-dsi"; + reg = <0x40016c00 0x800>; + interrupts = <92>; + resets = <&rcc STM32F4_APB2_RESET(DSI)>; + reset-names = "apb"; + clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>; + clock-names = "pclk", "ref"; + status = "disabled"; + }; + }; +}; -- cgit From 01aabf97d1f08694ed511785638685cbee21e597 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Tue, 19 Feb 2019 00:37:20 +0100 Subject: ARM: dts: stm32: Migrate U-boot nodes to U-boot DT files for stm32f7 In order to prepare and ease future DT synchronization with kernel DT, migrate all U-boot specific nodes/properties/addons to U-boot DT files. Migrate also DT nodes which are not yet available on kernel DT side as ethernet, ltdc and qspi nodes. Fix ethernet_mii pins and add missing qspi_pins for stm32746g-eval Signed-off-by: Patrice Chotard --- arch/arm/dts/stm32746g-eval-u-boot.dtsi | 171 +++++++++++++++++++++ arch/arm/dts/stm32746g-eval.dts | 142 +---------------- arch/arm/dts/stm32f7-u-boot.dtsi | 143 ++++++++++++++++-- arch/arm/dts/stm32f746-disco-u-boot.dtsi | 251 +++++++++++++++++++++++++++++++ arch/arm/dts/stm32f746-disco.dts | 217 -------------------------- arch/arm/dts/stm32f746.dtsi | 60 +------- arch/arm/dts/stm32f769-disco-u-boot.dtsi | 165 ++++++++++++++++++++ arch/arm/dts/stm32f769-disco.dts | 167 -------------------- 8 files changed, 718 insertions(+), 598 deletions(-) create mode 100644 arch/arm/dts/stm32746g-eval-u-boot.dtsi create mode 100644 arch/arm/dts/stm32f746-disco-u-boot.dtsi create mode 100644 arch/arm/dts/stm32f769-disco-u-boot.dtsi (limited to 'arch') diff --git a/arch/arm/dts/stm32746g-eval-u-boot.dtsi b/arch/arm/dts/stm32746g-eval-u-boot.dtsi new file mode 100644 index 0000000000..27d3c8a445 --- /dev/null +++ b/arch/arm/dts/stm32746g-eval-u-boot.dtsi @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +/{ + chosen { + bootargs = "root=/dev/mmcblk0p1 rw rootwait"; + }; + + aliases { + /* Aliases for gpios so as to use sequence */ + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + mmc0 = &sdio; + spi0 = &qspi; + }; + + button1 { + compatible = "st,button1"; + button-gpio = <&gpioc 13 0>; + }; + + led1 { + compatible = "st,led1"; + led-gpio = <&gpiof 10 0>; + }; +}; + +&fmc { + /* + * Memory configuration from sdram datasheet IS42S32800G-6BLI + */ + bank1: bank@0 { + u-boot,dm-pre-reloc; + st,sdram-control = /bits/ 8 ; + st,sdram-timing = /bits/ 8 ; + st,sdram-refcount = <1539>; + }; +}; + +&mac { + phy-mode = "mii"; +}; + +&pinctrl { + ethernet_mii: mii@0 { + pins { + pinmux = , + , + , + , + , + , + , + , + ; + slew-rate = <2>; + }; + }; + + fmc_pins: fmc@0 { + pins { + pinmux = , /* FMC_D31 */ + , /* FMC_D30*/ + , /* FMC_D29 */ + , /* FMC_D28 */ + , /* FMC_D27 */ + , /* FMC_D26 */ + , /* FMC_D25 */ + , /* FMC_D24 */ + , /* FMC_D23 */ + , /* FMC_D22 */ + , /* FMC_D21 */ + , /* FMC_D20 */ + , /* FMC_D19 */ + , /* FMC_D18 */ + , /* FMC_D17 */ + , /* FMC_D16 */ + + , /* FMC_D15 */ + , /* FMC_D14*/ + , /* FMC_D13 */ + ,/* FMC_D12 */ + ,/* FMC_D11 */ + ,/* FMC_D10 */ + , /* FMC_D9 */ + , /* FMC_D8 */ + , /* FMC_D7 */ + , /* FMC_D6 */ + , /* FMC_D5*/ + , /* FMC_D4 */ + , /* FMC_D3 */ + , /* FMC_D2 */ + , /* FMC_D1 */ + , /* FMC_D0 */ + + , /* FMC_NBL3 */ + , /* FMC_NBL2 */ + , /* FMC_NBL1 */ + , /* FMC_NBL0 */ + + , /* FMC_A15 FMC_BA1 */ + , /* FMC_A14 FMC_BA0*/ + + , /* FMC_A11 */ + , /* FMC_A10 */ + , /* FMC_A9 */ + , /* FMC_A8 */ + , /* FMC_A7 */ + , /* FMC_A6 */ + , /* FUNC_FMC_A5 */ + , /* FMC_A4 */ + , /* FMC_A3 */ + , /* FMC_A2 */ + , /* FMC_A1 */ + , /* FMC_A0 */ + + ,/* FMC_SDNE0 */ + , /* FMC_SDNWE */ + , /* FMC_SDNRAS */ + , /* FMC_SDNCAS */ + , /* FMC_SDCKE0 */ + ; /* FMC_SDCLK */ + slew-rate = <2>; + }; + }; + + qspi_pins: qspi@0 { + pins { + pinmux = , + , + , + , + , + ; + slew-rate = <2>; + }; + }; +}; + +&qspi { + qflash0: n25q512a { + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <108000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + reg = <0>; + }; +}; diff --git a/arch/arm/dts/stm32746g-eval.dts b/arch/arm/dts/stm32746g-eval.dts index 4f6d38accc..94df80f69d 100644 --- a/arch/arm/dts/stm32746g-eval.dts +++ b/arch/arm/dts/stm32746g-eval.dts @@ -53,7 +53,6 @@ compatible = "st,stm32f746g-eval", "st,stm32f746"; chosen { - bootargs = "root=/dev/mmcblk0p1 rw rootwait"; stdout-path = "serial0:115200n8"; }; @@ -63,30 +62,6 @@ aliases { serial0 = &usart1; - spi0 = &qspi; - mmc0 = &sdio; - /* Aliases for gpios so as to use sequence */ - gpio0 = &gpioa; - gpio1 = &gpiob; - gpio2 = &gpioc; - gpio3 = &gpiod; - gpio4 = &gpioe; - gpio5 = &gpiof; - gpio6 = &gpiog; - gpio7 = &gpioh; - gpio8 = &gpioi; - gpio9 = &gpioj; - gpio10 = &gpiok; - }; - - led1 { - compatible = "st,led1"; - led-gpio = <&gpiof 10 0>; - }; - - button1 { - compatible = "st,button1"; - button-gpio = <&gpioc 13 0>; }; }; @@ -97,7 +72,7 @@ &pinctrl { usart1_pins_a: usart1@0 { pins1 { - pinmux = ; + pinmux = ; bias-disable; drive-push-pull; slew-rate = <2>; @@ -107,88 +82,6 @@ bias-disable; }; }; - - ethernet_mii: mii@0 { - pins { - pinmux = , - , - , - , - , - , - , - , - ; - slew-rate = <2>; - }; - }; - - fmc_pins: fmc@0 { - pins { - pinmux = , /* FMC_D31 */ - , /* FMC_D30*/ - , /* FMC_D29 */ - , /* FMC_D28 */ - , /* FMC_D27 */ - , /* FMC_D26 */ - , /* FMC_D25 */ - , /* FMC_D24 */ - , /* FMC_D23 */ - , /* FMC_D22 */ - , /* FMC_D21 */ - , /* FMC_D20 */ - , /* FMC_D19 */ - , /* FMC_D18 */ - , /* FMC_D17 */ - , /* FMC_D16 */ - - , /* FMC_D15 */ - , /* FMC_D14*/ - , /* FMC_D13 */ - ,/* FMC_D12 */ - ,/* FMC_D11 */ - ,/* FMC_D10 */ - , /* FMC_D9 */ - , /* FMC_D8 */ - , /* FMC_D7 */ - , /* FMC_D6 */ - , /* FMC_D5*/ - , /* FMC_D4 */ - , /* FMC_D3 */ - , /* FMC_D2 */ - , /* FMC_D1 */ - , /* FMC_D0 */ - - , /* FMC_NBL3 */ - , /* FMC_NBL2 */ - , /* FMC_NBL1 */ - , /* FMC_NBL0 */ - - , /* FMC_A15 FMC_BA1 */ - , /* FMC_A14 FMC_BA0*/ - - , /* FMC_A11 */ - , /* FMC_A10 */ - , /* FMC_A9 */ - , /* FMC_A8 */ - , /* FMC_A7 */ - , /* FMC_A6 */ - , /* FUNC_FMC_A5 */ - , /* FMC_A4 */ - , /* FMC_A3 */ - , /* FMC_A2 */ - , /* FMC_A1 */ - , /* FMC_A0 */ - - ,/* FMC_SDNE0 */ - , /* FMC_SDNWE */ - , /* FMC_SDNRAS */ - , /* FMC_SDNCAS */ - , /* FMC_SDCKE0 */ - ; /* FMC_SDCLK */ - slew-rate = <2>; - }; - }; }; &usart1 { @@ -197,39 +90,6 @@ status = "okay"; }; -&mac { - status = "okay"; - pinctrl-0 = <ðernet_mii>; - phy-mode = "rmii"; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&fmc { - pinctrl-0 = <&fmc_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* - * Memory configuration from sdram datasheet IS42S32800G-6BLI - */ - bank1: bank@0 { - st,sdram-control = /bits/ 8 ; - st,sdram-timing = /bits/ 8 ; - st,sdram-refcount = <1539>; - }; -}; - &sdio { status = "okay"; pinctrl-names = "default", "opendrain"; diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi index 4a677192a2..cf0cc3b408 100644 --- a/arch/arm/dts/stm32f7-u-boot.dtsi +++ b/arch/arm/dts/stm32f7-u-boot.dtsi @@ -1,12 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ + /{ soc { - timer5: timer@40000c00 { + u-boot,dm-pre-reloc; + + fmc: fmc@A0000000 { + compatible = "st,stm32-fmc"; + reg = <0xA0000000 0x1000>; + clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>; + pinctrl-0 = <&fmc_pins>; + pinctrl-names = "default"; + status = "okay"; u-boot,dm-pre-reloc; }; + + mac: ethernet@40028000 { + compatible = "st,stm32-dwmac"; + reg = <0x40028000 0x8000>; + reg-names = "stmmaceth"; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>, + <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>, + <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>; + interrupts = <61>, <62>; + interrupt-names = "macirq", "eth_wake_irq"; + snps,pbl = <8>; + snps,mixed-burst; + dma-ranges; + pinctrl-0 = <ðernet_mii>; + phy-mode = "rmii"; + phy-handle = <&phy0>; + + status = "okay"; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; + }; + + qspi: quadspi@A0001000 { + compatible = "st,stm32-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; + interrupts = <92>; + spi-max-frequency = <108000000>; + clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>; + resets = <&rcc STM32F7_AHB3_RESET(QSPI)>; + pinctrl-0 = <&qspi_pins>; + + status = "okay"; + }; }; }; +&clk_hse { + u-boot,dm-pre-reloc; +}; + +&gpioa { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiob { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioc { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiod { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioe { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiof { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiog { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioh { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioi { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioj { + compatible = "st,stm32-gpio"; +}; + +&gpiok { + compatible = "st,stm32-gpio"; +}; + &pinctrl { + u-boot,dm-pre-reloc; + + fmc_pins: fmc@0 { + u-boot,dm-pre-reloc; + pins + { + u-boot,dm-pre-reloc; + }; + }; + usart1_pins_a: usart1@0 { u-boot,dm-pre-reloc; pins1 { @@ -16,25 +136,20 @@ u-boot,dm-pre-reloc; }; }; - fmc_pins: fmc@0 { - u-boot,dm-pre-reloc; - pins - { - u-boot,dm-pre-reloc; - }; - }; }; -&fmc { - bank1: bank@0 { - u-boot,dm-pre-reloc; - }; +&pwrcfg { + u-boot,dm-pre-reloc; }; -&pwrcfg { +&rcc { u-boot,dm-pre-reloc; }; -&clk_hse { +&timer5 { + u-boot,dm-pre-reloc; +}; + +&usart1 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi new file mode 100644 index 0000000000..ceab5e5933 --- /dev/null +++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +/{ + chosen { + bootargs = "root=/dev/ram rdinit=/linuxrc"; + }; + + aliases { + /* Aliases for gpios so as to use sequence */ + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + mmc0 = &sdio; + spi0 = &qspi; + }; + + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpiok 3 0>; + status = "okay"; + }; + + button1 { + compatible = "st,button1"; + button-gpio = <&gpioi 11 0>; + }; + + led1 { + compatible = "st,led1"; + led-gpio = <&gpioi 1 0>; + }; + + panel-rgb@0 { + compatible = "simple-panel"; + backlight = <&backlight>; + enable-gpios = <&gpioi 12 0>; + status = "okay"; + + display-timings { + timing@0 { + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <2>; + hback-porch = <2>; + hsync-len = <41>; + vfront-porch = <2>; + vback-porch = <2>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + }; + + soc { + ltdc: display-controller@40016800 { + compatible = "st,stm32-ltdc"; + reg = <0x40016800 0x200>; + resets = <&rcc STM32F7_APB2_RESET(LTDC)>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>; + pinctrl-0 = <<dc_pins>; + + status = "okay"; + u-boot,dm-pre-reloc; + }; + }; +}; + +&clk_hse { + u-boot,dm-pre-reloc; +}; + +&fmc { + /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */ + bank1: bank@0 { + u-boot,dm-pre-reloc; + st,sdram-control = /bits/ 8 ; + st,sdram-timing = /bits/ 8 ; + /* refcount = (64msec/total_row_sdram)*freq - 20 */ + st,sdram-refcount = < 1542 >; + }; +}; + +&pinctrl { + ethernet_mii: mii@0 { + pins { + pinmux = , + , + , + , + , + , + , + , + ; + slew-rate = <2>; + }; + }; + + fmc_pins: fmc@0 { + u-boot,dm-pre-reloc; + pins { + u-boot,dm-pre-reloc; + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + + , + , + + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + ; + slew-rate = <2>; + }; + }; + + ltdc_pins: ltdc@0 { + pins { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + slew-rate = <2>; + }; + }; + + qspi_pins: qspi@0 { + pins { + pinmux = , + , + , + , + , + ; + slew-rate = <2>; + }; + }; + + usart1_pins_a: usart1@0 { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + }; + }; +}; + +&pwrcfg { + u-boot,dm-pre-reloc; +}; + +&qspi { + qflash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a13", "jedec,spi-nor"; + spi-max-frequency = <108000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + memory-map = <0x90000000 0x1000000>; + reg = <0>; + }; +}; + +&timer5 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts index babd37f1c1..d568765170 100644 --- a/arch/arm/dts/stm32f746-disco.dts +++ b/arch/arm/dts/stm32f746-disco.dts @@ -65,62 +65,8 @@ aliases { serial0 = &usart1; - spi0 = &qspi; - mmc0 = &sdio; - /* Aliases for gpios so as to use sequence */ - gpio0 = &gpioa; - gpio1 = &gpiob; - gpio2 = &gpioc; - gpio3 = &gpiod; - gpio4 = &gpioe; - gpio5 = &gpiof; - gpio6 = &gpiog; - gpio7 = &gpioh; - gpio8 = &gpioi; - gpio9 = &gpioj; - gpio10 = &gpiok; }; - led1 { - compatible = "st,led1"; - led-gpio = <&gpioi 1 0>; - }; - - button1 { - compatible = "st,button1"; - button-gpio = <&gpioi 11 0>; - }; - - backlight: backlight { - compatible = "gpio-backlight"; - gpios = <&gpiok 3 0>; - status = "okay"; - }; - - panel-rgb@0 { - compatible = "simple-panel"; - backlight = <&backlight>; - enable-gpios = <&gpioi 12 0>; - status = "okay"; - - display-timings { - timing@0 { - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <2>; - hback-porch = <2>; - hsync-len = <41>; - vfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <1>; - }; - }; - }; }; &clk_hse { @@ -140,115 +86,6 @@ bias-disable; }; }; - - ethernet_mii: mii@0 { - pins { - pinmux = , - , - , - , - , - , - , - , - ; - slew-rate = <2>; - }; - }; - - qspi_pins: qspi@0 { - pins { - pinmux = , - , - , - , - , - ; - slew-rate = <2>; - }; - }; - - fmc_pins: fmc@0 { - pins { - pinmux = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - - , - , - - , - , - - , - , - , - , - , - , - , - , - , - , - , - , - - , - , - , - , - , - ; - slew-rate = <2>; - }; - }; - - ltdc_pins: ltdc@0 { - pins { - pinmux = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - slew-rate = <2>; - }; - }; }; &usart1 { @@ -257,55 +94,6 @@ status = "okay"; }; -&fmc { - pinctrl-0 = <&fmc_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */ - bank1: bank@0 { - st,sdram-control = /bits/ 8 ; - st,sdram-timing = /bits/ 8 ; - /* refcount = (64msec/total_row_sdram)*freq - 20 */ - st,sdram-refcount = < 1542 >; - }; -}; - -&mac { - status = "okay"; - pinctrl-0 = <ðernet_mii>; - phy-mode = "rmii"; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - status = "okay"; - - qflash0: n25q128a { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q128a13", "jedec,spi-nor"; - spi-max-frequency = <108000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - memory-map = <0x90000000 0x1000000>; - reg = <0>; - }; -}; - &sdio { status = "okay"; cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; @@ -315,8 +103,3 @@ bus-width = <4>; max-frequency = <25000000>; }; - -<dc { - status = "okay"; - pinctrl-0 = <<dc_pins>; -}; diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index afa7832f89..7209864266 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -57,51 +57,15 @@ compatible = "fixed-clock"; clock-frequency = <0>; }; -}; + }; soc { - u-boot,dm-pre-reloc; - mac: ethernet@40028000 { - compatible = "st,stm32-dwmac"; - reg = <0x40028000 0x8000>; - reg-names = "stmmaceth"; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>, - <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>, - <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>; - interrupts = <61>, <62>; - interrupt-names = "macirq", "eth_wake_irq"; - snps,pbl = <8>; - snps,mixed-burst; - dma-ranges; - status = "disabled"; - }; - - fmc: fmc@A0000000 { - compatible = "st,stm32-fmc"; - reg = <0xA0000000 0x1000>; - clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>; - u-boot,dm-pre-reloc; - }; - - qspi: quadspi@A0001000 { - compatible = "st,stm32-qspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>; - reg-names = "qspi", "qspi_mm"; - interrupts = <92>; - spi-max-frequency = <108000000>; - clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>; - resets = <&rcc STM32F7_AHB3_RESET(QSPI)>; - status = "disabled"; - }; usart1: serial@40011000 { compatible = "st,stm32f7-usart", "st,stm32f7-uart"; reg = <0x40011000 0x400>; interrupts = <37>; clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>; status = "disabled"; - u-boot,dm-pre-reloc; }; pwrcfg: power-config@58024800 { @@ -116,7 +80,6 @@ reg = <0x40023800 0x400>; clocks = <&clk_hse>; st,syscfg = <&pwrcfg>; - u-boot,dm-pre-reloc; }; pinctrl: pin-controller { @@ -124,7 +87,6 @@ #size-cells = <1>; compatible = "st,stm32f746-pinctrl"; ranges = <0 0x40020000 0x3000>; - u-boot,dm-pre-reloc; pins-are-numbered; gpioa: gpio@40020000 { @@ -134,7 +96,6 @@ reg = <0x0 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>; st,bank-name = "GPIOA"; - u-boot,dm-pre-reloc; }; gpiob: gpio@40020400 { @@ -144,7 +105,6 @@ reg = <0x400 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>; st,bank-name = "GPIOB"; - u-boot,dm-pre-reloc; }; @@ -155,7 +115,6 @@ reg = <0x800 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>; st,bank-name = "GPIOC"; - u-boot,dm-pre-reloc; }; gpiod: gpio@40020c00 { @@ -165,7 +124,6 @@ reg = <0xc00 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>; st,bank-name = "GPIOD"; - u-boot,dm-pre-reloc; }; gpioe: gpio@40021000 { @@ -175,7 +133,6 @@ reg = <0x1000 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>; st,bank-name = "GPIOE"; - u-boot,dm-pre-reloc; }; gpiof: gpio@40021400 { @@ -185,7 +142,6 @@ reg = <0x1400 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>; st,bank-name = "GPIOF"; - u-boot,dm-pre-reloc; }; gpiog: gpio@40021800 { @@ -195,7 +151,6 @@ reg = <0x1800 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>; st,bank-name = "GPIOG"; - u-boot,dm-pre-reloc; }; gpioh: gpio@40021c00 { @@ -205,7 +160,6 @@ reg = <0x1c00 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>; st,bank-name = "GPIOH"; - u-boot,dm-pre-reloc; }; gpioi: gpio@40022000 { @@ -215,7 +169,6 @@ reg = <0x2000 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>; st,bank-name = "GPIOI"; - u-boot,dm-pre-reloc; }; gpioj: gpio@40022400 { @@ -225,7 +178,6 @@ reg = <0x2400 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>; st,bank-name = "GPIOJ"; - u-boot,dm-pre-reloc; }; gpiok: gpio@40022800 { @@ -235,7 +187,6 @@ reg = <0x2800 0x400>; clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>; st,bank-name = "GPIOK"; - u-boot,dm-pre-reloc; }; sdio_pins: sdio_pins@0 { @@ -331,15 +282,6 @@ interrupts = <50>; clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; }; - - ltdc: display-controller@40016800 { - compatible = "st,stm32-ltdc"; - reg = <0x40016800 0x200>; - resets = <&rcc STM32F7_APB2_RESET(LTDC)>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>; - u-boot,dm-pre-reloc; - status = "disabled"; - }; }; }; diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi b/arch/arm/dts/stm32f769-disco-u-boot.dtsi new file mode 100644 index 0000000000..217c937b23 --- /dev/null +++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +/{ + chosen { + bootargs = "root=/dev/ram rdinit=/linuxrc"; + }; + + aliases { + /* Aliases for gpios so as to use sequence */ + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + mmc0 = &sdio2; + spi0 = &qspi; + }; + + button1 { + compatible = "st,button1"; + button-gpio = <&gpioa 0 0>; + }; + + led1 { + compatible = "st,led1"; + led-gpio = <&gpioj 5 0>; + }; +}; + +&fmc { + /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */ + bank1: bank@0 { + u-boot,dm-pre-reloc; + st,sdram-control = /bits/ 8 ; + st,sdram-timing = /bits/ 8 ; + /* refcount = (64msec/total_row_sdram)*freq - 20 */ + st,sdram-refcount = < 1542 >; + }; +}; + +&pinctrl { + ethernet_mii: mii@0 { + pins { + pinmux = , + , + , + , + , + , + , + , + ; + slew-rate = <2>; + }; + }; + + fmc_pins: fmc@0 { + pins { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + + , + , + + , + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + ; + slew-rate = <2>; + }; + }; + + qspi_pins: qspi@0 { + pins { + pinmux = , + , + , + , + , + ; + slew-rate = <2>; + }; + }; +}; + +&qspi { + flash0: mx66l51235l { + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <108000000>; + spi-rx-bus-width = <4>; + reg = <0>; + }; +}; diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts index a23d02d300..046bb225a6 100644 --- a/arch/arm/dts/stm32f769-disco.dts +++ b/arch/arm/dts/stm32f769-disco.dts @@ -50,7 +50,6 @@ compatible = "st,stm32f769-disco", "st,stm32f7"; chosen { - bootargs = "root=/dev/ram rdinit=/linuxrc"; stdout-path = "serial0:115200n8"; }; @@ -60,30 +59,6 @@ aliases { serial0 = &usart1; - spi0 = &qspi; - mmc0 = &sdio2; - /* Aliases for gpios so as to use sequence */ - gpio0 = &gpioa; - gpio1 = &gpiob; - gpio2 = &gpioc; - gpio3 = &gpiod; - gpio4 = &gpioe; - gpio5 = &gpiof; - gpio6 = &gpiog; - gpio7 = &gpioh; - gpio8 = &gpioi; - gpio9 = &gpioj; - gpio10 = &gpiok; - }; - - led1 { - compatible = "st,led1"; - led-gpio = <&gpioj 5 0>; - }; - - button1 { - compatible = "st,button1"; - button-gpio = <&gpioa 0 0>; }; }; @@ -105,99 +80,6 @@ }; }; - ethernet_mii: mii@0 { - pins { - pinmux = , - , - , - , - , - , - , - , - ; - slew-rate = <2>; - }; - }; - - qspi_pins: qspi@0 { - pins { - pinmux = , - , - , - , - , - ; - slew-rate = <2>; - }; - }; - - fmc_pins: fmc@0 { - pins { - pinmux = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - - , - , - , - , - - , - , - - , - , - , - , - , - , - , - , - , - , - , - , - - , - , - , - , - , - ; - slew-rate = <2>; - }; - }; }; &usart1 { @@ -206,55 +88,6 @@ status = "okay"; }; -&fmc { - pinctrl-0 = <&fmc_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */ - bank1: bank@0 { - st,sdram-control = /bits/ 8 ; - st,sdram-timing = /bits/ 8 ; - /* refcount = (64msec/total_row_sdram)*freq - 20 */ - st,sdram-refcount = < 1542 >; - }; -}; - -&mac { - status = "okay"; - pinctrl-0 = <ðernet_mii>; - phy-mode = "rmii"; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&qspi { - pinctrl-0 = <&qspi_pins>; - status = "okay"; - - qflash0: n25q128a { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q128a13", "jedec,spi-nor"; - spi-max-frequency = <108000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - memory-map = <0x90000000 0x1000000>; - reg = <0>; - }; -}; - &sdio2 { status = "okay"; cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>; -- cgit From fe63d3cfb77ef5986951c04a9fa8fe73fb32fdb6 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Tue, 19 Feb 2019 16:49:05 +0100 Subject: ARM: dts: stm32: Sync DT with v4.20 kernel for stm32f7 Synchronize stm32f7 device tree with kernel v4.20. All pinctrl bindings are updated. Signed-off-by: Patrice Chotard --- arch/arm/dts/stm32746g-eval-u-boot.dtsi | 171 ++++---- arch/arm/dts/stm32746g-eval.dts | 102 +++-- arch/arm/dts/stm32f7-pinctrl.dtsi | 289 +++++++++++++ arch/arm/dts/stm32f7-u-boot.dtsi | 11 +- arch/arm/dts/stm32f746-disco-u-boot.dtsi | 174 ++++---- arch/arm/dts/stm32f746-disco.dts | 84 ++-- arch/arm/dts/stm32f746-pinctrl.dtsi | 11 + arch/arm/dts/stm32f746.dtsi | 699 +++++++++++++++++++++++-------- arch/arm/dts/stm32f769-disco-u-boot.dtsi | 142 +++---- arch/arm/dts/stm32f769-disco.dts | 93 +++- arch/arm/dts/stm32f769-pinctrl.dtsi | 11 + 11 files changed, 1287 insertions(+), 500 deletions(-) create mode 100644 arch/arm/dts/stm32f7-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32f746-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32f769-pinctrl.dtsi (limited to 'arch') diff --git a/arch/arm/dts/stm32746g-eval-u-boot.dtsi b/arch/arm/dts/stm32746g-eval-u-boot.dtsi index 27d3c8a445..9b55bb7601 100644 --- a/arch/arm/dts/stm32746g-eval-u-boot.dtsi +++ b/arch/arm/dts/stm32746g-eval-u-boot.dtsi @@ -19,7 +19,7 @@ gpio8 = &gpioi; gpio9 = &gpioj; gpio10 = &gpiok; - mmc0 = &sdio; + mmc0 = &sdio1; spi0 = &qspi; }; @@ -66,97 +66,114 @@ &pinctrl { ethernet_mii: mii@0 { pins { - pinmux = , - , - , - , - , - , - , - , - ; + pinmux = , /*ETH_MII_CRS */ + , /*ETH_MII_RX_CLK */ + , /*ETH_MII_RX_DV */ + , /*ETH_MII_MCO1 */ + , /*ETH_MII_TXD0 */ + , /*ETH_MII_TXD1 */ + , /*ETH_MII_TXD2 */ + , /*ETH_MII_TXD3 */ + , /*ETH_MII_TX_CLK */ + , /*ETH_MII_RXD0 */ + , /*ETH_MII_RXD1 */ + , /*ETH_MII_RXD2 */ + , /*ETH_MII_RXD3 */ + , /*ETH_MII_TX_EN */ + , /*ETH_MII_MDC */ + ; /*ETH_MII_MDIO */ slew-rate = <2>; }; }; fmc_pins: fmc@0 { pins { - pinmux = , /* FMC_D31 */ - , /* FMC_D30*/ - , /* FMC_D29 */ - , /* FMC_D28 */ - , /* FMC_D27 */ - , /* FMC_D26 */ - , /* FMC_D25 */ - , /* FMC_D24 */ - , /* FMC_D23 */ - , /* FMC_D22 */ - , /* FMC_D21 */ - , /* FMC_D20 */ - , /* FMC_D19 */ - , /* FMC_D18 */ - , /* FMC_D17 */ - , /* FMC_D16 */ - - , /* FMC_D15 */ - , /* FMC_D14*/ - , /* FMC_D13 */ - ,/* FMC_D12 */ - ,/* FMC_D11 */ - ,/* FMC_D10 */ - , /* FMC_D9 */ - , /* FMC_D8 */ - , /* FMC_D7 */ - , /* FMC_D6 */ - , /* FMC_D5*/ - , /* FMC_D4 */ - , /* FMC_D3 */ - , /* FMC_D2 */ - , /* FMC_D1 */ - , /* FMC_D0 */ - - , /* FMC_NBL3 */ - , /* FMC_NBL2 */ - , /* FMC_NBL1 */ - , /* FMC_NBL0 */ - - , /* FMC_A15 FMC_BA1 */ - , /* FMC_A14 FMC_BA0*/ - - , /* FMC_A11 */ - , /* FMC_A10 */ - , /* FMC_A9 */ - , /* FMC_A8 */ - , /* FMC_A7 */ - , /* FMC_A6 */ - , /* FUNC_FMC_A5 */ - , /* FMC_A4 */ - , /* FMC_A3 */ - , /* FMC_A2 */ - , /* FMC_A1 */ - , /* FMC_A0 */ - - ,/* FMC_SDNE0 */ - , /* FMC_SDNWE */ - , /* FMC_SDNRAS */ - , /* FMC_SDNCAS */ - , /* FMC_SDCKE0 */ - ; /* FMC_SDCLK */ + pinmux = , /* D31 */ + , /* D30 */ + , /* D29 */ + , /* D28 */ + , /* D27 */ + , /* D26 */ + , /* D25 */ + , /* D24 */ + , /* D23 */ + , /* D22 */ + , /* D21 */ + , /* D20 */ + , /* D19 */ + , /* D18 */ + , /* D17 */ + , /* D16 */ + + , /* D15 */ + , /* D14 */ + , /* D13 */ + , /* D12 */ + , /* D11 */ + , /* D10 */ + , /* D9 */ + , /* D8 */ + , /* D7 */ + , /* D6 */ + , /* D5 */ + , /* D4 */ + , /* D3 */ + , /* D2 */ + , /* D1 */ + , /* D0 */ + + , /* NBL3 */ + , /* NBL2 */ + , /* NBL1 */ + , /* NBL0 */ + + , /* BA1 */ + , /* BA0 */ + + , /* A11 */ + , /* A10 */ + , /* A9 */ + , /* A8 */ + , /* A7 */ + , /* A6 */ + , /* A5 */ + , /* A4 */ + , /* A3 */ + , /* A2 */ + , /* A1 */ + , /* A0 */ + + , /* SDNE0 */ + , /* SDNWE */ + , /* SDNRAS */ + , /* SDNCAS */ + , /* SDCKE0 */ + ; /* SDCLK> */ slew-rate = <2>; }; }; qspi_pins: qspi@0 { pins { - pinmux = , - , - , - , - , - ; + pinmux = , /* _FUNC_QUADSPI_CLK */ + , /*_FUNC_QUADSPI_BK1_NCS */ + , /* _FUNC_QUADSPI_BK1_IO0 */ + , /* _FUNC_QUADSPI_BK1_IO1 */ + , /* AF_FUNC_QUADSPI_BK1_IO3 */ + ; /* _FUNC_QUADSPI_BK1_IO2 */ slew-rate = <2>; }; }; + + usart1_pins_a: usart1@0 { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + }; + }; }; &qspi { diff --git a/arch/arm/dts/stm32746g-eval.dts b/arch/arm/dts/stm32746g-eval.dts index 94df80f69d..8c081eaf20 100644 --- a/arch/arm/dts/stm32746g-eval.dts +++ b/arch/arm/dts/stm32746g-eval.dts @@ -1,9 +1,5 @@ /* - * Copyright 2018 - Christophe Priouzeau - * - * Based on: - * stm32f746-disco.dts from U-boot 2018.01 - * Copyright 2016 - Lee Jones + * Copyright 2015 - Maxime Coquelin * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -46,55 +42,105 @@ /dts-v1/; #include "stm32f746.dtsi" -#include +#include "stm32f746-pinctrl.dtsi" +#include / { - model = "STMicroelectronics STM32F746G-EVAL board"; - compatible = "st,stm32f746g-eval", "st,stm32f746"; + model = "STMicroelectronics STM32746g-EVAL board"; + compatible = "st,stm32746g-eval", "st,stm32f746"; chosen { + bootargs = "root=/dev/ram"; stdout-path = "serial0:115200n8"; }; memory { - reg = <0xC0000000 0x2000000>; + reg = <0xc0000000 0x2000000>; }; aliases { serial0 = &usart1; }; + + leds { + compatible = "gpio-leds"; + green { + gpios = <&gpiof 10 1>; + linux,default-trigger = "heartbeat"; + }; + red { + gpios = <&gpiob 7 1>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + button@0 { + label = "Wake up"; + linux,code = ; + gpios = <&gpioc 13 0>; + }; + }; + + usbotg_hs_phy: usb-phy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; + clock-names = "main_clk"; + }; + + mmc_vcard: mmc_vcard { + compatible = "regulator-fixed"; + regulator-name = "mmc_vcard"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; &clk_hse { clock-frequency = <25000000>; }; -&pinctrl { - usart1_pins_a: usart1@0 { - pins1 { - pinmux = ; - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = ; - bias-disable; - }; - }; +&crc { + status = "okay"; }; -&usart1 { - pinctrl-0 = <&usart1_pins_a>; +&i2c1 { + pinctrl-0 = <&i2c1_pins_b>; pinctrl-names = "default"; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; +}; + +&rtc { status = "okay"; }; -&sdio { +&sdio1 { status = "okay"; + vmmc-supply = <&mmc_vcard>; + broken-cd; pinctrl-names = "default", "opendrain"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_pins_od>; + pinctrl-0 = <&sdio_pins_a>; + pinctrl-1 = <&sdio_pins_od_a>; bus-width = <4>; - max-frequency = <25000000>; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "otg"; + phys = <&usbotg_hs_phy>; + phy-names = "usb2-phy"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + status = "okay"; }; diff --git a/arch/arm/dts/stm32f7-pinctrl.dtsi b/arch/arm/dts/stm32f7-pinctrl.dtsi new file mode 100644 index 0000000000..9314128df1 --- /dev/null +++ b/arch/arm/dts/stm32f7-pinctrl.dtsi @@ -0,0 +1,289 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include +#include + +/ { + soc { + pinctrl: pin-controller { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40020000 0x3000>; + interrupt-parent = <&exti>; + st,syscfg = <&syscfg 0x8>; + pins-are-numbered; + + gpioa: gpio@40020000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>; + st,bank-name = "GPIOA"; + }; + + gpiob: gpio@40020400 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x400 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>; + st,bank-name = "GPIOB"; + }; + + gpioc: gpio@40020800 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x800 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>; + st,bank-name = "GPIOC"; + }; + + gpiod: gpio@40020c00 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xc00 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>; + st,bank-name = "GPIOD"; + }; + + gpioe: gpio@40021000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>; + st,bank-name = "GPIOE"; + }; + + gpiof: gpio@40021400 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1400 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>; + st,bank-name = "GPIOF"; + }; + + gpiog: gpio@40021800 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1800 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>; + st,bank-name = "GPIOG"; + }; + + gpioh: gpio@40021c00 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1c00 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>; + st,bank-name = "GPIOH"; + }; + + gpioi: gpio@40022000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>; + st,bank-name = "GPIOI"; + }; + + gpioj: gpio@40022400 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2400 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>; + st,bank-name = "GPIOJ"; + }; + + gpiok: gpio@40022800 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2800 0x400>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>; + st,bank-name = "GPIOK"; + }; + + cec_pins_a: cec@0 { + pins { + pinmux = ; /* HDMI CEC */ + slew-rate = <0>; + drive-open-drain; + bias-disable; + }; + }; + + usart1_pins_a: usart1@0 { + pins1 { + pinmux = ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-disable; + }; + }; + + usart1_pins_b: usart1@1 { + pins1 { + pinmux = ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-disable; + }; + }; + + i2c1_pins_b: i2c1@0 { + pins { + pinmux = , /* I2C1 SDA */ + ; /* I2C1 SCL */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + usbotg_hs_pins_a: usbotg-hs@0 { + pins { + pinmux = , /* OTG_HS_ULPI_NXT */ + , /* OTG_HS_ULPI_DIR */ + , /* OTG_HS_ULPI_STP */ + , /* OTG_HS_ULPI_CK */ + , /* OTG_HS_ULPI_D0 */ + , /* OTG_HS_ULPI_D1 */ + , /* OTG_HS_ULPI_D2 */ + , /* OTG_HS_ULPI_D3 */ + , /* OTG_HS_ULPI_D4 */ + , /* OTG_HS_ULPI_D5 */ + , /* OTG_HS_ULPI_D6 */ + ; /* OTG_HS_ULPI_D7 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + usbotg_hs_pins_b: usbotg-hs@1 { + pins { + pinmux = , /* OTG_HS_ULPI_NXT */ + , /* OTG_HS_ULPI_DIR */ + , /* OTG_HS_ULPI_STP */ + , /* OTG_HS_ULPI_CK */ + , /* OTG_HS_ULPI_D0 */ + , /* OTG_HS_ULPI_D1 */ + , /* OTG_HS_ULPI_D2 */ + , /* OTG_HS_ULPI_D3 */ + , /* OTG_HS_ULPI_D4 */ + , /* OTG_HS_ULPI_D5 */ + , /* OTG_HS_ULPI_D6 */ + ; /* OTG_HS_ULPI_D7 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + usbotg_fs_pins_a: usbotg-fs@0 { + pins { + pinmux = , /* OTG_FS_ID */ + , /* OTG_FS_DM */ + ; /* OTG_FS_DP */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + sdio_pins_a: sdio_pins_a@0 { + pins { + pinmux = , /* SDMMC1 D0 */ + , /* SDMMC1 D1 */ + , /* SDMMC1 D2 */ + , /* SDMMC1 D3 */ + , /* SDMMC1 CLK */ + ; /* SDMMC1 CMD */ + drive-push-pull; + slew-rate = <2>; + }; + }; + + sdio_pins_od_a: sdio_pins_od_a@0 { + pins1 { + pinmux = , /* SDMMC1 D0 */ + , /* SDMMC1 D1 */ + , /* SDMMC1 D2 */ + , /* SDMMC1 D3 */ + ; /* SDMMC1 CLK */ + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = ; /* SDMMC1 CMD */ + drive-open-drain; + slew-rate = <2>; + }; + }; + + sdio_pins_b: sdio_pins_b@0 { + pins { + pinmux = , /* SDMMC2 D0 */ + , /* SDMMC2 D1 */ + , /* SDMMC2 D2 */ + , /* SDMMC2 D3 */ + , /* SDMMC2 CLK */ + ; /* SDMMC2 CMD */ + drive-push-pull; + slew-rate = <2>; + }; + }; + + sdio_pins_od_b: sdio_pins_od_b@0 { + pins1 { + pinmux = , /* SDMMC2 D0 */ + , /* SDMMC2 D1 */ + , /* SDMMC2 D2 */ + , /* SDMMC2 D3 */ + ; /* SDMMC2 CLK */ + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = ; /* SDMMC2 CMD */ + drive-open-drain; + slew-rate = <2>; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi index cf0cc3b408..7816b79bcf 100644 --- a/arch/arm/dts/stm32f7-u-boot.dtsi +++ b/arch/arm/dts/stm32f7-u-boot.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ +#include /{ soc { u-boot,dm-pre-reloc; @@ -126,16 +127,6 @@ u-boot,dm-pre-reloc; }; }; - - usart1_pins_a: usart1@0 { - u-boot,dm-pre-reloc; - pins1 { - u-boot,dm-pre-reloc; - }; - pins2 { - u-boot,dm-pre-reloc; - }; - }; }; &pwrcfg { diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi index ceab5e5933..bc337b1628 100644 --- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi @@ -19,7 +19,7 @@ gpio8 = &gpioi; gpio9 = &gpioj; gpio10 = &gpiok; - mmc0 = &sdio; + mmc0 = &sdio1; spi0 = &qspi; }; @@ -109,15 +109,15 @@ &pinctrl { ethernet_mii: mii@0 { pins { - pinmux = , - , - , - , - , - , - , - , - ; + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_TX_EN */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RMII_REF_CLK */ + , /* ETH_RMII_CRS_DV */ + , /* ETH_RMII_RXD0 */ + ; /* ETH_RMII_RXD1 */ slew-rate = <2>; }; }; @@ -126,99 +126,99 @@ u-boot,dm-pre-reloc; pins { u-boot,dm-pre-reloc; - pinmux = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - - , - , - - , - , - - , - , - , - , - , - , - , - , - , - , - , - , - - , - , - , - , - , - ; + pinmux = , /* D15 */ + , /* D14 */ + , /* D13 */ + , /* D12 */ + , /* D11 */ + , /* D10 */ + , /* D9 */ + , /* D8 */ + , /* D7 */ + , /* D6 */ + , /* D5 */ + , /* D4 */ + , /* D3 */ + , /* D2 */ + , /* D1 */ + , /* D0 */ + + , /* NBL1 */ + , /* NBL0 */ + + , /* BA1 */ + , /* BA0 */ + + , /* A11 */ + , /* A10 */ + , /* A9 */ + , /* A8 */ + , /* A7 */ + , /* A6 */ + , /* A5 */ + , /* A4 */ + , /* A3 */ + , /* A2 */ + , /* A1 */ + , /* A0 */ + + , /* SDNE0 */ + , /* SDNWE */ + , /* SDNRAS */ + , /* SDNCAS */ + , /* SDCKE0 */ + ; /* SDCLK> */ slew-rate = <2>; }; }; ltdc_pins: ltdc@0 { pins { - pinmux = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + pinmux = , /* B0 */ + , /* B4 */ + , /* VSYNC */ + , /* HSYNC */ + , /* CLK */ + , /* R0 */ + , /* R1 */ + , /* R2 */ + , /* R3 */ + , /* R4 */ + , /* R5 */ + , /* R6 */ + , /* R7 */ + , /* G0 */ + , /* G1 */ + , /* G2 */ + , /* G3 */ + , /* G4 */ + , /* B1 */ + , /* B2 */ + , /* B3 */ + , /* G5 */ + , /* G6 */ + , /* G7 */ + , /* B5 */ + , /* B6 */ + , /* B7 */ + ; /* DE */ slew-rate = <2>; }; }; qspi_pins: qspi@0 { pins { - pinmux = , - , - , - , - , - ; + pinmux = , /* CLK */ + , /* BK1_NCS */ + , /* BK1_IO0 */ + , /* BK1_IO1 */ + , /* BK1_IO3 */ + ; /* BK1_IO2 */ slew-rate = <2>; }; }; - usart1_pins_a: usart1@0 { + usart1_pins_b: usart1@1 { u-boot,dm-pre-reloc; pins1 { u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts index d568765170..e3a7bd338d 100644 --- a/arch/arm/dts/stm32f746-disco.dts +++ b/arch/arm/dts/stm32f746-disco.dts @@ -1,10 +1,5 @@ /* - * Copyright 2016 - Michael Kurz - * Copyright 2016 - Vikas MANOCHA - * - * Based on: - * stm32f469-disco.dts from Linux - * Copyright 2016 - Lee Jones + * Copyright 2017 - Vikas MANOCHA * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -47,7 +42,8 @@ /dts-v1/; #include "stm32f746.dtsi" -#include +#include "stm32f746-pinctrl.dtsi" +#include #include / { @@ -55,7 +51,7 @@ compatible = "st,stm32f746-disco", "st,stm32f746"; chosen { - bootargs = "root=/dev/ram rdinit=/linuxrc"; + bootargs = "root=/dev/ram"; stdout-path = "serial0:115200n8"; }; @@ -67,39 +63,69 @@ serial0 = &usart1; }; + usbotg_hs_phy: usb-phy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; + clock-names = "main_clk"; + }; + + /* This turns on vbus for otg fs for host mode (dwc2) */ + vcc5v_otg_fs: vcc5v-otg-fs-regulator { + compatible = "regulator-fixed"; + gpio = <&gpiod 5 0>; + regulator-name = "vcc5_host1"; + regulator-always-on; + }; + + mmc_vcard: mmc_vcard { + compatible = "regulator-fixed"; + regulator-name = "mmc_vcard"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; &clk_hse { clock-frequency = <25000000>; }; -&pinctrl { - usart1_pins_a: usart1@0 { - pins1 { - pinmux = ; - bias-disable; - drive-push-pull; - slew-rate = <2>; - }; - pins2 { - pinmux = ; - bias-disable; - }; - }; -}; - -&usart1 { - pinctrl-0 = <&usart1_pins_a>; +&i2c1 { + pinctrl-0 = <&i2c1_pins_b>; pinctrl-names = "default"; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; status = "okay"; }; -&sdio { +&sdio1 { status = "okay"; + vmmc-supply = <&mmc_vcard>; cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; pinctrl-names = "default", "opendrain"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_pins_od>; + pinctrl-0 = <&sdio_pins_a>; + pinctrl-1 = <&sdio_pins_od_a>; bus-width = <4>; - max-frequency = <25000000>; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_b>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg_fs { + dr_mode = "host"; + pinctrl-0 = <&usbotg_fs_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "host"; + phys = <&usbotg_hs_phy>; + phy-names = "usb2-phy"; + pinctrl-0 = <&usbotg_hs_pins_b>; + pinctrl-names = "default"; + status = "okay"; }; diff --git a/arch/arm/dts/stm32f746-pinctrl.dtsi b/arch/arm/dts/stm32f746-pinctrl.dtsi new file mode 100644 index 0000000000..fcfd2ac723 --- /dev/null +++ b/arch/arm/dts/stm32f746-pinctrl.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include "stm32f7-pinctrl.dtsi" + +&pinctrl{ + compatible = "st,stm32f746-pinctrl"; +}; diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index 7209864266..f48d06a80d 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -1,9 +1,4 @@ /* - * Copyright 2016 - Michael Kurz - * Copyright 2016 - Vikas MANOCHA - * - * Based on: - * stm32f429.dtsi from Linux * Copyright 2015 - Maxime Coquelin * * This file is dual-licensed: you can use it either under the terms @@ -45,8 +40,8 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include "skeleton.dtsi" #include "armv7-m.dtsi" -#include #include #include @@ -57,234 +52,584 @@ compatible = "fixed-clock"; clock-frequency = <0>; }; + + clk-lse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk-lsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000>; + }; + + clk_i2s_ckin: clk-i2s-ckin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <48000000>; + }; }; soc { - usart1: serial@40011000 { - compatible = "st,stm32f7-usart", "st,stm32f7-uart"; - reg = <0x40011000 0x400>; - interrupts = <37>; - clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>; + timer2: timer@40000000 { + compatible = "st,stm32-timer"; + reg = <0x40000000 0x400>; + interrupts = <28>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; status = "disabled"; }; - pwrcfg: power-config@58024800 { - compatible = "syscon"; - reg = <0x40007000 0x400>; + timers2: timers@40000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000000 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@1 { + compatible = "st,stm32-timer-trigger"; + reg = <1>; + status = "disabled"; + }; }; - rcc: rcc@40023810 { - #reset-cells = <1>; - #clock-cells = <2>; - compatible = "st,stm32f746-rcc", "st,stm32-rcc"; - reg = <0x40023800 0x400>; - clocks = <&clk_hse>; - st,syscfg = <&pwrcfg>; + timer3: timer@40000400 { + compatible = "st,stm32-timer"; + reg = <0x40000400 0x400>; + interrupts = <29>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; + status = "disabled"; }; - pinctrl: pin-controller { + timers3: timers@40000400 { #address-cells = <1>; - #size-cells = <1>; - compatible = "st,stm32f746-pinctrl"; - ranges = <0 0x40020000 0x3000>; - pins-are-numbered; - - gpioa: gpio@40020000 { - gpio-controller; - #gpio-cells = <2>; - compatible = "st,stm32-gpio"; - reg = <0x0 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>; - st,bank-name = "GPIOA"; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000400 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; }; - gpiob: gpio@40020400 { - gpio-controller; - #gpio-cells = <2>; - compatible = "st,stm32-gpio"; - reg = <0x400 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>; - st,bank-name = "GPIOB"; + timer@2 { + compatible = "st,stm32-timer-trigger"; + reg = <2>; + status = "disabled"; }; + }; + timer4: timer@40000800 { + compatible = "st,stm32-timer"; + reg = <0x40000800 0x400>; + interrupts = <30>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; + status = "disabled"; + }; - gpioc: gpio@40020800 { - gpio-controller; - #gpio-cells = <2>; - compatible = "st,stm32-gpio"; - reg = <0x800 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>; - st,bank-name = "GPIOC"; + timers4: timers@40000800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000800 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; }; - gpiod: gpio@40020c00 { - gpio-controller; - #gpio-cells = <2>; - compatible = "st,stm32-gpio"; - reg = <0xc00 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>; - st,bank-name = "GPIOD"; + timer@3 { + compatible = "st,stm32-timer-trigger"; + reg = <3>; + status = "disabled"; + }; + }; + + timer5: timer@40000c00 { + compatible = "st,stm32-timer"; + reg = <0x40000c00 0x400>; + interrupts = <50>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; + }; + + timers5: timers@40000c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000C00 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; }; - gpioe: gpio@40021000 { - gpio-controller; - #gpio-cells = <2>; - compatible = "st,stm32-gpio"; - reg = <0x1000 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>; - st,bank-name = "GPIOE"; + timer@4 { + compatible = "st,stm32-timer-trigger"; + reg = <4>; + status = "disabled"; }; + }; + + timer6: timer@40001000 { + compatible = "st,stm32-timer"; + reg = <0x40001000 0x400>; + interrupts = <54>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; + status = "disabled"; + }; + + timers6: timers@40001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001000 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; + clock-names = "int"; + status = "disabled"; - gpiof: gpio@40021400 { - gpio-controller; - #gpio-cells = <2>; - compatible = "st,stm32-gpio"; - reg = <0x1400 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>; - st,bank-name = "GPIOF"; + timer@5 { + compatible = "st,stm32-timer-trigger"; + reg = <5>; + status = "disabled"; }; + }; + + timer7: timer@40001400 { + compatible = "st,stm32-timer"; + reg = <0x40001400 0x400>; + interrupts = <55>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; + status = "disabled"; + }; + + timers7: timers@40001400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001400 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; + clock-names = "int"; + status = "disabled"; - gpiog: gpio@40021800 { - gpio-controller; - #gpio-cells = <2>; - compatible = "st,stm32-gpio"; - reg = <0x1800 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>; - st,bank-name = "GPIOG"; + timer@6 { + compatible = "st,stm32-timer-trigger"; + reg = <6>; + status = "disabled"; }; + }; + + timers12: timers@40001800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001800 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>; + clock-names = "int"; + status = "disabled"; - gpioh: gpio@40021c00 { - gpio-controller; - #gpio-cells = <2>; - compatible = "st,stm32-gpio"; - reg = <0x1c00 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>; - st,bank-name = "GPIOH"; + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; }; - gpioi: gpio@40022000 { - gpio-controller; - #gpio-cells = <2>; - compatible = "st,stm32-gpio"; - reg = <0x2000 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>; - st,bank-name = "GPIOI"; + timer@11 { + compatible = "st,stm32-timer-trigger"; + reg = <11>; + status = "disabled"; }; + }; + + timers13: timers@40001c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001C00 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>; + clock-names = "int"; + status = "disabled"; - gpioj: gpio@40022400 { - gpio-controller; - #gpio-cells = <2>; - compatible = "st,stm32-gpio"; - reg = <0x2400 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>; - st,bank-name = "GPIOJ"; + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; }; + }; - gpiok: gpio@40022800 { - gpio-controller; - #gpio-cells = <2>; - compatible = "st,stm32-gpio"; - reg = <0x2800 0x400>; - clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>; - st,bank-name = "GPIOK"; + timers14: timers@40002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40002000 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; }; + }; + + rtc: rtc@40002800 { + compatible = "st,stm32-rtc"; + reg = <0x40002800 0x400>; + clocks = <&rcc 1 CLK_RTC>; + clock-names = "ck_rtc"; + assigned-clocks = <&rcc 1 CLK_RTC>; + assigned-clock-parents = <&rcc 1 CLK_LSE>; + interrupt-parent = <&exti>; + interrupts = <17 1>; + interrupt-names = "alarm"; + st,syscfg = <&pwrcfg 0x00 0x100>; + status = "disabled"; + }; + + usart2: serial@40004400 { + compatible = "st,stm32f7-uart"; + reg = <0x40004400 0x400>; + interrupts = <38>; + clocks = <&rcc 1 CLK_USART2>; + status = "disabled"; + }; + + usart3: serial@40004800 { + compatible = "st,stm32f7-uart"; + reg = <0x40004800 0x400>; + interrupts = <39>; + clocks = <&rcc 1 CLK_USART3>; + status = "disabled"; + }; + + usart4: serial@40004c00 { + compatible = "st,stm32f7-uart"; + reg = <0x40004c00 0x400>; + interrupts = <52>; + clocks = <&rcc 1 CLK_UART4>; + status = "disabled"; + }; + + usart5: serial@40005000 { + compatible = "st,stm32f7-uart"; + reg = <0x40005000 0x400>; + interrupts = <53>; + clocks = <&rcc 1 CLK_UART5>; + status = "disabled"; + }; + + i2c1: i2c@40005400 { + compatible = "st,stm32f7-i2c"; + reg = <0x40005400 0x400>; + interrupts = <31>, + <32>; + resets = <&rcc STM32F7_APB1_RESET(I2C1)>; + clocks = <&rcc 1 CLK_I2C1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@40005800 { + compatible = "st,stm32f7-i2c"; + reg = <0x40005800 0x400>; + interrupts = <33>, + <34>; + resets = <&rcc STM32F7_APB1_RESET(I2C2)>; + clocks = <&rcc 1 CLK_I2C2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@40005C00 { + compatible = "st,stm32f7-i2c"; + reg = <0x40005C00 0x400>; + interrupts = <72>, + <73>; + resets = <&rcc STM32F7_APB1_RESET(I2C3)>; + clocks = <&rcc 1 CLK_I2C3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@40006000 { + compatible = "st,stm32f7-i2c"; + reg = <0x40006000 0x400>; + interrupts = <95>, + <96>; + resets = <&rcc STM32F7_APB1_RESET(I2C4)>; + clocks = <&rcc 1 CLK_I2C4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + cec: cec@40006c00 { + compatible = "st,stm32-cec"; + reg = <0x40006C00 0x400>; + interrupts = <94>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>; + clock-names = "cec", "hdmi-cec"; + status = "disabled"; + }; + + usart7: serial@40007800 { + compatible = "st,stm32f7-uart"; + reg = <0x40007800 0x400>; + interrupts = <82>; + clocks = <&rcc 1 CLK_UART7>; + status = "disabled"; + }; + + usart8: serial@40007c00 { + compatible = "st,stm32f7-uart"; + reg = <0x40007c00 0x400>; + interrupts = <83>; + clocks = <&rcc 1 CLK_UART8>; + status = "disabled"; + }; + + timers1: timers@40010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40010000 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>; + clock-names = "int"; + status = "disabled"; - sdio_pins: sdio_pins@0 { - pins { - pinmux = , - , - , - , - , - ; - drive-push-pull; - slew-rate = <2>; - }; + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; }; - sdio_pins_od: sdio_pins_od@0 { - pins1 { - pinmux = , - , - , - , - ; - drive-push-pull; - slew-rate = <2>; - }; - - pins2 { - pinmux = ; - drive-open-drain; - slew-rate = <2>; - }; + timer@0 { + compatible = "st,stm32-timer-trigger"; + reg = <0>; + status = "disabled"; }; + }; - sdio_pins_b: sdio_pins_b@0 { - pins { - pinmux = , - , - , - , - , - ; - drive-push-pull; - slew-rate = <2>; - }; + timers8: timers@40010400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40010400 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; }; - sdio_pins_od_b: sdio_pins_od_b@0 { - pins1 { - pinmux = , - , - , - , - ; - drive-push-pull; - slew-rate = <2>; - }; - - pins2 { - pinmux = ; - drive-open-drain; - slew-rate = <2>; - }; + timer@7 { + compatible = "st,stm32-timer-trigger"; + reg = <7>; + status = "disabled"; }; + }; + usart1: serial@40011000 { + compatible = "st,stm32f7-uart"; + reg = <0x40011000 0x400>; + interrupts = <37>; + clocks = <&rcc 1 CLK_USART1>; + status = "disabled"; }; - sdio: sdio@40012c00 { - compatible = "st,stm32f4xx-sdio"; - reg = <0x40012c00 0x400>; - clocks = <&rcc 0 171>; - interrupts = <49>; + + usart6: serial@40011400 { + compatible = "st,stm32f7-uart"; + reg = <0x40011400 0x400>; + interrupts = <71>; + clocks = <&rcc 1 CLK_USART6>; status = "disabled"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_pins_od>; - pinctrl-names = "default", "opendrain"; - max-frequency = <48000000>; }; sdio2: sdio2@40011c00 { - compatible = "st,stm32f4xx-sdio"; + compatible = "arm,pl180", "arm,primecell"; + arm,primecell-periphid = <0x00880180>; reg = <0x40011c00 0x400>; - clocks = <&rcc 0 167>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>; + clock-names = "apb_pclk"; interrupts = <103>; + max-frequency = <48000000>; status = "disabled"; - pinctrl-0 = <&sdio_pins_b>; - pinctrl-1 = <&sdio_pins_od_b>; - pinctrl-names = "default", "opendrain"; + }; + + sdio1: sdio1@40012c00 { + compatible = "arm,pl180", "arm,primecell"; + arm,primecell-periphid = <0x00880180>; + reg = <0x40012c00 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>; + clock-names = "apb_pclk"; + interrupts = <49>; max-frequency = <48000000>; + status = "disabled"; }; - timer5: timer@40000c00 { - compatible = "st,stm32-timer"; - reg = <0x40000c00 0x400>; - interrupts = <50>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; + syscfg: system-config@40013800 { + compatible = "syscon"; + reg = <0x40013800 0x400>; + }; + + exti: interrupt-controller@40013c00 { + compatible = "st,stm32-exti"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x40013C00 0x400>; + interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; + }; + + timers9: timers@40014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40014000 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@8 { + compatible = "st,stm32-timer-trigger"; + reg = <8>; + status = "disabled"; + }; + }; + + timers10: timers@40014400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40014400 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + }; + + timers11: timers@40014800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40014800 0x400>; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + }; + + pwrcfg: power-config@40007000 { + compatible = "syscon"; + reg = <0x40007000 0x400>; + }; + + crc: crc@40023000 { + compatible = "st,stm32f7-crc"; + reg = <0x40023000 0x400>; + clocks = <&rcc 0 12>; + status = "disabled"; + }; + + rcc: rcc@40023800 { + #reset-cells = <1>; + #clock-cells = <2>; + compatible = "st,stm32f746-rcc", "st,stm32-rcc"; + reg = <0x40023800 0x400>; + clocks = <&clk_hse>, <&clk_i2s_ckin>; + st,syscfg = <&pwrcfg>; + assigned-clocks = <&rcc 1 CLK_HSE_RTC>; + assigned-clock-rates = <1000000>; + }; + + dma1: dma@40026000 { + compatible = "st,stm32-dma"; + reg = <0x40026000 0x400>; + interrupts = <11>, + <12>, + <13>, + <14>, + <15>, + <16>, + <17>, + <47>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>; + #dma-cells = <4>; + status = "disabled"; + }; + + dma2: dma@40026400 { + compatible = "st,stm32-dma"; + reg = <0x40026400 0x400>; + interrupts = <56>, + <57>, + <58>, + <59>, + <60>, + <68>, + <69>, + <70>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>; + #dma-cells = <4>; + st,mem2mem; + status = "disabled"; + }; + + usbotg_hs: usb@40040000 { + compatible = "st,stm32f7-hsotg"; + reg = <0x40040000 0x40000>; + interrupts = <77>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>; + clock-names = "otg"; + g-rx-fifo-size = <256>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <128 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + usbotg_fs: usb@50000000 { + compatible = "st,stm32f4x9-fsotg"; + reg = <0x50000000 0x40000>; + interrupts = <67>; + clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>; + clock-names = "otg"; + status = "disabled"; }; }; }; &systick { + clocks = <&rcc 1 0>; status = "okay"; }; diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi b/arch/arm/dts/stm32f769-disco-u-boot.dtsi index 217c937b23..e9e43cba10 100644 --- a/arch/arm/dts/stm32f769-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi @@ -61,94 +61,94 @@ &pinctrl { ethernet_mii: mii@0 { pins { - pinmux = , - , - , - , - , - , - , - , - ; + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_TX_EN */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RMII_REF_CLK */ + , /* ETH_RMII_CRS_DV */ + , /* ETH_RMII_RXD0 */ + ; /* ETH_RMII_RXD1 */ slew-rate = <2>; }; }; fmc_pins: fmc@0 { pins { - pinmux = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , + pinmux = , /* D31 */ + , /* D30 */ + , /* D29 */ + , /* D28 */ + , /* D27 */ + , /* D26 */ + , /* D25 */ + , /* D24 */ + , /* D23 */ + , /* D22 */ + , /* D21 */ + , /* D20 */ + , /* D19 */ + , /* D18 */ + , /* D17 */ + , /* D16 */ - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , + , /* D15 */ + , /* D14 */ + , /* D13 */ + , /* D12 */ + , /* D11 */ + , /* D10 */ + , /* D9 */ + , /* D8 */ + , /* D7 */ + , /* D6 */ + , /* D5 */ + , /* D4 */ + , /* D3 */ + , /* D2 */ + , /* D1 */ + , /* D0 */ - , - , - , - , + , /* NBL3 */ + , /* NBL2 */ + , /* NBL1 */ + , /* NBL0 */ - , - , + , /* BA1 */ + , /* BA0 */ - , - , - , - , - , - , - , - , - , - , - , - , + , /* A11 */ + , /* A10 */ + , /* A9 */ + , /* A8 */ + , /* A7 */ + , /* A6 */ + , /* A5 */ + , /* A4 */ + , /* A3 */ + , /* A2 */ + , /* A1 */ + , /* A0 */ - , - , - , - , - , - ; + , /* SDNE0 */ + , /* SDNWE */ + , /* SDNRAS */ + , /* SDNCAS */ + , /* SDCKE0 */ + ; /* SDCLK> */ slew-rate = <2>; }; }; qspi_pins: qspi@0 { pins { - pinmux = , - , - , - , - , - ; + pinmux = , /* CLK */ + , /* BK1_NCS */ + , /* BK1_IO0 */ + , /* BK1_IO1 */ + , /* BK1_IO3 */ + ; /* BK1_IO2 */ slew-rate = <2>; }; }; diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts index 046bb225a6..483d896e2b 100644 --- a/arch/arm/dts/stm32f769-disco.dts +++ b/arch/arm/dts/stm32f769-disco.dts @@ -1,5 +1,5 @@ /* - * Copyright 2016 - Vikas Manocha + * Copyright 2017 - Vikas MANOCHA * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,14 +42,16 @@ /dts-v1/; #include "stm32f746.dtsi" -#include +#include "stm32f769-pinctrl.dtsi" +#include #include / { model = "STMicroelectronics STM32F769-DISCO board"; - compatible = "st,stm32f769-disco", "st,stm32f7"; + compatible = "st,stm32f769-disco", "st,stm32f769"; chosen { + bootargs = "root=/dev/ram"; stdout-path = "serial0:115200n8"; }; @@ -60,40 +62,89 @@ aliases { serial0 = &usart1; }; -}; - -&clk_hse { - clock-frequency = <25000000>; -}; -&pinctrl { - usart1_pins_a: usart1@0 { - pins1 { - pinmux = ; - bias-disable; - drive-push-pull; - slew-rate = <2>; + leds { + compatible = "gpio-leds"; + green { + gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; }; - pins2 { - pinmux = ; - bias-disable; + red { + gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>; }; }; + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + button@0 { + label = "User"; + linux,code = ; + gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; + }; + }; + + usbotg_hs_phy: usb-phy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>; + clock-names = "main_clk"; + }; + + mmc_vcard: mmc_vcard { + compatible = "regulator-fixed"; + regulator-name = "mmc_vcard"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; -&usart1 { - pinctrl-0 = <&usart1_pins_a>; +&cec { + pinctrl-0 = <&cec_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins_b>; pinctrl-names = "default"; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; +}; + +&rtc { status = "okay"; }; &sdio2 { status = "okay"; + vmmc-supply = <&mmc_vcard>; cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>; + broken-cd; pinctrl-names = "default", "opendrain"; pinctrl-0 = <&sdio_pins_b>; pinctrl-1 = <&sdio_pins_od_b>; bus-width = <4>; - max-frequency = <25000000>; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "otg"; + phys = <&usbotg_hs_phy>; + phy-names = "usb2-phy"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + status = "okay"; }; diff --git a/arch/arm/dts/stm32f769-pinctrl.dtsi b/arch/arm/dts/stm32f769-pinctrl.dtsi new file mode 100644 index 0000000000..31005dd992 --- /dev/null +++ b/arch/arm/dts/stm32f769-pinctrl.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2017 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +#include "stm32f7-pinctrl.dtsi" + +&pinctrl{ + compatible = "st,stm32f769-pinctrl"; +}; -- cgit From 105630314887e63e95590ec4db07ed3b00e77aa1 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 6 Dec 2018 11:59:42 +0100 Subject: ARM: dts: Migrate U-boot nodes to U-boot DT files for stm32h7 In order to prepare and ease future DT synchronization with kernel DT, migrate all U-boot specific nodes/properties/addons to U-boot DT files. As sdmmc is not yet supported on kernel side, sdmmc nodes are located in eval-u-boot and disco-u-boot DT files. Signed-off-by: Patrice Chotard --- arch/arm/dts/stm32h7-u-boot.dtsi | 167 ++++++++++++++++++++++++++++-- arch/arm/dts/stm32h743-pinctrl.dtsi | 97 +---------------- arch/arm/dts/stm32h743.dtsi | 18 ---- arch/arm/dts/stm32h743i-disco-u-boot.dtsi | 11 ++ arch/arm/dts/stm32h743i-disco.dts | 39 ------- arch/arm/dts/stm32h743i-eval-u-boot.dtsi | 12 +++ arch/arm/dts/stm32h743i-eval.dts | 40 ------- 7 files changed, 183 insertions(+), 201 deletions(-) create mode 100644 arch/arm/dts/stm32h743i-disco-u-boot.dtsi create mode 100644 arch/arm/dts/stm32h743i-eval-u-boot.dtsi (limited to 'arch') diff --git a/arch/arm/dts/stm32h7-u-boot.dtsi b/arch/arm/dts/stm32h7-u-boot.dtsi index 2525035da1..6e5b805a97 100644 --- a/arch/arm/dts/stm32h7-u-boot.dtsi +++ b/arch/arm/dts/stm32h7-u-boot.dtsi @@ -1,13 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include + /{ clocks { u-boot,dm-pre-reloc; }; + aliases { + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + mmc0 = &sdmmc1; + }; + soc { u-boot,dm-pre-reloc; pin-controller { u-boot,dm-pre-reloc; }; + + fmc: fmc@52004000 { + compatible = "st,stm32h7-fmc"; + reg = <0x52004000 0x1000>; + clocks = <&rcc FMC_CK>; + + pinctrl-0 = <&fmc_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* + * Memory configuration from sdram datasheet IS42S32800G-6BLI + * firsct bank is bank@0 + * second bank is bank@1 + */ + bank1: bank@1 { + st,sdram-control = /bits/ 8 ; + st,sdram-timing = /bits/ 8 ; + st,sdram-refcount = <1539>; + }; + }; + + sdmmc1: sdmmc@52007000 { + compatible = "st,stm32-sdmmc2"; + reg = <0x52007000 0x1000>; + interrupts = <49>; + clocks = <&rcc SDMMC1_CK>; + resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>; + st,idma = <1>; + cap-sd-highspeed; + cap-mmc-highspeed; + }; }; }; @@ -15,21 +68,14 @@ u-boot,dm-pre-reloc; }; -&clk_lse { - u-boot,dm-pre-reloc; -}; - &clk_i2s { u-boot,dm-pre-reloc; }; -&pwrcfg { +&clk_lse { u-boot,dm-pre-reloc; }; -&rcc { - u-boot,dm-pre-reloc; -}; &fmc { u-boot,dm-pre-reloc; @@ -86,3 +132,108 @@ &gpiok { u-boot,dm-pre-reloc; }; + +&pinctrl { + fmc_pins: fmc@0 { + pins { + pinmux = , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + ; + + slew-rate = <3>; + }; + }; + + pinctrl_sdmmc1_level_shifter: sdmmc0_ls@0 { + pins { + pinmux = , + , + , + ; + drive-push-pull; + slew-rate = <3>; + }; + }; + + sdmmc1_pins: sdmmc@0 { + pins { + pinmux = , + , + , + , + , + ; + + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + }; +}; + +&pwrcfg { + u-boot,dm-pre-reloc; +}; + +&rcc { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/stm32h743-pinctrl.dtsi b/arch/arm/dts/stm32h743-pinctrl.dtsi index e4f4aa579b..85b96be99b 100644 --- a/arch/arm/dts/stm32h743-pinctrl.dtsi +++ b/arch/arm/dts/stm32h743-pinctrl.dtsi @@ -44,7 +44,7 @@ / { soc { - pin-controller { + pinctrl: pin-controller { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32h743-pinctrl"; @@ -175,101 +175,6 @@ bias-disable; }; }; - - fmc_pins: fmc@0 { - pins { - pinmux = , - , - , - , - , - , - , - - , - , - , - , - , - , - , - , - , - , - , - - , - , - , - , - , - , - , - , - , - , - , - - , - , - , - , - , - , - , - - , - , - , - , - , - , - , - , - , - , - , - - , - , - , - , - , - , - , - , - , - ; - - slew-rate = <3>; - }; - }; - - sdmmc1_pins: sdmmc@0 { - pins { - pinmux = , - , - , - , - , - ; - - slew-rate = <3>; - drive-push-pull; - bias-disable; - }; - }; - - pinctrl_sdmmc1_level_shifter: sdmmc0_ls@0 { - pins { - pinmux = , - , - , - ; - drive-push-pull; - slew-rate = <3>; - }; - }; }; }; }; diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi index d5b8d879ee..23e185cf11 100644 --- a/arch/arm/dts/stm32h743.dtsi +++ b/arch/arm/dts/stm32h743.dtsi @@ -104,12 +104,6 @@ reg = <0x58024800 0x400>; }; - fmc: fmc@52004000 { - compatible = "st,stm32h7-fmc"; - reg = <0x52004000 0x1000>; - clocks = <&rcc FMC_CK>; - }; - clk_hsi: clk-hsi { #clock-cells = <0>; compatible = "fixed-clock"; @@ -121,18 +115,6 @@ compatible = "fixed-clock"; clock-frequency = <4000000>; }; - - sdmmc1: sdmmc@52007000 { - compatible = "st,stm32-sdmmc2"; - reg = <0x52007000 0x1000>; - interrupts = <49>; - clocks = <&rcc SDMMC1_CK>; - resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>; - st,idma = <1>; - cap-sd-highspeed; - cap-mmc-highspeed; - status = "disabled"; - }; }; }; diff --git a/arch/arm/dts/stm32h743i-disco-u-boot.dtsi b/arch/arm/dts/stm32h743i-disco-u-boot.dtsi new file mode 100644 index 0000000000..2d6b41bfb9 --- /dev/null +++ b/arch/arm/dts/stm32h743i-disco-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include + +&sdmmc1 { + status = "okay"; + pinctrl-0 = <&sdmmc1_pins>; + pinctrl-names = "default"; + bus-width = <4>; + cd-gpios = <&gpioi 8 1>; +}; diff --git a/arch/arm/dts/stm32h743i-disco.dts b/arch/arm/dts/stm32h743i-disco.dts index 917a859a09..1237a814a4 100644 --- a/arch/arm/dts/stm32h743i-disco.dts +++ b/arch/arm/dts/stm32h743i-disco.dts @@ -43,7 +43,6 @@ /dts-v1/; #include "stm32h743.dtsi" #include "stm32h743-pinctrl.dtsi" -#include / { model = "STMicroelectronics STM32H743i-Discovery board"; @@ -60,18 +59,6 @@ aliases { serial0 = &usart2; - mmc0 = &sdmmc1; - gpio0 = &gpioa; - gpio1 = &gpiob; - gpio2 = &gpioc; - gpio3 = &gpiod; - gpio4 = &gpioe; - gpio5 = &gpiof; - gpio6 = &gpiog; - gpio7 = &gpioh; - gpio8 = &gpioi; - gpio9 = &gpioj; - gpio10 = &gpiok; }; }; @@ -81,29 +68,3 @@ status = "okay"; }; -&fmc { - pinctrl-0 = <&fmc_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* - * Memory configuration from sdram datasheet IS42S32800G-6BLI - * firsct bank is bank@0 - * second bank is bank@1 - */ - bank1: bank@1 { - st,sdram-control = /bits/ 8 ; - st,sdram-timing = /bits/ 8 ; - st,sdram-refcount = <1539>; - }; -}; - -&sdmmc1 { - status = "okay"; - pinctrl-0 = <&sdmmc1_pins>; - pinctrl-names = "default"; - bus-width = <4>; - cd-gpios = <&gpioi 8 1>; -}; diff --git a/arch/arm/dts/stm32h743i-eval-u-boot.dtsi b/arch/arm/dts/stm32h743i-eval-u-boot.dtsi new file mode 100644 index 0000000000..220a2d706c --- /dev/null +++ b/arch/arm/dts/stm32h743i-eval-u-boot.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include + +&sdmmc1 { + status = "okay"; + pinctrl-0 = <&sdmmc1_pins>, + <&pinctrl_sdmmc1_level_shifter>; + pinctrl-names = "default"; + bus-width = <4>; + st,dirpol; +}; diff --git a/arch/arm/dts/stm32h743i-eval.dts b/arch/arm/dts/stm32h743i-eval.dts index 28c876be27..c8b6dfbdd3 100644 --- a/arch/arm/dts/stm32h743i-eval.dts +++ b/arch/arm/dts/stm32h743i-eval.dts @@ -43,7 +43,6 @@ /dts-v1/; #include "stm32h743.dtsi" #include "stm32h743-pinctrl.dtsi" -#include / { model = "STMicroelectronics STM32H743i-EVAL board"; @@ -60,17 +59,6 @@ aliases { serial0 = &usart1; - gpio0 = &gpioa; - gpio1 = &gpiob; - gpio2 = &gpioc; - gpio3 = &gpiod; - gpio4 = &gpioe; - gpio5 = &gpiof; - gpio6 = &gpiog; - gpio7 = &gpioh; - gpio8 = &gpioi; - gpio9 = &gpioj; - gpio10 = &gpiok; }; }; @@ -79,31 +67,3 @@ pinctrl-names = "default"; status = "okay"; }; - -&fmc { - pinctrl-0 = <&fmc_pins>; - pinctrl-names = "default"; - status = "okay"; - - /* - * Memory configuration from sdram datasheet IS42S32800G-6BLI - * firsct bank is bank@0 - * second bank is bank@1 - */ - bank2: bank@1 { - st,sdram-control = /bits/ 8 ; - st,sdram-timing = /bits/ 8 ; - st,sdram-refcount = <1539>; - }; -}; - -&sdmmc1 { - status = "okay"; - pinctrl-0 = <&sdmmc1_pins>, - <&pinctrl_sdmmc1_level_shifter>; - pinctrl-names = "default"; - bus-width = <4>; - st,dirpol; -}; -- cgit From 13ba6d0e6f8bd69662d8cddd20b4485246757d16 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 6 Dec 2018 11:53:39 +0100 Subject: ARM: dts: stm32: Sync DT with v4.20 kernel for stm32h7 Synchronize stm32h7 device tree with kernel v4.20. U-boot DT files and pinctrl bindings are updated, useless nodes are removed and gpio compatible added. Signed-off-by: Patrice Chotard --- arch/arm/dts/stm32h7-u-boot.dtsi | 188 ++++++++------- arch/arm/dts/stm32h743-pinctrl.dtsi | 75 ++++-- arch/arm/dts/stm32h743.dtsi | 452 +++++++++++++++++++++++++++++++++--- arch/arm/dts/stm32h743i-disco.dts | 5 +- arch/arm/dts/stm32h743i-eval.dts | 51 ++++ 5 files changed, 639 insertions(+), 132 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/stm32h7-u-boot.dtsi b/arch/arm/dts/stm32h7-u-boot.dtsi index 6e5b805a97..99fa0e673a 100644 --- a/arch/arm/dts/stm32h7-u-boot.dtsi +++ b/arch/arm/dts/stm32h7-u-boot.dtsi @@ -43,10 +43,21 @@ * second bank is bank@1 */ bank1: bank@1 { - st,sdram-control = /bits/ 8 ; - st,sdram-timing = /bits/ 8 ; + st,sdram-control = /bits/ 8 ; + st,sdram-timing = /bits/ 8 ; st,sdram-refcount = <1539>; }; }; @@ -81,134 +92,137 @@ u-boot,dm-pre-reloc; }; -&clk_hsi { - u-boot,dm-pre-reloc; -}; - -&clk_csi { - u-boot,dm-pre-reloc; -}; - &gpioa { u-boot,dm-pre-reloc; + compatible = "st,stm32-gpio"; }; &gpiob { u-boot,dm-pre-reloc; + compatible = "st,stm32-gpio"; }; &gpioc { u-boot,dm-pre-reloc; + compatible = "st,stm32-gpio"; }; &gpiod { u-boot,dm-pre-reloc; + compatible = "st,stm32-gpio"; }; &gpioe { u-boot,dm-pre-reloc; + compatible = "st,stm32-gpio"; }; &gpiof { u-boot,dm-pre-reloc; + compatible = "st,stm32-gpio"; }; &gpiog { u-boot,dm-pre-reloc; + compatible = "st,stm32-gpio"; }; &gpioh { u-boot,dm-pre-reloc; + compatible = "st,stm32-gpio"; }; &gpioi { u-boot,dm-pre-reloc; + compatible = "st,stm32-gpio"; }; &gpioj { u-boot,dm-pre-reloc; + compatible = "st,stm32-gpio"; }; &gpiok { u-boot,dm-pre-reloc; + compatible = "st,stm32-gpio"; }; &pinctrl { fmc_pins: fmc@0 { - pins { - pinmux = , - , - , - , - , - , - , - - , - , - , - , - , - , - , - , - , - , - , - - , - , - , - , - , - , - , - , - , - , - , - - , - , - , - , - , - , - , - - , - , - , - , - , - , - , - , - , - , - , - - , - , - , - , - , - , - , - , - , - ; - - slew-rate = <3>; + pins { + pinmux = , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + , + , + + , + , + , + , + , + , + , + , + , + ; + + slew-rate = <3>; }; }; pinctrl_sdmmc1_level_shifter: sdmmc0_ls@0 { pins { - pinmux = , - , - , - ; + pinmux = , + , + , + ; drive-push-pull; slew-rate = <3>; }; @@ -216,12 +230,12 @@ sdmmc1_pins: sdmmc@0 { pins { - pinmux = , - , - , - , - , - ; + pinmux = , + , + , + , + , + ; slew-rate = <3>; drive-push-pull; diff --git a/arch/arm/dts/stm32h743-pinctrl.dtsi b/arch/arm/dts/stm32h743-pinctrl.dtsi index 85b96be99b..c823541a0d 100644 --- a/arch/arm/dts/stm32h743-pinctrl.dtsi +++ b/arch/arm/dts/stm32h743-pinctrl.dtsi @@ -40,7 +40,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include +#include / { soc { @@ -49,132 +49,175 @@ #size-cells = <1>; compatible = "st,stm32h743-pinctrl"; ranges = <0 0x58020000 0x3000>; + interrupt-parent = <&exti>; + st,syscfg = <&syscfg 0x8>; pins-are-numbered; gpioa: gpio@58020000 { gpio-controller; #gpio-cells = <2>; - compatible = "st,stm32-gpio"; reg = <0x0 0x400>; clocks = <&rcc GPIOA_CK>; st,bank-name = "GPIOA"; + interrupt-controller; + #interrupt-cells = <2>; }; gpiob: gpio@58020400 { gpio-controller; #gpio-cells = <2>; - compatible = "st,stm32-gpio"; reg = <0x400 0x400>; clocks = <&rcc GPIOB_CK>; st,bank-name = "GPIOB"; + interrupt-controller; + #interrupt-cells = <2>; }; gpioc: gpio@58020800 { gpio-controller; #gpio-cells = <2>; - compatible = "st,stm32-gpio"; reg = <0x800 0x400>; clocks = <&rcc GPIOC_CK>; st,bank-name = "GPIOC"; + interrupt-controller; + #interrupt-cells = <2>; }; gpiod: gpio@58020c00 { gpio-controller; #gpio-cells = <2>; - compatible = "st,stm32-gpio"; reg = <0xc00 0x400>; clocks = <&rcc GPIOD_CK>; st,bank-name = "GPIOD"; + interrupt-controller; + #interrupt-cells = <2>; }; gpioe: gpio@58021000 { gpio-controller; #gpio-cells = <2>; - compatible = "st,stm32-gpio"; reg = <0x1000 0x400>; clocks = <&rcc GPIOE_CK>; st,bank-name = "GPIOE"; + interrupt-controller; + #interrupt-cells = <2>; }; gpiof: gpio@58021400 { gpio-controller; #gpio-cells = <2>; - compatible = "st,stm32-gpio"; reg = <0x1400 0x400>; clocks = <&rcc GPIOF_CK>; st,bank-name = "GPIOF"; + interrupt-controller; + #interrupt-cells = <2>; }; gpiog: gpio@58021800 { gpio-controller; #gpio-cells = <2>; - compatible = "st,stm32-gpio"; reg = <0x1800 0x400>; clocks = <&rcc GPIOG_CK>; st,bank-name = "GPIOG"; + interrupt-controller; + #interrupt-cells = <2>; }; gpioh: gpio@58021c00 { gpio-controller; #gpio-cells = <2>; - compatible = "st,stm32-gpio"; reg = <0x1c00 0x400>; clocks = <&rcc GPIOH_CK>; st,bank-name = "GPIOH"; + interrupt-controller; + #interrupt-cells = <2>; }; gpioi: gpio@58022000 { gpio-controller; #gpio-cells = <2>; - compatible = "st,stm32-gpio"; reg = <0x2000 0x400>; clocks = <&rcc GPIOI_CK>; st,bank-name = "GPIOI"; + interrupt-controller; + #interrupt-cells = <2>; }; gpioj: gpio@58022400 { gpio-controller; #gpio-cells = <2>; - compatible = "st,stm32-gpio"; reg = <0x2400 0x400>; clocks = <&rcc GPIOJ_CK>; st,bank-name = "GPIOJ"; + interrupt-controller; + #interrupt-cells = <2>; }; gpiok: gpio@58022800 { gpio-controller; #gpio-cells = <2>; - compatible = "st,stm32-gpio"; reg = <0x2800 0x400>; clocks = <&rcc GPIOK_CK>; st,bank-name = "GPIOK"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + i2c1_pins_a: i2c1@0 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; }; usart1_pins: usart1@0 { pins1 { - pinmux = ; + pinmux = ; /* USART1_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = ; + pinmux = ; /* USART1_RX */ bias-disable; }; }; usart2_pins: usart2@0 { pins1 { - pinmux = ; + pinmux = ; /* USART2_TX */ bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = ; + pinmux = ; /* USART2_RX */ bias-disable; }; }; + + usbotg_hs_pins_a: usbotg-hs@0 { + pins { + pinmux = , /* ULPI_NXT */ + , /* ULPI_DIR> */ + , /* ULPI_STP> */ + , /* ULPI_CK> */ + , /* ULPI_D0> */ + , /* ULPI_D1> */ + , /* ULPI_D2> */ + , /* ULPI_D3> */ + , /* ULPI_D4> */ + , /* ULPI_D5> */ + , /* ULPI_D6> */ + ; /* ULPI_D7> */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; }; }; }; diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi index 23e185cf11..cbdd69ca9e 100644 --- a/arch/arm/dts/stm32h743.dtsi +++ b/arch/arm/dts/stm32h743.dtsi @@ -44,13 +44,14 @@ #include "armv7-m.dtsi" #include #include +#include / { clocks { clk_hse: clk-hse { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <25000000>; + clock-frequency = <0>; }; clk_lse: clk-lse { @@ -67,36 +68,421 @@ }; soc { - rcc: rcc@58024400 { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "st,stm32h743-rcc", "st,stm32-rcc"; - reg = <0x58024400 0x400>; - clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>, <&clk_hsi>, <&clk_csi>; - st,syscfg = <&pwrcfg>; + timer5: timer@40000c00 { + compatible = "st,stm32-timer"; + reg = <0x40000c00 0x400>; + interrupts = <50>; + clocks = <&rcc TIM5_CK>; }; - usart1: serial@40011000 { - compatible = "st,stm32h7-uart"; - reg = <0x40011000 0x400>; - interrupts = <37>; + lptimer1: timer@40002400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x40002400 0x400>; + clocks = <&rcc LPTIM1_CK>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@0 { + compatible = "st,stm32-lptimer-trigger"; + reg = <0>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + }; + + spi2: spi@40003800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x40003800 0x400>; + interrupts = <36>; + clocks = <&rcc SPI2_CK>; + status = "disabled"; + + }; + + spi3: spi@40003c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x40003c00 0x400>; + interrupts = <51>; + clocks = <&rcc SPI3_CK>; status = "disabled"; - clocks = <&rcc USART1_CK>; }; usart2: serial@40004400 { - compatible = "st,stm32h7-uart"; + compatible = "st,stm32f7-uart"; reg = <0x40004400 0x400>; interrupts = <38>; status = "disabled"; clocks = <&rcc USART2_CK>; }; - timer5: timer@40000c00 { - compatible = "st,stm32-timer"; - reg = <0x40000c00 0x400>; - interrupts = <50>; - clocks = <&rcc TIM5_CK>; + i2c1: i2c@40005400 { + compatible = "st,stm32f7-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40005400 0x400>; + interrupts = <31>, + <32>; + resets = <&rcc STM32H7_APB1L_RESET(I2C1)>; + clocks = <&rcc I2C1_CK>; + status = "disabled"; + }; + + i2c2: i2c@40005800 { + compatible = "st,stm32f7-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40005800 0x400>; + interrupts = <33>, + <34>; + resets = <&rcc STM32H7_APB1L_RESET(I2C2)>; + clocks = <&rcc I2C2_CK>; + status = "disabled"; + }; + + i2c3: i2c@40005C00 { + compatible = "st,stm32f7-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40005C00 0x400>; + interrupts = <72>, + <73>; + resets = <&rcc STM32H7_APB1L_RESET(I2C3)>; + clocks = <&rcc I2C3_CK>; + status = "disabled"; + }; + + dac: dac@40007400 { + compatible = "st,stm32h7-dac-core"; + reg = <0x40007400 0x400>; + clocks = <&rcc DAC12_CK>; + clock-names = "pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + dac1: dac@1 { + compatible = "st,stm32-dac"; + #io-channels-cells = <1>; + reg = <1>; + status = "disabled"; + }; + + dac2: dac@2 { + compatible = "st,stm32-dac"; + #io-channels-cells = <1>; + reg = <2>; + status = "disabled"; + }; + }; + + usart1: serial@40011000 { + compatible = "st,stm32f7-uart"; + reg = <0x40011000 0x400>; + interrupts = <37>; + status = "disabled"; + clocks = <&rcc USART1_CK>; + }; + + spi1: spi@40013000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x40013000 0x400>; + interrupts = <35>; + clocks = <&rcc SPI1_CK>; + status = "disabled"; + }; + + spi4: spi@40013400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x40013400 0x400>; + interrupts = <84>; + clocks = <&rcc SPI4_CK>; + status = "disabled"; + }; + + spi5: spi@40015000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x40015000 0x400>; + interrupts = <85>; + clocks = <&rcc SPI5_CK>; + status = "disabled"; + }; + + dma1: dma@40020000 { + compatible = "st,stm32-dma"; + reg = <0x40020000 0x400>; + interrupts = <11>, + <12>, + <13>, + <14>, + <15>, + <16>, + <17>, + <47>; + clocks = <&rcc DMA1_CK>; + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; + status = "disabled"; + }; + + dma2: dma@40020400 { + compatible = "st,stm32-dma"; + reg = <0x40020400 0x400>; + interrupts = <56>, + <57>, + <58>, + <59>, + <60>, + <68>, + <69>, + <70>; + clocks = <&rcc DMA2_CK>; + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; + status = "disabled"; + }; + + dmamux1: dma-router@40020800 { + compatible = "st,stm32h7-dmamux"; + reg = <0x40020800 0x1c>; + #dma-cells = <3>; + dma-channels = <16>; + dma-requests = <128>; + dma-masters = <&dma1 &dma2>; + clocks = <&rcc DMA1_CK>; + }; + + adc_12: adc@40022000 { + compatible = "st,stm32h7-adc-core"; + reg = <0x40022000 0x400>; + interrupts = <18>; + clocks = <&rcc ADC12_CK>; + clock-names = "bus"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc1: adc@0 { + compatible = "st,stm32h7-adc"; + #io-channel-cells = <1>; + reg = <0x0>; + interrupt-parent = <&adc_12>; + interrupts = <0>; + status = "disabled"; + }; + + adc2: adc@100 { + compatible = "st,stm32h7-adc"; + #io-channel-cells = <1>; + reg = <0x100>; + interrupt-parent = <&adc_12>; + interrupts = <1>; + status = "disabled"; + }; + }; + + usbotg_hs: usb@40040000 { + compatible = "st,stm32f7-hsotg"; + reg = <0x40040000 0x40000>; + interrupts = <77>; + clocks = <&rcc USB1OTG_CK>; + clock-names = "otg"; + g-rx-fifo-size = <256>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <128 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + usbotg_fs: usb@40080000 { + compatible = "st,stm32f4x9-fsotg"; + reg = <0x40080000 0x40000>; + interrupts = <101>; + clocks = <&rcc USB2OTG_CK>; + clock-names = "otg"; + status = "disabled"; + }; + + mdma1: dma@52000000 { + compatible = "st,stm32h7-mdma"; + reg = <0x52000000 0x1000>; + interrupts = <122>; + clocks = <&rcc MDMA_CK>; + #dma-cells = <5>; + dma-channels = <16>; + dma-requests = <32>; + }; + + exti: interrupt-controller@58000000 { + compatible = "st,stm32h7-exti"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x58000000 0x400>; + interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>; + }; + + syscfg: system-config@58000400 { + compatible = "syscon"; + reg = <0x58000400 0x400>; + }; + + spi6: spi@58001400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32h7-spi"; + reg = <0x58001400 0x400>; + interrupts = <86>; + clocks = <&rcc SPI6_CK>; + status = "disabled"; + }; + + i2c4: i2c@58001C00 { + compatible = "st,stm32f7-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x58001C00 0x400>; + interrupts = <95>, + <96>; + resets = <&rcc STM32H7_APB4_RESET(I2C4)>; + clocks = <&rcc I2C4_CK>; + status = "disabled"; + }; + + lptimer2: timer@58002400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x58002400 0x400>; + clocks = <&rcc LPTIM2_CK>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@1 { + compatible = "st,stm32-lptimer-trigger"; + reg = <1>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + }; + + lptimer3: timer@58002800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x58002800 0x400>; + clocks = <&rcc LPTIM3_CK>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@2 { + compatible = "st,stm32-lptimer-trigger"; + reg = <2>; + status = "disabled"; + }; + }; + + lptimer4: timer@58002c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x58002c00 0x400>; + clocks = <&rcc LPTIM4_CK>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + lptimer5: timer@58003000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x58003000 0x400>; + clocks = <&rcc LPTIM5_CK>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + vrefbuf: regulator@58003c00 { + compatible = "st,stm32-vrefbuf"; + reg = <0x58003C00 0x8>; + clocks = <&rcc VREF_CK>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2500000>; + status = "disabled"; + }; + + rtc: rtc@58004000 { + compatible = "st,stm32h7-rtc"; + reg = <0x58004000 0x400>; + clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>; + clock-names = "pclk", "rtc_ck"; + assigned-clocks = <&rcc RTC_CK>; + assigned-clock-parents = <&rcc LSE_CK>; + interrupt-parent = <&exti>; + interrupts = <17 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "alarm"; + st,syscfg = <&pwrcfg 0x00 0x100>; + status = "disabled"; + }; + + rcc: reset-clock-controller@58024400 { + compatible = "st,stm32h743-rcc", "st,stm32-rcc"; + reg = <0x58024400 0x400>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>; + st,syscfg = <&pwrcfg>; }; pwrcfg: power-config@58024800 { @@ -104,16 +490,26 @@ reg = <0x58024800 0x400>; }; - clk_hsi: clk-hsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <64000000>; - }; + adc_3: adc@58026000 { + compatible = "st,stm32h7-adc-core"; + reg = <0x58026000 0x400>; + interrupts = <127>; + clocks = <&rcc ADC3_CK>; + clock-names = "bus"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; - clk_csi: clk-csi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <4000000>; + adc3: adc@0 { + compatible = "st,stm32h7-adc"; + #io-channel-cells = <1>; + reg = <0x0>; + interrupt-parent = <&adc_3>; + interrupts = <0>; + status = "disabled"; + }; }; }; }; diff --git a/arch/arm/dts/stm32h743i-disco.dts b/arch/arm/dts/stm32h743i-disco.dts index 1237a814a4..45e088c557 100644 --- a/arch/arm/dts/stm32h743i-disco.dts +++ b/arch/arm/dts/stm32h743i-disco.dts @@ -62,9 +62,12 @@ }; }; +&clk_hse { + clock-frequency = <25000000>; +}; + &usart2 { pinctrl-0 = <&usart2_pins>; pinctrl-names = "default"; status = "okay"; }; - diff --git a/arch/arm/dts/stm32h743i-eval.dts b/arch/arm/dts/stm32h743i-eval.dts index c8b6dfbdd3..3f8e0c4a99 100644 --- a/arch/arm/dts/stm32h743i-eval.dts +++ b/arch/arm/dts/stm32h743i-eval.dts @@ -60,6 +60,48 @@ aliases { serial0 = &usart1; }; + + vdda: regulator-vdda { + compatible = "regulator-fixed"; + regulator-name = "vdda"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + usbotg_hs_phy: usb-phy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + clocks = <&rcc USB1ULPI_CK>; + clock-names = "main_clk"; + }; + +}; + +&adc_12 { + vref-supply = <&vdda>; + status = "okay"; + adc1: adc@0 { + /* potentiometer */ + st,adc-channels = <0>; + status = "okay"; + }; +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-names = "default"; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; +}; + +&rtc { + status = "okay"; }; &usart1 { @@ -67,3 +109,12 @@ pinctrl-names = "default"; status = "okay"; }; + +&usbotg_hs { + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phys = <&usbotg_hs_phy>; + phy-names = "usb2-phy"; + dr_mode = "otg"; + status = "okay"; +}; -- cgit From 60121266c900f694b8750504a2edce0bac4b1d7d Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 18 Feb 2019 23:19:45 +0100 Subject: ARM: dts: stm32: Restore old usart1 clock bindings for stm32f7 As U-boot stm32f clock driver doesn't support new bindings for auxiliary clocks (clocks = <&rcc 1 ....>), restore old bindings for usart1 to get console output. Signed-off-by: Patrice Chotard --- arch/arm/dts/stm32f7-u-boot.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi index 7816b79bcf..29b157324e 100644 --- a/arch/arm/dts/stm32f7-u-boot.dtsi +++ b/arch/arm/dts/stm32f7-u-boot.dtsi @@ -143,4 +143,5 @@ &usart1 { u-boot,dm-pre-reloc; + clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>; }; -- cgit From e4995e61c92d263f752e304b684157c7cf7844d0 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 17 Apr 2019 11:53:29 +0200 Subject: ARM: dts: stm32: Update sdmmc binding for stm32h743i-eval Update some sdmmc properties which have been updated with v4.19 DT bindings: - st,dirpol becomes st,sig-dir - st,negedge becomes st,neg-edge - st,pin-ckin becomes st,use-ckin Signed-off-by: Patrick Delaunay Signed-off-by: Patrice Chotard --- arch/arm/dts/stm32h743i-eval-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/dts/stm32h743i-eval-u-boot.dtsi b/arch/arm/dts/stm32h743i-eval-u-boot.dtsi index 220a2d706c..251977abe0 100644 --- a/arch/arm/dts/stm32h743i-eval-u-boot.dtsi +++ b/arch/arm/dts/stm32h743i-eval-u-boot.dtsi @@ -8,5 +8,5 @@ <&pinctrl_sdmmc1_level_shifter>; pinctrl-names = "default"; bus-width = <4>; - st,dirpol; + st,sig-dir; }; -- cgit From c89b87cbfccb05d863c53bcf8f8a9b39d6554540 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Tue, 12 Feb 2019 17:17:58 +0100 Subject: ARM: dts: stm32: Update sdmmc binding for stm32mp157c-ed1 Update some sdmmc properties which have been updated with v4.19 DT bindings: - st,dirpol becomes st,sig-dir - st,negedge becomes st,neg-edge - st,pin-ckin becomes st,use-ckin Signed-off-by: Patrice Chotard --- arch/arm/dts/stm32mp157c-ed1.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index 2664c9ce90..8c0ff3c6ff 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -342,9 +342,9 @@ &sdmmc1 { pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; broken-cd; - st,dirpol; - st,negedge; - st,pin-ckin; + st,sig-dir; + st,neg-edge; + st,use-ckin; bus-width = <4>; vmmc-supply = <&vdd_sd>; vqmmc-supply = <&sd_switch>; @@ -361,8 +361,8 @@ non-removable; no-sd; no-sdio; - st,dirpol; - st,negedge; + st,sig-dir; + st,neg-edge; bus-width = <8>; vmmc-supply = <&v3v3>; vqmmc-supply = <&vdd>; -- cgit