From 6e7b9f4fa0aed88051d6700afa510430b5d3fb69 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 5 Mar 2014 19:58:37 +0100 Subject: aes: Move the AES-128-CBC encryption function to common code Move the AES-128-CBC encryption function implemented in tegra20-common/crypto.c into lib/aes.c . This is well re-usable common code. Moreover, clean the code up a bit and fix the kerneldoc-style annotations. Signed-off-by: Marek Vasut --- arch/arm/cpu/tegra20-common/crypto.c | 72 +----------------------------------- 1 file changed, 2 insertions(+), 70 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/tegra20-common/crypto.c b/arch/arm/cpu/tegra20-common/crypto.c index 8209f7661a..b18e67c346 100644 --- a/arch/arm/cpu/tegra20-common/crypto.c +++ b/arch/arm/cpu/tegra20-common/crypto.c @@ -19,74 +19,6 @@ enum security_op { SECURITY_ENCRYPT = 1 << 1, /* Encrypt the data */ }; -static void debug_print_vector(char *name, u32 num_bytes, u8 *data) -{ - u32 i; - - debug("%s [%d] @0x%08x", name, num_bytes, (u32)data); - for (i = 0; i < num_bytes; i++) { - if (i % 16 == 0) - debug(" = "); - debug("%02x", data[i]); - if ((i+1) % 16 != 0) - debug(" "); - } - debug("\n"); -} - -/** - * Apply chain data to the destination using EOR - * - * Each array is of length AES_AES_KEY_LENGTH. - * - * \param cbc_chain_data Chain data - * \param src Source data - * \param dst Destination data, which is modified here - */ -static void apply_cbc_chain_data(u8 *cbc_chain_data, u8 *src, u8 *dst) -{ - int i; - - for (i = 0; i < 16; i++) - *dst++ = *src++ ^ *cbc_chain_data++; -} - -/** - * Encrypt some data with AES. - * - * \param key_schedule Expanded key to use - * \param src Source data to encrypt - * \param dst Destination buffer - * \param num_aes_blocks Number of AES blocks to encrypt - */ -static void encrypt_object(u8 *key_schedule, u8 *src, u8 *dst, - u32 num_aes_blocks) -{ - u8 tmp_data[AES_KEY_LENGTH]; - u8 *cbc_chain_data; - u32 i; - - cbc_chain_data = zero_key; /* Convenient array of 0's for IV */ - - for (i = 0; i < num_aes_blocks; i++) { - debug("encrypt_object: block %d of %d\n", i, num_aes_blocks); - debug_print_vector("AES Src", AES_KEY_LENGTH, src); - - /* Apply the chain data */ - apply_cbc_chain_data(cbc_chain_data, src, tmp_data); - debug_print_vector("AES Xor", AES_KEY_LENGTH, tmp_data); - - /* encrypt the AES block */ - aes_encrypt(tmp_data, key_schedule, dst); - debug_print_vector("AES Dst", AES_KEY_LENGTH, dst); - - /* Update pointers for next loop. */ - cbc_chain_data = dst; - src += AES_KEY_LENGTH; - dst += AES_KEY_LENGTH; - } -} - /** * Shift a vector left by one bit * @@ -129,7 +61,7 @@ static void sign_object(u8 *key, u8 *key_schedule, u8 *src, u8 *dst, for (i = 0; i < AES_KEY_LENGTH; i++) tmp_data[i] = 0; - encrypt_object(key_schedule, tmp_data, left, 1); + aes_cbc_encrypt_blocks(key_schedule, tmp_data, left, 1); debug_print_vector("AES(key, nonce)", AES_KEY_LENGTH, left); left_shift_vector(left, k1, sizeof(left)); @@ -193,7 +125,7 @@ static int encrypt_and_sign(u8 *key, enum security_op oper, u8 *src, if (oper & SECURITY_ENCRYPT) { /* Perform this in place, resulting in src being encrypted. */ debug("encrypt_and_sign: begin encryption\n"); - encrypt_object(key_schedule, src, src, num_aes_blocks); + aes_cbc_encrypt_blocks(key_schedule, src, src, num_aes_blocks); debug("encrypt_and_sign: end encryption\n"); } -- cgit From ece0d370144fdecb6f3ed5738ffe96f5b12f9e96 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 13 Mar 2014 19:48:57 +0900 Subject: sparc: consolidate CONFIG_{LEON, LEON2, LEON3} definition CONFIG_LEON is already defined in arch/sparc/cpu/{leon2,leon3}/config.mk. Remove the redundant definition in board header files. All leon3 boards define CONFIG_LEON3 in board header files. Move the definition to arch/sparc/cpu/leon3/config.mk. CONFIG_LEON2 can be move to arch/sparc/cpu/leon2/config.mk as well. Signed-off-by: Masahiro Yamada Cc: Daniel Hellstrom --- arch/sparc/cpu/leon2/config.mk | 2 +- arch/sparc/cpu/leon3/config.mk | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/sparc/cpu/leon2/config.mk b/arch/sparc/cpu/leon2/config.mk index f9b0d347f7..c44b0930ec 100644 --- a/arch/sparc/cpu/leon2/config.mk +++ b/arch/sparc/cpu/leon2/config.mk @@ -7,4 +7,4 @@ PLATFORM_RELFLAGS += -fPIC -PLATFORM_CPPFLAGS += -DCONFIG_LEON +PLATFORM_CPPFLAGS += -DCONFIG_LEON -DCONFIG_LEON2 diff --git a/arch/sparc/cpu/leon3/config.mk b/arch/sparc/cpu/leon3/config.mk index f9b0d347f7..ca6c9b13ec 100644 --- a/arch/sparc/cpu/leon3/config.mk +++ b/arch/sparc/cpu/leon3/config.mk @@ -7,4 +7,4 @@ PLATFORM_RELFLAGS += -fPIC -PLATFORM_CPPFLAGS += -DCONFIG_LEON +PLATFORM_CPPFLAGS += -DCONFIG_LEON -DCONFIG_LEON3 -- cgit From dc2164da46c1ba4a2ff44ed3cd48e5f6211640e2 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 1 Apr 2014 17:15:13 +0900 Subject: powerpc: mpc8xx: delete an unused source file References to the wireless keyboard should also be removed from README.console. Signed-off-by: Masahiro Yamada Cc: Wolfgang Denk Acked-by: Wolfgang Denk --- arch/powerpc/cpu/mpc8xx/wlkbd.c | 20 -------------------- 1 file changed, 20 deletions(-) delete mode 100644 arch/powerpc/cpu/mpc8xx/wlkbd.c (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc8xx/wlkbd.c b/arch/powerpc/cpu/mpc8xx/wlkbd.c deleted file mode 100644 index 3a41c2f164..0000000000 --- a/arch/powerpc/cpu/mpc8xx/wlkbd.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * (C) Copyright 2000 - * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#ifdef CONFIG_WL_4PPM_KEYBOARD - -/* WIP: Wireless keyboard on SMC - */ -int drv_wlkbd_init (void) -{ - return 0 ; -} - -#endif /* CONFIG_WL_4PPM_KEYBOARD */ -- cgit From d8d7cbd96affe6e842577b47afa0debf12fac2db Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 31 Mar 2014 13:29:48 +0900 Subject: kbuild: use boolean macros to select tegra*-common directory Signed-off-by: Masahiro Yamada --- arch/arm/cpu/Makefile | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile index b2d30b1a72..35d8d387bd 100644 --- a/arch/arm/cpu/Makefile +++ b/arch/arm/cpu/Makefile @@ -1,3 +1,6 @@ obj-$(CONFIG_AT91FAMILY) += at91-common/ -obj-$(CONFIG_TEGRA) += $(SOC)-common/ +obj-$(CONFIG_TEGRA20) += tegra20-common/ +obj-$(CONFIG_TEGRA30) += tegra30-common/ +obj-$(CONFIG_TEGRA114) += tegra114-common/ +obj-$(CONFIG_TEGRA124) += tegra124-common/ obj-$(CONFIG_TEGRA) += tegra-common/ -- cgit From fd11bea2ccb97909f421e20e6a5ba770dbf39d0b Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Thu, 27 Mar 2014 20:34:13 +0000 Subject: blackfin: make name_to_gpio be a weak symbol This required moving it into a C file from the header. The only user of a non-default name_to_gpio is blackfin, therefore build tested with the blackfin bct-brettl2 build, which is one I picked at random. Also tested with a build for the ARM tec board which uses the default/fallback implementation. Inspection with objdump shows that both have done the right thing. This change was requested by Marek during review of the sunxi patch series. Signed-off-by: Ian Campbell Cc: Marek Vasut Cc: Wolfgang Denk Cc: Sonic Zhang --- arch/blackfin/cpu/gpio.c | 48 +++++++++++++++++++++++++++++++++++++++ arch/blackfin/include/asm/gpio.h | 49 ---------------------------------------- 2 files changed, 48 insertions(+), 49 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/cpu/gpio.c b/arch/blackfin/cpu/gpio.c index 86da706f08..4b4cf93c2d 100644 --- a/arch/blackfin/cpu/gpio.c +++ b/arch/blackfin/cpu/gpio.c @@ -759,6 +759,54 @@ void bfin_reset_boot_spi_cs(unsigned short pin) udelay(1); } +int name_to_gpio(const char *name) +{ + int port_base; + + if (tolower(*name) == 'p') { + ++name; + + switch (tolower(*name)) { +#ifdef GPIO_PA0 + case 'a': port_base = GPIO_PA0; break; +#endif +#ifdef GPIO_PB0 + case 'b': port_base = GPIO_PB0; break; +#endif +#ifdef GPIO_PC0 + case 'c': port_base = GPIO_PC0; break; +#endif +#ifdef GPIO_PD0 + case 'd': port_base = GPIO_PD0; break; +#endif +#ifdef GPIO_PE0 + case 'e': port_base = GPIO_PE0; break; +#endif +#ifdef GPIO_PF0 + case 'f': port_base = GPIO_PF0; break; +#endif +#ifdef GPIO_PG0 + case 'g': port_base = GPIO_PG0; break; +#endif +#ifdef GPIO_PH0 + case 'h': port_base = GPIO_PH0; break; +#endif +#ifdef GPIO_PI0 + case 'i': port_base = GPIO_PI0; break; +#endif +#ifdef GPIO_PJ + case 'j': port_base = GPIO_PJ0; break; +#endif + default: return -1; + } + + ++name; + } else + port_base = 0; + + return port_base + simple_strtoul(name, NULL, 10); +} + void gpio_labels(void) { int c, gpio; diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h index 6ebcf01aff..1fa1a8e6ec 100644 --- a/arch/blackfin/include/asm/gpio.h +++ b/arch/blackfin/include/asm/gpio.h @@ -160,55 +160,6 @@ static inline int gpio_is_valid(int number) #include -static inline int name_to_gpio(const char *name) -{ - int port_base; - - if (tolower(*name) == 'p') { - ++name; - - switch (tolower(*name)) { -#ifdef GPIO_PA0 - case 'a': port_base = GPIO_PA0; break; -#endif -#ifdef GPIO_PB0 - case 'b': port_base = GPIO_PB0; break; -#endif -#ifdef GPIO_PC0 - case 'c': port_base = GPIO_PC0; break; -#endif -#ifdef GPIO_PD0 - case 'd': port_base = GPIO_PD0; break; -#endif -#ifdef GPIO_PE0 - case 'e': port_base = GPIO_PE0; break; -#endif -#ifdef GPIO_PF0 - case 'f': port_base = GPIO_PF0; break; -#endif -#ifdef GPIO_PG0 - case 'g': port_base = GPIO_PG0; break; -#endif -#ifdef GPIO_PH0 - case 'h': port_base = GPIO_PH0; break; -#endif -#ifdef GPIO_PI0 - case 'i': port_base = GPIO_PI0; break; -#endif -#ifdef GPIO_PJ - case 'j': port_base = GPIO_PJ0; break; -#endif - default: return -1; - } - - ++name; - } else - port_base = 0; - - return port_base + simple_strtoul(name, NULL, 10); -} -#define name_to_gpio(n) name_to_gpio(n) - #define gpio_status() gpio_labels() #endif /* __ASSEMBLY__ */ -- cgit From a146e8b189abf73b8bac0bfa9c8c3c1b3bfe5507 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 4 Apr 2014 15:25:02 +0900 Subject: powerpc: remove NX823 board support Enough time has passed since this board was moved to Orphan. Remove. - Remove board/nx823/* - Remove include/configs/NX823.h - Clean-up ifdef(CONFIG_NX823) - Move the entry from boards.cfg to doc/README.scrapyard Signed-off-by: Masahiro Yamada --- arch/powerpc/include/asm/u-boot.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h index 3c28420574..f4d4a6b300 100644 --- a/arch/powerpc/include/asm/u-boot.h +++ b/arch/powerpc/include/asm/u-boot.h @@ -106,9 +106,6 @@ typedef struct bd_info { unsigned int bi_opbfreq; /* OPB clock in Hz */ int bi_iic_fast[2]; /* Use fast i2c mode */ #endif -#if defined(CONFIG_NX823) - unsigned char bi_sernum[8]; -#endif #if defined(CONFIG_4xx) #if defined(CONFIG_440GX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) -- cgit From d6b11fd1f0ef1b6cbc81ca7655c47bf68a16f32d Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 4 Apr 2014 15:25:03 +0900 Subject: powerpc: remove MBX and MBX860T boards support Enough time has passed since these boards were moved to Orphan. Remove. - Remove board/mbx8xx/* - Remove include/configs/{MBX.h,MBX860T.h} - Clean-up if defined(CONFIG_MBX) - Move the entries from boards.cfg to doc/README.scrapyard Signed-off-by: Masahiro Yamada --- arch/powerpc/cpu/mpc8xx/cpu_init.c | 16 ---------------- arch/powerpc/cpu/mpc8xx/scc.c | 4 ---- arch/powerpc/cpu/mpc8xx/serial.c | 4 ---- arch/powerpc/include/asm/immap_512x.h | 1 - 4 files changed, 25 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index 53f873d1ab..69455c7be0 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -29,12 +29,10 @@ void cpm_load_patch (volatile immap_t * immr); */ void cpu_init_f (volatile immap_t * immr) { -#ifndef CONFIG_MBX volatile memctl8xx_t *memctl = &immr->im_memctl; # ifdef CONFIG_SYS_PLPRCR ulong mfmask; # endif -#endif ulong reg; /* SYPCR - contains watchdog control (11-9) */ @@ -74,8 +72,6 @@ void cpu_init_f (volatile immap_t * immr) immr->im_clkrstk.cark_plprcrk = KAPWR_KEY; -#ifndef CONFIG_MBX /* MBX board does things different */ - /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr, * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF @@ -203,8 +199,6 @@ void cpu_init_f (volatile immap_t * immr) memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM; #endif -#endif /* ! CONFIG_MBX */ - /* * Reset CPM */ @@ -213,16 +207,6 @@ void cpu_init_f (volatile immap_t * immr) __asm__ ("eieio"); } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); -#ifdef CONFIG_MBX - /* - * on the MBX, things are a little bit different: - * - we need to read the VPD to get board information - * - the plprcr is set up dynamically - * - the memory controller is set up dynamically - */ - mbx_init (); -#endif /* CONFIG_MBX */ - #ifdef CONFIG_RPXCLASSIC rpxclassic_init (); #endif diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c index 2ef77b4c14..94c9969e3f 100644 --- a/arch/powerpc/cpu/mpc8xx/scc.c +++ b/arch/powerpc/cpu/mpc8xx/scc.c @@ -492,10 +492,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis) immr->im_cpm.cp_pbdat &= ~0x00000010; #endif /* QS860T */ -#ifdef CONFIG_MBX - board_ether_init (); -#endif - #if defined(CONFIG_NETVIA) #if defined(PA_ENET_PDN) immr->im_ioport.iop_papar &= ~PA_ENET_PDN; diff --git a/arch/powerpc/cpu/mpc8xx/serial.c b/arch/powerpc/cpu/mpc8xx/serial.c index 4e840498d7..cb48ed942f 100644 --- a/arch/powerpc/cpu/mpc8xx/serial.c +++ b/arch/powerpc/cpu/mpc8xx/serial.c @@ -225,10 +225,6 @@ static int smc_init (void) up->smc_tstate = 0; #endif -#if defined(CONFIG_MBX) - board_serial_init(); -#endif /* CONFIG_MBX */ - /* Set UART mode, 8 bit, no parity, one stop. * Enable receive and transmit. */ diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h index bed80aa933..6086a73ba9 100644 --- a/arch/powerpc/include/asm/immap_512x.h +++ b/arch/powerpc/include/asm/immap_512x.h @@ -59,7 +59,6 @@ typedef struct sysconf512x { u8 res2[0x28]; law512x_t ddrlaw; /* DDR Local Access Window */ u8 res3[0x18]; - u32 mbxbar; /* MBX Base Address */ u32 srambar; /* SRAM Base Address */ u32 nfcbar; /* NFC Base Address */ u8 res4[0x34]; -- cgit From aa6e1e45cfc16d9ea199d18c639cca2a388823a2 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 4 Apr 2014 15:25:05 +0900 Subject: powerpc: remove ADS860, FADS823, FADS850SAR, FADS860T support Enough time has passed since these boards were moved to Orphan. Remove. - Remove include/configs/{ADS860.h,FADS823.h,FADS850SAR.h,FADS860T.h} - Cleanup defined(CONFIG_ADS), defined(CONFIG_MPC823FADS), defined(CONFIG_MPC850SAR), defined(CONFIG_SYS_DAUGHTERBOARD) - Remove the entries from boards.cfg Signed-off-by: Masahiro Yamada --- arch/powerpc/cpu/mpc8xx/scc.c | 12 ------------ arch/powerpc/cpu/mpc8xx/serial.c | 2 +- 2 files changed, 1 insertion(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c index 94c9969e3f..647f05817b 100644 --- a/arch/powerpc/cpu/mpc8xx/scc.c +++ b/arch/powerpc/cpu/mpc8xx/scc.c @@ -461,18 +461,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis) #error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined #endif -#if defined(CONFIG_ADS) && defined(CONFIG_MPC860) - /* - * Port C is used to control the PHY,MC68160. - */ - immr->im_ioport.iop_pcdir |= - (PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL); - - immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL; - immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL); - *((uint *) BCSR1) &= ~BCSR1_ETHEN; -#endif /* MPC860ADS */ - #ifdef CONFIG_RPXCLASSIC *((uchar *) BCSR0) &= ~BCSR0_ETHLPBK; *((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX); diff --git a/arch/powerpc/cpu/mpc8xx/serial.c b/arch/powerpc/cpu/mpc8xx/serial.c index cb48ed942f..f7ca11e394 100644 --- a/arch/powerpc/cpu/mpc8xx/serial.c +++ b/arch/powerpc/cpu/mpc8xx/serial.c @@ -173,7 +173,7 @@ static int smc_init (void) # endif #endif -#if defined(CONFIG_FADS) || defined(CONFIG_ADS) +#if defined(CONFIG_FADS) /* Enable RS232 */ #if defined(CONFIG_8xx_CONS_SMC1) *((uint *) BCSR1) &= ~BCSR1_RS232EN_1; -- cgit From 4fb3925ff8b64422eb904c630e914c29ed824e85 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 4 Apr 2014 15:25:06 +0900 Subject: powerpc: remove RPXClassic, RPXlite boards support Enough time has passed since these boards were moved to Orphan. Remove. - Remove board/RPXlite/* - Remove board/RPXClassic/* - Remove include/configs/RPXlite.h - Remove include/configs/RPXClassic.h - Clean-up defined(CONFIG_RPXCLASSIC) - Move the entry from boards.cfg to doc/README.scrapyard Signed-off-by: Masahiro Yamada --- arch/powerpc/cpu/mpc8xx/cpu_init.c | 5 ----- arch/powerpc/cpu/mpc8xx/scc.c | 7 ------- arch/powerpc/cpu/mpc8xx/serial.c | 2 +- 3 files changed, 1 insertion(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index 69455c7be0..9c3102dc69 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -138,7 +138,6 @@ void cpu_init_f (volatile immap_t * immr) defined(CONFIG_MHPC) || \ defined(CONFIG_R360MPI) || \ defined(CONFIG_RMU) || \ - defined(CONFIG_RPXCLASSIC) || \ defined(CONFIG_RPXLITE) || \ defined(CONFIG_SPC1920) || \ defined(CONFIG_SPD823TS) @@ -207,10 +206,6 @@ void cpu_init_f (volatile immap_t * immr) __asm__ ("eieio"); } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); -#ifdef CONFIG_RPXCLASSIC - rpxclassic_init (); -#endif - #if defined(CONFIG_RPXLITE) && defined(CONFIG_ENV_IS_IN_NVRAM) rpxlite_init (); #endif diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c index 647f05817b..5da697366d 100644 --- a/arch/powerpc/cpu/mpc8xx/scc.c +++ b/arch/powerpc/cpu/mpc8xx/scc.c @@ -461,11 +461,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis) #error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined #endif -#ifdef CONFIG_RPXCLASSIC - *((uchar *) BCSR0) &= ~BCSR0_ETHLPBK; - *((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX); -#endif - #ifdef CONFIG_RPXLITE *((uchar *) BCSR0) |= BCSR0_ETHEN; #endif @@ -512,8 +507,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis) */ #if defined (CONFIG_FADS) udelay (10000); /* wait 10 ms */ -#elif defined(CONFIG_RPXCLASSIC) - udelay (100000); /* wait 100 ms */ #endif return 1; diff --git a/arch/powerpc/cpu/mpc8xx/serial.c b/arch/powerpc/cpu/mpc8xx/serial.c index f7ca11e394..932141144c 100644 --- a/arch/powerpc/cpu/mpc8xx/serial.c +++ b/arch/powerpc/cpu/mpc8xx/serial.c @@ -182,7 +182,7 @@ static int smc_init (void) #endif #endif /* CONFIG_FADS */ -#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) +#if defined(CONFIG_RPXLITE) /* Enable Monitor Port Transceiver */ *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ; #endif /* CONFIG_RPXLITE */ -- cgit From 03f2ecc2cb28efeb35912710754d9857cdc05190 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 4 Apr 2014 15:25:09 +0900 Subject: powerpc: remove MOUSSE board support Enough time has passed since this board was moved to Orphan. Remove. - Remove board/mousse/* - Remove include/configs/MOUSSE.h - Clean-up defined(CONFIG_MOUSSE) - Move the entry from boards.cfg to doc/README.scrapyard Signed-off-by: Masahiro Yamada --- arch/powerpc/cpu/mpc824x/cpu_init.c | 88 ------------------------------------- 1 file changed, 88 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc824x/cpu_init.c b/arch/powerpc/cpu/mpc824x/cpu_init.c index 47ac18e757..68d88e910c 100644 --- a/arch/powerpc/cpu/mpc824x/cpu_init.c +++ b/arch/powerpc/cpu/mpc824x/cpu_init.c @@ -46,8 +46,6 @@ void cpu_init_f (void) { -/* MOUSSE board is initialized in asm */ -#if !defined(CONFIG_MOUSSE) register unsigned long val; CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/ /* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/ @@ -302,98 +300,12 @@ cpu_init_f (void) CONFIG_READ_WORD(MCCR1, val); CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */ __asm__ __volatile__("eieio"); - -#endif /* !CONFIG_MOUSSE */ } - -#ifdef CONFIG_MOUSSE -#ifdef INCLUDE_MPC107_REPORT -struct MPC107_s { - unsigned int iobase; - char desc[120]; -} MPC107Regs[] = { - { BMC_BASE + 0x00, "MPC107 Vendor/Device ID" }, - { BMC_BASE + 0x04, "MPC107 PCI Command/Status Register" }, - { BMC_BASE + 0x08, "MPC107 Revision" }, - { BMC_BASE + 0x0C, "MPC107 Cache Line Size" }, - { BMC_BASE + 0x10, "MPC107 LMBAR" }, - { BMC_BASE + 0x14, "MPC824x PCSR" }, - { BMC_BASE + 0xA8, "MPC824x PICR1" }, - { BMC_BASE + 0xAC, "MPC824x PICR2" }, - { BMC_BASE + 0x46, "MPC824x PACR" }, - { BMC_BASE + 0x310, "MPC824x ITWR" }, - { BMC_BASE + 0x300, "MPC824x OMBAR" }, - { BMC_BASE + 0x308, "MPC824x OTWR" }, - { BMC_BASE + 0x14, "MPC107 Peripheral Control and Status Register" }, - { BMC_BASE + 0x78, "MPC107 EUMBAR" }, - { BMC_BASE + 0xC0, "MPC107 Processor Bus Error Status" }, - { BMC_BASE + 0xC4, "MPC107 PCI Bus Error Status" }, - { BMC_BASE + 0xC8, "MPC107 Processor/PCI Error Address" }, - { BMC_BASE + 0xE0, "MPC107 AMBOR Register" }, - { BMC_BASE + 0xF0, "MPC107 MCCR1 Register" }, - { BMC_BASE + 0xF4, "MPC107 MCCR2 Register" }, - { BMC_BASE + 0xF8, "MPC107 MCCR3 Register" }, - { BMC_BASE + 0xFC, "MPC107 MCCR4 Register" }, -}; -#define N_MPC107_Regs (sizeof(MPC107Regs)/sizeof(MPC107Regs[0])) -#endif /* INCLUDE_MPC107_REPORT */ -#endif /* CONFIG_MOUSSE */ - /* * initialize higher level parts of CPU like time base and timers */ int cpu_init_r (void) { -#ifdef CONFIG_MOUSSE -#ifdef INCLUDE_MPC107_REPORT - unsigned int tmp = 0, i; -#endif - /* - * Initialize the EUMBBAR (Embedded Util Mem Block Base Addr Reg). - * This is necessary before the EPIC, DMA ctlr, I2C ctlr, etc. can - * be accessed. - */ - -#ifdef CONFIG_MPC8240 /* only on MPC8240 */ - mpc824x_mpc107_setreg (EUMBBAR, EUMBBAR_VAL); - /* MOT/SPS: Issue #10002, PCI (FD Alias enable) */ - mpc824x_mpc107_setreg (AMBOR, 0x000000C0); -#endif - - -#ifdef INCLUDE_MPC107_REPORT - /* Check MPC824x PCI Device and Vendor ID */ - while ((tmp = mpc824x_mpc107_getreg (BMC_BASE)) != 0x31057) { - printf (" MPC107: offset=0x%x, val = 0x%x\n", - BMC_BASE, - tmp); - } - - for (i = 0; i < N_MPC107_Regs; i++) { - printf (" 0x%x/%s = 0x%x\n", - MPC107Regs[i].iobase, - MPC107Regs[i].desc, - mpc824x_mpc107_getreg (MPC107Regs[i].iobase)); - } - - printf ("IBAT0L = 0x%08X\n", mfspr (IBAT0L)); - printf ("IBAT0U = 0x%08X\n", mfspr (IBAT0U)); - printf ("IBAT1L = 0x%08X\n", mfspr (IBAT1L)); - printf ("IBAT1U = 0x%08X\n", mfspr (IBAT1U)); - printf ("IBAT2L = 0x%08X\n", mfspr (IBAT2L)); - printf ("IBAT2U = 0x%08X\n", mfspr (IBAT2U)); - printf ("IBAT3L = 0x%08X\n", mfspr (IBAT3L)); - printf ("IBAT3U = 0x%08X\n", mfspr (IBAT3U)); - printf ("DBAT0L = 0x%08X\n", mfspr (DBAT0L)); - printf ("DBAT0U = 0x%08X\n", mfspr (DBAT0U)); - printf ("DBAT1L = 0x%08X\n", mfspr (DBAT1L)); - printf ("DBAT1U = 0x%08X\n", mfspr (DBAT1U)); - printf ("DBAT2L = 0x%08X\n", mfspr (DBAT2L)); - printf ("DBAT2U = 0x%08X\n", mfspr (DBAT2U)); - printf ("DBAT3L = 0x%08X\n", mfspr (DBAT3L)); - printf ("DBAT3U = 0x%08X\n", mfspr (DBAT3U)); -#endif /* INCLUDE_MPC107_REPORT */ -#endif /* CONFIG_MOUSSE */ return (0); } -- cgit From 53eb768dfb97269ccec60d34321252b1ee1850d9 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 18 Apr 2014 10:28:58 -0600 Subject: aes: make apply_cbc_chain_data non-static MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tegra's crypto.c uses apply_cbc_chain_data() to sign the warm restart code. This function was recently moved into the core aes.c and made static, which prevents the Tegra code from compiling. Make it public again to avoid the compile errors: arch/arm/cpu/tegra20-common/crypto.c: In function ‘sign_object’: arch/arm/cpu/tegra20-common/crypto.c:74:3: warning: implicit declaration of function ‘apply_cbc_chain_data’ [-Wimplicit-function-declaration] arch/arm/cpu/built-in.o: In function `sign_object': .../arch/arm/cpu/tegra20-common/crypto.c:74: undefined reference to `apply_cbc_chain_data' .../arch/arm/cpu/tegra20-common/crypto.c:78: undefined reference to `apply_cbc_chain_data' Fixes: 6e7b9f4fa0ae ("aes: Move the AES-128-CBC encryption function to common code") Signed-off-by: Stephen Warren Reviewed-by: Simon Glass Acked-by: Marek Vasut --- arch/arm/cpu/tegra20-common/crypto.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/tegra20-common/crypto.c b/arch/arm/cpu/tegra20-common/crypto.c index b18e67c346..0967f3ed04 100644 --- a/arch/arm/cpu/tegra20-common/crypto.c +++ b/arch/arm/cpu/tegra20-common/crypto.c @@ -74,11 +74,11 @@ static void sign_object(u8 *key, u8 *key_schedule, u8 *src, u8 *dst, /* compute the AES-CMAC value */ for (i = 0; i < num_aes_blocks; i++) { /* Apply the chain data */ - apply_cbc_chain_data(cbc_chain_data, src, tmp_data); + aes_apply_cbc_chain_data(cbc_chain_data, src, tmp_data); /* for the final block, XOR K1 into the IV */ if (i == num_aes_blocks - 1) - apply_cbc_chain_data(tmp_data, k1, tmp_data); + aes_apply_cbc_chain_data(tmp_data, k1, tmp_data); /* encrypt the AES block */ aes_encrypt(tmp_data, key_schedule, dst); -- cgit From b149c4c399b111cec1ff7505ca9fabbeeb4fe394 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 18 Apr 2014 08:18:23 -0400 Subject: ARM:tegra20: Remove aes debug prints In 6e7b9f4 some of the debug prints for AES code moved into the generic code, so we remove these additional calls. Signed-off-by: Tom Rini Acked-by: Tom Warren --- arch/arm/cpu/tegra20-common/crypto.c | 9 --------- 1 file changed, 9 deletions(-) (limited to 'arch') diff --git a/arch/arm/cpu/tegra20-common/crypto.c b/arch/arm/cpu/tegra20-common/crypto.c index 0967f3ed04..ec95d7ceb1 100644 --- a/arch/arm/cpu/tegra20-common/crypto.c +++ b/arch/arm/cpu/tegra20-common/crypto.c @@ -62,14 +62,11 @@ static void sign_object(u8 *key, u8 *key_schedule, u8 *src, u8 *dst, tmp_data[i] = 0; aes_cbc_encrypt_blocks(key_schedule, tmp_data, left, 1); - debug_print_vector("AES(key, nonce)", AES_KEY_LENGTH, left); left_shift_vector(left, k1, sizeof(left)); - debug_print_vector("L", AES_KEY_LENGTH, left); if ((left[0] >> 7) != 0) /* get MSB of L */ k1[AES_KEY_LENGTH-1] ^= AES_CMAC_CONST_RB; - debug_print_vector("K1", AES_KEY_LENGTH, k1); /* compute the AES-CMAC value */ for (i = 0; i < num_aes_blocks; i++) { @@ -84,16 +81,11 @@ static void sign_object(u8 *key, u8 *key_schedule, u8 *src, u8 *dst, aes_encrypt(tmp_data, key_schedule, dst); debug("sign_obj: block %d of %d\n", i, num_aes_blocks); - debug_print_vector("AES-CMAC Src", AES_KEY_LENGTH, src); - debug_print_vector("AES-CMAC Xor", AES_KEY_LENGTH, tmp_data); - debug_print_vector("AES-CMAC Dst", AES_KEY_LENGTH, dst); /* Update pointers for next loop. */ cbc_chain_data = dst; src += AES_KEY_LENGTH; } - - debug_print_vector("AES-CMAC Hash", AES_KEY_LENGTH, dst); } /** @@ -112,7 +104,6 @@ static int encrypt_and_sign(u8 *key, enum security_op oper, u8 *src, u8 key_schedule[AES_EXPAND_KEY_LENGTH]; debug("encrypt_and_sign: length = %d\n", length); - debug_print_vector("AES key", AES_KEY_LENGTH, key); /* * The only need for a key is for signing/checksum purposes, so -- cgit From 79fd7e649e287228a1445820a72f7dd33baedb96 Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Fri, 11 Oct 2013 17:46:59 +0200 Subject: MIPS: always keep all sections in u-boot ELF binary. Always keep all sections in u-boot ELF binary. Move all unneeded sections after _end to avoid allocating space in the final binary. Also remove .deadcode section which is now obsolete. Signed-off-by: Daniel Schwierzeck --- arch/mips/config.mk | 3 ++- arch/mips/cpu/u-boot.lds | 56 ++++++++++++++++++++++++++---------------------- 2 files changed, 32 insertions(+), 27 deletions(-) (limited to 'arch') diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 1899f51872..42a806252b 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -52,4 +52,5 @@ PLATFORM_CPPFLAGS += -msoft-float PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib $(ENDIANNESS) PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections LDFLAGS_FINAL += --gc-sections -pie -OBJCOPYFLAGS += --remove-section=.dynsym +OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .got +OBJCOPYFLAGS += -j .u_boot_list -j .rel.dyn diff --git a/arch/mips/cpu/u-boot.lds b/arch/mips/cpu/u-boot.lds index 16a9d6ac57..4c9edf8a69 100644 --- a/arch/mips/cpu/u-boot.lds +++ b/arch/mips/cpu/u-boot.lds @@ -60,27 +60,7 @@ SECTIONS __rel_dyn_end = .; } - .deadcode : { - /* - * Workaround for a binutils feature (or bug?). - * - * The GNU ld from binutils puts the dynamic relocation - * entries into the .rel.dyn section. Sometimes it - * allocates more dynamic relocation entries than it needs - * and the unused slots are set to R_MIPS_NONE entries. - * - * However the size of the .rel.dyn section in the ELF - * section header does not cover the unused entries, so - * objcopy removes those during stripping. - * - * Create a small section here to avoid that. - */ - LONG(0xffffffff); - } - - .dynsym : { - *(.dynsym) - } + _end = .; .bss __rel_dyn_start (OVERLAY) : { __bss_start = .; @@ -91,15 +71,39 @@ SECTIONS __bss_end = .; } - /DISCARD/ : { + .dynsym _end : { + *(.dynsym) + } + + .dynbss : { *(.dynbss) + } + + .dynstr : { *(.dynstr) + } + + .dynamic : { *(.dynamic) + } + + .plt : { + *(.plt) + } + + .interp : { *(.interp) + } + + .gnu : { + *(.gnu*) + } + + .MIPS.stubs : { + *(.MIPS.stubs) + } + + .hash : { *(.hash) - *(.gnu.*) - *(.plt) - *(.got.plt) - *(.rel.plt) } } -- cgit From 7e3d473b5ec5ee2cf6220ce15d9f87c565d98b05 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 7 Mar 2014 18:02:01 +0900 Subject: mips: xburst: remove remainders of dead board Commit 54e458de deleted qi_lb60 board support because of the incompatible license issue. There is no board with XBurst CPU. Signed-off-by: Masahiro Yamada Cc: Daniel Schwierzeck --- arch/mips/cpu/xburst/Makefile | 9 -- arch/mips/cpu/xburst/config.mk | 16 --- arch/mips/cpu/xburst/cpu.c | 136 ---------------------- arch/mips/cpu/xburst/jz4740.c | 235 --------------------------------------- arch/mips/cpu/xburst/jz_serial.c | 118 -------------------- arch/mips/cpu/xburst/start.S | 179 ----------------------------- arch/mips/cpu/xburst/timer.c | 149 ------------------------- 7 files changed, 842 deletions(-) delete mode 100644 arch/mips/cpu/xburst/Makefile delete mode 100644 arch/mips/cpu/xburst/config.mk delete mode 100644 arch/mips/cpu/xburst/cpu.c delete mode 100644 arch/mips/cpu/xburst/jz4740.c delete mode 100644 arch/mips/cpu/xburst/jz_serial.c delete mode 100644 arch/mips/cpu/xburst/start.S delete mode 100644 arch/mips/cpu/xburst/timer.c (limited to 'arch') diff --git a/arch/mips/cpu/xburst/Makefile b/arch/mips/cpu/xburst/Makefile deleted file mode 100644 index 57714d0c95..0000000000 --- a/arch/mips/cpu/xburst/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright (C) 2011 Xiangfu Liu -# -# SPDX-License-Identifier: GPL-2.0+ -# - -extra-y = start.o -obj-y = cpu.o timer.o jz_serial.o -obj-$(CONFIG_JZ4740) += jz4740.o diff --git a/arch/mips/cpu/xburst/config.mk b/arch/mips/cpu/xburst/config.mk deleted file mode 100644 index b8e53e55c0..0000000000 --- a/arch/mips/cpu/xburst/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (C) 2011 Xiangfu Liu -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -march=mips32 -PLATFORM_CPPFLAGS += -mabi=32 -DCONFIG_32BIT -ifdef CONFIG_SYS_BIG_ENDIAN -PLATFORM_LDFLAGS += -m elf32btsmip -else -PLATFORM_LDFLAGS += -m elf32ltsmip -endif - -CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 \ - -T $(srctree)/examples/standalone/mips.lds diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c deleted file mode 100644 index 1fdaa32bb0..0000000000 --- a/arch/mips/cpu/xburst/cpu.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, - * (C) Copyright 2011 - * Xiangfu Liu - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define cache_op(op, addr) \ - __asm__ __volatile__( \ - ".set push\n" \ - ".set noreorder\n" \ - ".set mips3\n" \ - "cache %0, %1\n" \ - ".set pop\n" \ - : \ - : "i" (op), "R" (*(unsigned char *)(addr))) - -void __attribute__((weak)) _machine_restart(void) -{ - struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE; - struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE; - u16 tmp; - - /* wdt_select_extalclk() */ - tmp = readw(&wdt->tcsr); - tmp &= ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN); - tmp |= WDT_TCSR_EXT_EN; - writew(tmp, &wdt->tcsr); - - /* wdt_select_clk_div64() */ - tmp = readw(&wdt->tcsr); - tmp &= ~WDT_TCSR_PRESCALE_MASK; - tmp |= WDT_TCSR_PRESCALE64, - writew(tmp, &wdt->tcsr); - - writew(100, &wdt->tdr); /* wdt_set_data(100) */ - writew(0, &wdt->tcnt); /* wdt_set_count(0); */ - writel(TCU_TSSR_WDTSC, &tcu->tscr); /* tcu_start_wdt_clock */ - writeb(readb(&wdt->tcer) | WDT_TCER_TCEN, &wdt->tcer); /* wdt start */ - - while (1) - ; -} - -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - _machine_restart(); - - fprintf(stderr, "*** reset failed ***\n"); - return 0; -} - -void flush_cache(ulong start_addr, ulong size) -{ - unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; - unsigned long addr = start_addr & ~(lsize - 1); - unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); - - for (; addr <= aend; addr += lsize) { - cache_op(HIT_WRITEBACK_INV_D, addr); - cache_op(HIT_INVALIDATE_I, addr); - } -} - -void flush_dcache_range(ulong start_addr, ulong stop) -{ - unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; - unsigned long addr = start_addr & ~(lsize - 1); - unsigned long aend = (stop - 1) & ~(lsize - 1); - - for (; addr <= aend; addr += lsize) - cache_op(HIT_WRITEBACK_INV_D, addr); -} - -void invalidate_dcache_range(ulong start_addr, ulong stop) -{ - unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; - unsigned long addr = start_addr & ~(lsize - 1); - unsigned long aend = (stop - 1) & ~(lsize - 1); - - for (; addr <= aend; addr += lsize) - cache_op(HIT_INVALIDATE_D, addr); -} - -void flush_icache_all(void) -{ - u32 addr, t = 0; - - __asm__ __volatile__("mtc0 $0, $28"); /* Clear Taglo */ - __asm__ __volatile__("mtc0 $0, $29"); /* Clear TagHi */ - - for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_ICACHE_SIZE; - addr += CONFIG_SYS_CACHELINE_SIZE) { - cache_op(INDEX_STORE_TAG_I, addr); - } - - /* invalidate btb */ - __asm__ __volatile__( - ".set mips32\n\t" - "mfc0 %0, $16, 7\n\t" - "nop\n\t" - "ori %0,2\n\t" - "mtc0 %0, $16, 7\n\t" - ".set mips2\n\t" - : - : "r" (t)); -} - -void flush_dcache_all(void) -{ - u32 addr; - - for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE; - addr += CONFIG_SYS_CACHELINE_SIZE) { - cache_op(INDEX_WRITEBACK_INV_D, addr); - } - - __asm__ __volatile__("sync"); -} - -void flush_cache_all(void) -{ - flush_dcache_all(); - flush_icache_all(); -} diff --git a/arch/mips/cpu/xburst/jz4740.c b/arch/mips/cpu/xburst/jz4740.c deleted file mode 100644 index 30f35bde7a..0000000000 --- a/arch/mips/cpu/xburst/jz4740.c +++ /dev/null @@ -1,235 +0,0 @@ -/* - * Jz4740 common routines - * Copyright (c) 2006 Ingenic Semiconductor, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -void enable_interrupts(void) -{ -} - -int disable_interrupts(void) -{ - return 0; -} - -/* - * PLL output clock = EXTAL * NF / (NR * NO) - * NF = FD + 2, NR = RD + 2 - * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3) - */ -void pll_init(void) -{ - struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE; - - register unsigned int cfcr, plcr1; - int n2FR[33] = { - 0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, - 7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, - 9 - }; - int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */ - int nf, pllout2; - - cfcr = CPM_CPCCR_CLKOEN | - CPM_CPCCR_PCS | - (n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) | - (n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) | - (n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) | - (n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) | - (n2FR[div[4]] << CPM_CPCCR_LDIV_BIT); - - pllout2 = (cfcr & CPM_CPCCR_PCS) ? - CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2); - - /* Init USB Host clock, pllout2 must be n*48MHz */ - writel(pllout2 / 48000000 - 1, &cpm->uhccdr); - - nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL; - plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */ - (0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */ - (0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */ - (0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */ - CPM_CPPCR_PLLEN; /* enable PLL */ - - /* init PLL */ - writel(cfcr, &cpm->cpccr); - writel(plcr1, &cpm->cppcr); -} - -void sdram_init(void) -{ - struct jz4740_emc *emc = (struct jz4740_emc *)JZ4740_EMC_BASE; - - register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns; - - unsigned int cas_latency_sdmr[2] = { - EMC_SDMR_CAS_2, - EMC_SDMR_CAS_3, - }; - - unsigned int cas_latency_dmcr[2] = { - 1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */ - 2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */ - }; - - int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; - - cpu_clk = CONFIG_SYS_CPU_SPEED; - mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()]; - - writel(0, &emc->bcr); /* Disable bus release */ - writew(0, &emc->rtcsr); /* Disable clock for counting */ - - /* Fault DMCR value for mode register setting*/ -#define SDRAM_ROW0 11 -#define SDRAM_COL0 8 -#define SDRAM_BANK40 0 - - dmcr0 = ((SDRAM_ROW0 - 11) << EMC_DMCR_RA_BIT) | - ((SDRAM_COL0 - 8) << EMC_DMCR_CA_BIT) | - (SDRAM_BANK40 << EMC_DMCR_BA_BIT) | - (SDRAM_BW16 << EMC_DMCR_BW_BIT) | - EMC_DMCR_EPIN | - cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; - - /* Basic DMCR value */ - dmcr = ((SDRAM_ROW - 11) << EMC_DMCR_RA_BIT) | - ((SDRAM_COL - 8) << EMC_DMCR_CA_BIT) | - (SDRAM_BANK4 << EMC_DMCR_BA_BIT) | - (SDRAM_BW16 << EMC_DMCR_BW_BIT) | - EMC_DMCR_EPIN | - cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; - - /* SDRAM timimg */ - ns = 1000000000 / mem_clk; - tmp = SDRAM_TRAS / ns; - if (tmp < 4) - tmp = 4; - if (tmp > 11) - tmp = 11; - dmcr |= (tmp - 4) << EMC_DMCR_TRAS_BIT; - tmp = SDRAM_RCD / ns; - - if (tmp > 3) - tmp = 3; - dmcr |= tmp << EMC_DMCR_RCD_BIT; - tmp = SDRAM_TPC / ns; - - if (tmp > 7) - tmp = 7; - dmcr |= tmp << EMC_DMCR_TPC_BIT; - tmp = SDRAM_TRWL / ns; - - if (tmp > 3) - tmp = 3; - dmcr |= tmp << EMC_DMCR_TRWL_BIT; - tmp = (SDRAM_TRAS + SDRAM_TPC) / ns; - - if (tmp > 14) - tmp = 14; - dmcr |= ((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT; - - /* SDRAM mode value */ - sdmode = EMC_SDMR_BT_SEQ | - EMC_SDMR_OM_NORMAL | - EMC_SDMR_BL_4 | - cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)]; - - /* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */ - writel(dmcr, &emc->dmcr); - writeb(0, JZ4740_EMC_SDMR0 | sdmode); - - /* Wait for precharge, > 200us */ - tmp = (cpu_clk / 1000000) * 1000; - while (tmp--) - ; - - /* Stage 2. Enable auto-refresh */ - writel(dmcr | EMC_DMCR_RFSH, &emc->dmcr); - - tmp = SDRAM_TREF / ns; - tmp = tmp / 64 + 1; - if (tmp > 0xff) - tmp = 0xff; - writew(tmp, &emc->rtcor); - writew(0, &emc->rtcnt); - /* Divisor is 64, CKO/64 */ - writew(EMC_RTCSR_CKS_64, &emc->rtcsr); - - /* Wait for number of auto-refresh cycles */ - tmp = (cpu_clk / 1000000) * 1000; - while (tmp--) - ; - - /* Stage 3. Mode Register Set */ - writel(dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr); - writeb(0, JZ4740_EMC_SDMR0 | sdmode); - - /* Set back to basic DMCR value */ - writel(dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr); - - /* everything is ok now */ -} - -DECLARE_GLOBAL_DATA_PTR; - -void calc_clocks(void) -{ - unsigned int pllout; - unsigned int div[10] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32}; - - pllout = __cpm_get_pllout(); - - gd->cpu_clk = pllout / div[__cpm_get_cdiv()]; - gd->arch.sys_clk = pllout / div[__cpm_get_hdiv()]; - gd->arch.per_clk = pllout / div[__cpm_get_pdiv()]; - gd->mem_clk = pllout / div[__cpm_get_mdiv()]; - gd->arch.dev_clk = CONFIG_SYS_EXTAL; -} - -void rtc_init(void) -{ - struct jz4740_rtc *rtc = (struct jz4740_rtc *)JZ4740_RTC_BASE; - - while (!(readl(&rtc->rcr) & RTC_RCR_WRDY)) - ; - writel(readl(&rtc->rcr) | RTC_RCR_AE, &rtc->rcr); /* enable alarm */ - - while (!(readl(&rtc->rcr) & RTC_RCR_WRDY)) - ; - writel(0x00007fff, &rtc->rgr); /* type value */ - - while (!(readl(&rtc->rcr) & RTC_RCR_WRDY)) - ; - writel(0x0000ffe0, &rtc->hwfcr); /* Power on delay 2s */ - - while (!(readl(&rtc->rcr) & RTC_RCR_WRDY)) - ; - writel(0x00000fe0, &rtc->hrcr); /* reset delay 125ms */ -} - -/* U-Boot common routines */ -phys_size_t initdram(int board_type) -{ - struct jz4740_emc *emc = (struct jz4740_emc *)JZ4740_EMC_BASE; - u32 dmcr; - u32 rows, cols, dw, banks; - ulong size; - - dmcr = readl(&emc->dmcr); - rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT); - cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT); - dw = (dmcr & EMC_DMCR_BW) ? 2 : 4; - banks = (dmcr & EMC_DMCR_BA) ? 4 : 2; - - size = (1 << (rows + cols)) * dw * banks; - - return size; -} diff --git a/arch/mips/cpu/xburst/jz_serial.c b/arch/mips/cpu/xburst/jz_serial.c deleted file mode 100644 index 9184223794..0000000000 --- a/arch/mips/cpu/xburst/jz_serial.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Jz4740 UART support - * Copyright (c) 2011 - * Qi Hardware, Xiangfu Liu - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -/* - * serial_init - initialize a channel - * - * This routine initializes the number of data bits, parity - * and set the selected baud rate. Interrupts are disabled. - * Set the modem control signals if the option is selected. - * - * RETURNS: N/A - */ -struct jz4740_uart *uart = (struct jz4740_uart *)CONFIG_SYS_UART_BASE; - -static int jz_serial_init(void) -{ - /* Disable port interrupts while changing hardware */ - writeb(0, &uart->dlhr_ier); - - /* Disable UART unit function */ - writeb(~UART_FCR_UUE, &uart->iir_fcr); - - /* Set both receiver and transmitter in UART mode (not SIR) */ - writeb(~(SIRCR_RSIRE | SIRCR_TSIRE), &uart->isr); - - /* - * Set databits, stopbits and parity. - * (8-bit data, 1 stopbit, no parity) - */ - writeb(UART_LCR_WLEN_8 | UART_LCR_STOP_1, &uart->lcr); - - /* Set baud rate */ - serial_setbrg(); - - /* Enable UART unit, enable and clear FIFO */ - writeb(UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS, - &uart->iir_fcr); - - return 0; -} - -static void jz_serial_setbrg(void) -{ - u32 baud_div, tmp; - - baud_div = CONFIG_SYS_EXTAL / 16 / CONFIG_BAUDRATE; - - tmp = readb(&uart->lcr); - tmp |= UART_LCR_DLAB; - writeb(tmp, &uart->lcr); - - writeb((baud_div >> 8) & 0xff, &uart->dlhr_ier); - writeb(baud_div & 0xff, &uart->rbr_thr_dllr); - - tmp &= ~UART_LCR_DLAB; - writeb(tmp, &uart->lcr); -} - -static int jz_serial_tstc(void) -{ - if (readb(&uart->lsr) & UART_LSR_DR) - return 1; - - return 0; -} - -static void jz_serial_putc(const char c) -{ - if (c == '\n') - serial_putc('\r'); - - /* Wait for fifo to shift out some bytes */ - while (!((readb(&uart->lsr) & (UART_LSR_TDRQ | UART_LSR_TEMT)) == 0x60)) - ; - - writeb((u8)c, &uart->rbr_thr_dllr); -} - -static int jz_serial_getc(void) -{ - while (!serial_tstc()) - ; - - return readb(&uart->rbr_thr_dllr); -} - -static struct serial_device jz_serial_drv = { - .name = "jz_serial", - .start = jz_serial_init, - .stop = NULL, - .setbrg = jz_serial_setbrg, - .putc = jz_serial_putc, - .puts = default_serial_puts, - .getc = jz_serial_getc, - .tstc = jz_serial_tstc, -}; - -void jz_serial_initialize(void) -{ - serial_register(&jz_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &jz_serial_drv; -} diff --git a/arch/mips/cpu/xburst/start.S b/arch/mips/cpu/xburst/start.S deleted file mode 100644 index 10dffb4a5c..0000000000 --- a/arch/mips/cpu/xburst/start.S +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Startup Code for MIPS32 XBURST CPU-core - * - * Copyright (c) 2010 Xiangfu Liu - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - - .set noreorder - - .globl _start - .text -_start: - /* Initialize $gp */ - bal 1f - nop - .word _gp -1: - lw gp, 0(ra) - - /* Set up temporary stack */ - li sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET - - la t9, board_init_f - jr t9 - nop - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * a0 = addr_sp - * a1 = gd - * a2 = destination address - */ - .globl relocate_code - .ent relocate_code -relocate_code: - move sp, a0 # set new stack pointer - - move s0, a1 # save gd in s0 - move s2, a2 # save destination address in s2 - - li t0, CONFIG_SYS_MONITOR_BASE - sub s1, s2, t0 # s1 <-- relocation offset - - la t3, in_ram - lw t2, -12(t3) # t2 <-- __image_copy_end - move t1, a2 - - add gp, s1 # adjust gp - - /* - * t0 = source address - * t1 = target address - * t2 = source end address - */ -1: - lw t3, 0(t0) - sw t3, 0(t1) - addu t0, 4 - blt t0, t2, 1b - addu t1, 4 - - /* If caches were enabled, we would have to flush them here. */ - - /* flush d-cache */ - li t0, KSEG0 - addi t1, t0, CONFIG_SYS_DCACHE_SIZE -2: - cache INDEX_WRITEBACK_INV_D, 0(t0) - bne t0, t1, 2b - addi t0, CONFIG_SYS_CACHELINE_SIZE - - sync - - /* flush i-cache */ - li t0, KSEG0 - addi t1, t0, CONFIG_SYS_ICACHE_SIZE -3: - cache INDEX_INVALIDATE_I, 0(t0) - bne t0, t1, 3b - addi t0, CONFIG_SYS_CACHELINE_SIZE - - /* Invalidate BTB */ - mfc0 t0, CP0_CONFIG, 7 - nop - ori t0, 2 - mtc0 t0, CP0_CONFIG, 7 - nop - - /* Jump to where we've relocated ourselves */ - addi t0, s2, in_ram - _start - jr t0 - nop - - .word __rel_dyn_end - .word __rel_dyn_start - .word __image_copy_end - .word _GLOBAL_OFFSET_TABLE_ - .word num_got_entries - -in_ram: - /* - * Now we want to update GOT. - * - * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object - * generated by GNU ld. Skip these reserved entries from relocation. - */ - lw t3, -4(t0) # t3 <-- num_got_entries - lw t8, -8(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_ - add t8, s1 # t8 now holds relocated _G_O_T_ - addi t8, t8, 8 # skipping first two entries - li t2, 2 -1: - lw t1, 0(t8) - beqz t1, 2f - add t1, s1 - sw t1, 0(t8) -2: - addi t2, 1 - blt t2, t3, 1b - addi t8, 4 - - /* Update dynamic relocations */ - lw t1, -16(t0) # t1 <-- __rel_dyn_start - lw t2, -20(t0) # t2 <-- __rel_dyn_end - - b 2f # skip first reserved entry - addi t1, 8 - -1: - lw t8, -4(t1) # t8 <-- relocation info - - li t3, 3 - bne t8, t3, 2f # skip non R_MIPS_REL32 entries - nop - - lw t3, -8(t1) # t3 <-- location to fix up in FLASH - - lw t8, 0(t3) # t8 <-- original pointer - add t8, s1 # t8 <-- adjusted pointer - - add t3, s1 # t3 <-- location to fix up in RAM - sw t8, 0(t3) - -2: - blt t1, t2, 1b - addi t1, 8 # each rel.dyn entry is 8 bytes - - /* - * Clear BSS - * - * GOT is now relocated. Thus __bss_start and __bss_end can be - * accessed directly via $gp. - */ - la t1, __bss_start # t1 <-- __bss_start - la t2, __bss_end # t2 <-- __bss_end - -1: - sw zero, 0(t1) - blt t1, t2, 1b - addi t1, 4 - - move a0, s0 # a0 <-- gd - la t9, board_init_r - jr t9 - move a1, s2 - - .end relocate_code diff --git a/arch/mips/cpu/xburst/timer.c b/arch/mips/cpu/xburst/timer.c deleted file mode 100644 index 79f34f00c9..0000000000 --- a/arch/mips/cpu/xburst/timer.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (c) 2006 - * Ingenic Semiconductor, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include - -#define TIMER_CHAN 0 -#define TIMER_FDATA 0xffff /* Timer full data value */ - -DECLARE_GLOBAL_DATA_PTR; - -static struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE; - -void reset_timer_masked(void) -{ - /* reset time */ - gd->arch.lastinc = readl(&tcu->tcnt0); - gd->arch.tbl = 0; -} - -ulong get_timer_masked(void) -{ - ulong now = readl(&tcu->tcnt0); - - if (gd->arch.lastinc <= now) - gd->arch.tbl += now - gd->arch.lastinc; /* normal mode */ - else { - /* we have an overflow ... */ - gd->arch.tbl += TIMER_FDATA + now - gd->arch.lastinc; - } - - gd->arch.lastinc = now; - - return gd->arch.tbl; -} - -void udelay_masked(unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - /* normalize */ - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= CONFIG_SYS_HZ; - tmo /= 1000; - } else { - if (usec > 1) { - tmo = usec * CONFIG_SYS_HZ; - tmo /= 1000*1000; - } else - tmo = 1; - } - - endtime = get_timer_masked() + tmo; - - do { - ulong now = get_timer_masked(); - diff = endtime - now; - } while (diff >= 0); -} - -int timer_init(void) -{ - writel(TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN, &tcu->tcsr0); - - writel(0, &tcu->tcnt0); - writel(0, &tcu->tdhr0); - writel(TIMER_FDATA, &tcu->tdfr0); - - /* mask irqs */ - writel((1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)), &tcu->tmsr); - writel(1 << TIMER_CHAN, &tcu->tscr); /* enable timer clock */ - writeb(1 << TIMER_CHAN, &tcu->tesr); /* start counting up */ - - gd->arch.lastinc = 0; - gd->arch.tbl = 0; - - return 0; -} - -void reset_timer(void) -{ - reset_timer_masked(); -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -void set_timer(ulong t) -{ - gd->arch.tbl = t; -} - -void __udelay(unsigned long usec) -{ - ulong tmo, tmp; - - /* normalize */ - if (usec >= 1000) { - tmo = usec / 1000; - tmo *= CONFIG_SYS_HZ; - tmo /= 1000; - } else { - if (usec >= 1) { - tmo = usec * CONFIG_SYS_HZ; - tmo /= 1000 * 1000; - } else - tmo = 1; - } - - /* check for rollover during this delay */ - tmp = get_timer(0); - if ((tmp + tmo) < tmp) - reset_timer_masked(); /* timer would roll over */ - else - tmo += tmp; - - while (get_timer_masked() < tmo) - ; -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On MIPS it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On MIPS it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} -- cgit From 186d8159f662e8b4964dca3ff5c87f06cf290a82 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Mon, 7 Apr 2014 10:11:17 +0100 Subject: MIPS: stub interrupt_init function interrupt_init is called unconditionally by the generic board code. Define a stub for it on MIPS like the enable & disable functions. Signed-off-by: Paul Burton --- arch/mips/cpu/mips32/interrupts.c | 5 +++++ arch/mips/cpu/mips64/interrupts.c | 5 +++++ 2 files changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/mips/cpu/mips32/interrupts.c b/arch/mips/cpu/mips32/interrupts.c index a7e2ed046a..275fcf5699 100644 --- a/arch/mips/cpu/mips32/interrupts.c +++ b/arch/mips/cpu/mips32/interrupts.c @@ -7,6 +7,11 @@ #include +int interrupt_init(void) +{ + return 0; +} + void enable_interrupts(void) { } diff --git a/arch/mips/cpu/mips64/interrupts.c b/arch/mips/cpu/mips64/interrupts.c index a7e2ed046a..275fcf5699 100644 --- a/arch/mips/cpu/mips64/interrupts.c +++ b/arch/mips/cpu/mips64/interrupts.c @@ -7,6 +7,11 @@ #include +int interrupt_init(void) +{ + return 0; +} + void enable_interrupts(void) { } -- cgit From 11a932fb18a497fc1b9ad0c4c0e3c5969e455a42 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Mon, 7 Apr 2014 10:11:18 +0100 Subject: MIPS: move mips_io_port_base out of board.c Move the definition of this variable out of arch/mips/lib/board.c in preparation for allowing use of generic board on MIPS, which will lead to this file not being compiled. Signed-off-by: Paul Burton --- arch/mips/lib/Makefile | 2 ++ arch/mips/lib/board.c | 6 ------ arch/mips/lib/io.c | 12 ++++++++++++ 3 files changed, 14 insertions(+), 6 deletions(-) create mode 100644 arch/mips/lib/io.c (limited to 'arch') diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index fabeb83f7e..88ef1c59ab 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -6,6 +6,8 @@ # obj-y += board.o +obj-y += io.o + obj-$(CONFIG_CMD_BOOTM) += bootm.o lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c index 9e6ba15aca..317c8258de 100644 --- a/arch/mips/lib/board.c +++ b/arch/mips/lib/board.c @@ -27,12 +27,6 @@ ulong monitor_flash_len; static char *failed = "*** failed ***\n"; -/* - * mips_io_port_base is the begin of the address space to which x86 style - * I/O ports are mapped. - */ -const unsigned long mips_io_port_base = -1; - int __board_early_init_f(void) { /* diff --git a/arch/mips/lib/io.c b/arch/mips/lib/io.c new file mode 100644 index 0000000000..b2d4a094da --- /dev/null +++ b/arch/mips/lib/io.c @@ -0,0 +1,12 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * mips_io_port_base is the begin of the address space to which x86 style + * I/O ports are mapped. + */ +const unsigned long mips_io_port_base = -1; -- cgit From a0af08b9db92c7dc8051a8cfd12d5520d85ab4a9 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Mon, 7 Apr 2014 10:11:19 +0100 Subject: MIPS: define __init_end in u-boot.lds The generic board code uses the __init_end symbol to calculate monitor_flash_len. Define said symbol for MIPS, equivalent to __image_copy_end which is used for the same purpose in arch/mips/lib/board.c. Signed-off-by: Paul Burton --- arch/mips/cpu/u-boot.lds | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/mips/cpu/u-boot.lds b/arch/mips/cpu/u-boot.lds index 4c9edf8a69..e504ea7544 100644 --- a/arch/mips/cpu/u-boot.lds +++ b/arch/mips/cpu/u-boot.lds @@ -53,6 +53,7 @@ SECTIONS . = ALIGN(4); __image_copy_end = .; + __init_end = .; .rel.dyn : { __rel_dyn_start = .; -- cgit From 9f0868fffb81ff6533d579b902058eb4f2669d40 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Mon, 7 Apr 2014 10:11:22 +0100 Subject: MIPS: allow use of generic board This patch allows MIPS boards to make use of generic board, replacing arch/mips/lib/board.c with common/board_{f,r}.c and struct bd_info with the asm-generic version. Signed-off-by: Paul Burton --- arch/mips/config.mk | 2 ++ arch/mips/include/asm/u-boot.h | 9 +++++++++ arch/mips/lib/Makefile | 2 ++ 3 files changed, 13 insertions(+) (limited to 'arch') diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 42a806252b..f4a234adbc 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -27,6 +27,8 @@ ENDIANNESS ?= -EB PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ +__HAVE_ARCH_GENERIC_BOARD := y + # # From Linux arch/mips/Makefile # diff --git a/arch/mips/include/asm/u-boot.h b/arch/mips/include/asm/u-boot.h index 985d7d808a..0eb170ded8 100644 --- a/arch/mips/include/asm/u-boot.h +++ b/arch/mips/include/asm/u-boot.h @@ -15,6 +15,13 @@ #ifndef _U_BOOT_H_ #define _U_BOOT_H_ 1 +#ifdef CONFIG_SYS_GENERIC_BOARD + +/* Use the generic board which requires a unified bd_info */ +#include + +#else /* !CONFIG_SYS_GENERIC_BOARD */ + typedef struct bd_info { unsigned int bi_baudrate; /* serial console baudrate */ unsigned long bi_arch_number; /* unique id for this board */ @@ -26,6 +33,8 @@ typedef struct bd_info { unsigned long bi_flashoffset; /* reserved area for startup monitor */ } bd_t; +#endif /* !CONFIG_SYS_GENERIC_BOARD */ + /* For image.h:image_check_target_arch() */ #define IH_ARCH_DEFAULT IH_ARCH_MIPS diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 88ef1c59ab..e483e86f6b 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -5,7 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifndef CONFIG_SYS_GENERIC_BOARD obj-y += board.o +endif obj-y += io.o obj-$(CONFIG_CMD_BOOTM) += bootm.o -- cgit From 538cf92c8c2e8ea7f78c87b5bfb2f705b4b02fa8 Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Thu, 10 Apr 2014 00:39:28 +0200 Subject: MIPS: drop incaip board This is dead hardware and no one is interested in making the necessary changes for upcoming features like generic board or driver model. Signed-off-by: Daniel Schwierzeck Cc: Wolfgang Denk --- arch/mips/cpu/mips32/incaip/Makefile | 9 - arch/mips/cpu/mips32/incaip/asc_serial.c | 300 ---- arch/mips/cpu/mips32/incaip/asc_serial.h | 177 -- arch/mips/cpu/mips32/incaip/config.mk | 8 - arch/mips/cpu/mips32/incaip/incaip_clock.c | 100 -- arch/mips/cpu/mips32/incaip/incaip_wdt.S | 55 - arch/mips/include/asm/inca-ip.h | 2430 ---------------------------- arch/mips/include/asm/u-boot-mips.h | 2 - arch/mips/lib/board.c | 3 - 9 files changed, 3084 deletions(-) delete mode 100644 arch/mips/cpu/mips32/incaip/Makefile delete mode 100644 arch/mips/cpu/mips32/incaip/asc_serial.c delete mode 100644 arch/mips/cpu/mips32/incaip/asc_serial.h delete mode 100644 arch/mips/cpu/mips32/incaip/config.mk delete mode 100644 arch/mips/cpu/mips32/incaip/incaip_clock.c delete mode 100644 arch/mips/cpu/mips32/incaip/incaip_wdt.S delete mode 100644 arch/mips/include/asm/inca-ip.h (limited to 'arch') diff --git a/arch/mips/cpu/mips32/incaip/Makefile b/arch/mips/cpu/mips32/incaip/Makefile deleted file mode 100644 index 7341a4a3e8..0000000000 --- a/arch/mips/cpu/mips32/incaip/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2011 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = incaip_wdt.o -obj-y += incaip_clock.o asc_serial.o diff --git a/arch/mips/cpu/mips32/incaip/asc_serial.c b/arch/mips/cpu/mips32/incaip/asc_serial.c deleted file mode 100644 index 6f0e4f2520..0000000000 --- a/arch/mips/cpu/mips32/incaip/asc_serial.c +++ /dev/null @@ -1,300 +0,0 @@ -/* - * (INCA) ASC UART support - */ - -#include -#include -#include -#include -#include -#include "asc_serial.h" - - -#define SET_BIT(reg, mask) reg |= (mask) -#define CLEAR_BIT(reg, mask) reg &= (~mask) -#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask) -#define SET_BITS(reg, mask) SET_BIT(reg, mask) -#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);} - -extern uint incaip_get_fpiclk(void); - -static int serial_setopt (void); - -/* pointer to ASC register base address */ -static volatile incaAsc_t *pAsc = (incaAsc_t *)INCA_IP_ASC; - -/****************************************************************************** -* -* serial_init - initialize a INCAASC channel -* -* This routine initializes the number of data bits, parity -* and set the selected baud rate. Interrupts are disabled. -* Set the modem control signals if the option is selected. -* -* RETURNS: N/A -*/ - -static int asc_serial_init(void) -{ - /* we have to set PMU.EN13 bit to enable an ASC device*/ - INCAASC_PMU_ENABLE(13); - - /* and we have to set CLC register*/ - CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS); - SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001); - - /* initialy we are in async mode */ - pAsc->asc_con = ASCCON_M_8ASYNC; - - /* select input port */ - pAsc->asc_pisel = (CONSOLE_TTY & 0x1); - - /* TXFIFO's filling level */ - SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK, - ASCTXFCON_TXFITLOFF, INCAASC_TXFIFO_FL); - /* enable TXFIFO */ - SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN); - - /* RXFIFO's filling level */ - SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK, - ASCRXFCON_RXFITLOFF, INCAASC_RXFIFO_FL); - /* enable RXFIFO */ - SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN); - - /* enable error signals */ - SET_BIT(pAsc->asc_con, ASCCON_FEN); - SET_BIT(pAsc->asc_con, ASCCON_OEN); - - /* acknowledge ASC interrupts */ - ASC_INTERRUPTS_CLEAR(INCAASC_IRQ_LINE_ALL); - - /* disable ASC interrupts */ - ASC_INTERRUPTS_DISABLE(INCAASC_IRQ_LINE_ALL); - - /* set FIFOs into the transparent mode */ - SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXTMEN); - SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXTMEN); - - /* set baud rate */ - serial_setbrg(); - - /* set the options */ - serial_setopt(); - - return 0; -} - -static void asc_serial_setbrg(void) -{ - ulong uiReloadValue, fdv; - ulong f_ASC; - - f_ASC = incaip_get_fpiclk(); - -#ifndef INCAASC_USE_FDV - fdv = 2; - uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1; -#else - fdv = INCAASC_FDV_HIGH_BAUDRATE; - uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1; -#endif /* INCAASC_USE_FDV */ - - if ( (uiReloadValue < 0) || (uiReloadValue > 8191) ) - { -#ifndef INCAASC_USE_FDV - fdv = 3; - uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1; -#else - fdv = INCAASC_FDV_LOW_BAUDRATE; - uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1; -#endif /* INCAASC_USE_FDV */ - - if ( (uiReloadValue < 0) || (uiReloadValue > 8191) ) - { - return; /* can't impossibly generate that baud rate */ - } - } - - /* Disable Baud Rate Generator; BG should only be written when R=0 */ - CLEAR_BIT(pAsc->asc_con, ASCCON_R); - -#ifndef INCAASC_USE_FDV - /* - * Disable Fractional Divider (FDE) - * Divide clock by reload-value + constant (BRS) - */ - /* FDE = 0 */ - CLEAR_BIT(pAsc->asc_con, ASCCON_FDE); - - if ( fdv == 2 ) - CLEAR_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 0 */ - else - SET_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 1 */ - -#else /* INCAASC_USE_FDV */ - - /* Enable Fractional Divider */ - SET_BIT(pAsc->asc_con, ASCCON_FDE); /* FDE = 1 */ - - /* Set fractional divider value */ - pAsc->asc_fdv = fdv & ASCFDV_VALUE_MASK; - -#endif /* INCAASC_USE_FDV */ - - /* Set reload value in BG */ - pAsc->asc_bg = uiReloadValue; - - /* Enable Baud Rate Generator */ - SET_BIT(pAsc->asc_con, ASCCON_R); /* R = 1 */ -} - -/******************************************************************************* -* -* serial_setopt - set the serial options -* -* Set the channel operating mode to that specified. Following options -* are supported: CREAD, CSIZE, PARENB, and PARODD. -* -* Note, this routine disables the transmitter. The calling routine -* may have to re-enable it. -* -* RETURNS: -* Returns 0 to indicate success, otherwise -1 is returned -*/ - -static int serial_setopt (void) -{ - ulong con; - - switch ( ASC_OPTIONS & ASCOPT_CSIZE ) - { - /* 7-bit-data */ - case ASCOPT_CS7: - con = ASCCON_M_7ASYNCPAR; /* 7-bit-data and parity bit */ - break; - - /* 8-bit-data */ - case ASCOPT_CS8: - if ( ASC_OPTIONS & ASCOPT_PARENB ) - con = ASCCON_M_8ASYNCPAR; /* 8-bit-data and parity bit */ - else - con = ASCCON_M_8ASYNC; /* 8-bit-data no parity */ - break; - - /* - * only 7 and 8-bit frames are supported - * if we don't use IOCTL extensions - */ - default: - return -1; - } - - if ( ASC_OPTIONS & ASCOPT_STOPB ) - SET_BIT(con, ASCCON_STP); /* 2 stop bits */ - else - CLEAR_BIT(con, ASCCON_STP); /* 1 stop bit */ - - if ( ASC_OPTIONS & ASCOPT_PARENB ) - SET_BIT(con, ASCCON_PEN); /* enable parity checking */ - else - CLEAR_BIT(con, ASCCON_PEN); /* disable parity checking */ - - if ( ASC_OPTIONS & ASCOPT_PARODD ) - SET_BIT(con, ASCCON_ODD); /* odd parity */ - else - CLEAR_BIT(con, ASCCON_ODD); /* even parity */ - - if ( ASC_OPTIONS & ASCOPT_CREAD ) - SET_BIT(pAsc->asc_whbcon, ASCWHBCON_SETREN); /* Receiver enable */ - - pAsc->asc_con |= con; - - return 0; -} - -static void asc_serial_putc(const char c) -{ - uint txFl = 0; - - if (c == '\n') serial_putc ('\r'); - - /* check do we have a free space in the TX FIFO */ - /* get current filling level */ - do - { - txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF; - } - while ( txFl == INCAASC_TXFIFO_FULL ); - - pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */ - - /* check for errors */ - if ( pAsc->asc_con & ASCCON_OE ) - { - SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE); - return; - } -} - -static int asc_serial_getc(void) -{ - ulong symbol_mask; - char c; - - while (!serial_tstc()); - - symbol_mask = - ((ASC_OPTIONS & ASCOPT_CSIZE) == ASCOPT_CS7) ? (0x7f) : (0xff); - - c = (char)(pAsc->asc_rbuf & symbol_mask); - - return c; -} - -static int asc_serial_tstc(void) -{ - int res = 1; - - if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 ) - { - res = 0; - } - else if ( pAsc->asc_con & ASCCON_FE ) - { - SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE); - res = 0; - } - else if ( pAsc->asc_con & ASCCON_PE ) - { - SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRPE); - res = 0; - } - else if ( pAsc->asc_con & ASCCON_OE ) - { - SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE); - res = 0; - } - - return res; -} - -static struct serial_device asc_serial_drv = { - .name = "asc_serial", - .start = asc_serial_init, - .stop = NULL, - .setbrg = asc_serial_setbrg, - .putc = asc_serial_putc, - .puts = default_serial_puts, - .getc = asc_serial_getc, - .tstc = asc_serial_tstc, -}; - -void asc_serial_initialize(void) -{ - serial_register(&asc_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &asc_serial_drv; -} diff --git a/arch/mips/cpu/mips32/incaip/asc_serial.h b/arch/mips/cpu/mips32/incaip/asc_serial.h deleted file mode 100644 index 7ffdcfaf8b..0000000000 --- a/arch/mips/cpu/mips32/incaip/asc_serial.h +++ /dev/null @@ -1,177 +0,0 @@ -/* incaAscSio.h - (INCA) ASC UART tty driver header */ - -#ifndef __INCincaAscSioh -#define __INCincaAscSioh - -#include - -/* channel operating modes */ -#define ASCOPT_CSIZE 0x00000003 -#define ASCOPT_CS7 0x00000001 -#define ASCOPT_CS8 0x00000002 -#define ASCOPT_PARENB 0x00000004 -#define ASCOPT_STOPB 0x00000008 -#define ASCOPT_PARODD 0x00000010 -#define ASCOPT_CREAD 0x00000020 - -#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8) - -/* ASC input select (0 or 1) */ -#define CONSOLE_TTY 0 - -/* use fractional divider for baudrate settings */ -#define INCAASC_USE_FDV - -#ifdef INCAASC_USE_FDV - #define INCAASC_FDV_LOW_BAUDRATE 71 - #define INCAASC_FDV_HIGH_BAUDRATE 453 -#endif /*INCAASC_USE_FDV*/ - - -#define INCAASC_TXFIFO_FL 1 -#define INCAASC_RXFIFO_FL 1 -#define INCAASC_TXFIFO_FULL 16 - -/* interrupt lines masks for the ASC device interrupts*/ -/* change these macroses if it's necessary */ -#define INCAASC_IRQ_LINE_ALL 0x000F0000 /* all IRQs */ - -#define INCAASC_IRQ_LINE_TIR 0x00010000 /* TIR - Tx */ -#define INCAASC_IRQ_LINE_RIR 0x00020000 /* RIR - Rx */ -#define INCAASC_IRQ_LINE_EIR 0x00040000 /* EIR - Err */ -#define INCAASC_IRQ_LINE_TBIR 0x00080000 /* TBIR - Tx Buf*/ - -/* interrupt controller access macros */ -#define ASC_INTERRUPTS_ENABLE(X) \ - *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) |= X; -#define ASC_INTERRUPTS_DISABLE(X) \ - *((volatile unsigned int*) INCA_IP_ICU_IM2_IER) &= ~X; -#define ASC_INTERRUPTS_CLEAR(X) \ - *((volatile unsigned int*) INCA_IP_ICU_IM2_ISR) = X; - -/* CLC register's bits and bitfields */ -#define ASCCLC_DISR 0x00000001 -#define ASCCLC_DISS 0x00000002 -#define ASCCLC_RMCMASK 0x0000FF00 -#define ASCCLC_RMCOFFSET 8 - -/* CON register's bits and bitfields */ -#define ASCCON_MODEMASK 0x0007 - #define ASCCON_M_8SYNC 0x0 - #define ASCCON_M_8ASYNC 0x1 - #define ASCCON_M_8IRDAASYNC 0x2 - #define ASCCON_M_7ASYNCPAR 0x3 - #define ASCCON_M_9ASYNC 0x4 - #define ASCCON_M_8WAKEUPASYNC 0x5 - #define ASCCON_M_8ASYNCPAR 0x7 -#define ASCCON_STP 0x0008 -#define ASCCON_REN 0x0010 -#define ASCCON_PEN 0x0020 -#define ASCCON_FEN 0x0040 -#define ASCCON_OEN 0x0080 -#define ASCCON_PE 0x0100 -#define ASCCON_FE 0x0200 -#define ASCCON_OE 0x0400 -#define ASCCON_FDE 0x0800 -#define ASCCON_ODD 0x1000 -#define ASCCON_BRS 0x2000 -#define ASCCON_LB 0x4000 -#define ASCCON_R 0x8000 - -/* WHBCON register's bits and bitfields */ -#define ASCWHBCON_CLRREN 0x0010 -#define ASCWHBCON_SETREN 0x0020 -#define ASCWHBCON_CLRPE 0x0100 -#define ASCWHBCON_CLRFE 0x0200 -#define ASCWHBCON_CLROE 0x0400 -#define ASCWHBCON_SETPE 0x0800 -#define ASCWHBCON_SETFE 0x1000 -#define ASCWHBCON_SETOE 0x2000 - -/* ABCON register's bits and bitfields */ -#define ASCABCON_ABEN 0x0001 -#define ASCABCON_AUREN 0x0002 -#define ASCABCON_ABSTEN 0x0004 -#define ASCABCON_ABDETEN 0x0008 -#define ASCABCON_FCDETEN 0x0010 -#define ASCABCON_EMMASK 0x0300 - #define ASCABCON_EMOFF 8 - #define ASCABCON_EM_DISAB 0x0 - #define ASCABCON_EM_DURAB 0x1 - #define ASCABCON_EM_ALWAYS 0x2 -#define ASCABCON_TXINV 0x0400 -#define ASCABCON_RXINV 0x0800 - -/* FDV register mask, offset and bitfields*/ -#define ASCFDV_VALUE_MASK 0x000001FF - -/* WHBABCON register's bits and bitfields */ -#define ASCWHBABCON_SETABEN 0x0001 -#define ASCWHBABCON_CLRABEN 0x0002 - -/* ABSTAT register's bits and bitfields */ -#define ASCABSTAT_FCSDET 0x0001 -#define ASCABSTAT_FCCDET 0x0002 -#define ASCABSTAT_SCSDET 0x0004 -#define ASCABSTAT_SCCDET 0x0008 -#define ASCABSTAT_DETWAIT 0x0010 - -/* WHBABSTAT register's bits and bitfields */ -#define ASCWHBABSTAT_CLRFCSDET 0x0001 -#define ASCWHBABSTAT_SETFCSDET 0x0002 -#define ASCWHBABSTAT_CLRFCCDET 0x0004 -#define ASCWHBABSTAT_SETFCCDET 0x0008 -#define ASCWHBABSTAT_CLRSCSDET 0x0010 -#define ASCWHBABSTAT_SETSCSDET 0x0020 -#define ASCWHBABSTAT_SETSCCDET 0x0040 -#define ASCWHBABSTAT_CLRSCCDET 0x0080 -#define ASCWHBABSTAT_CLRDETWAIT 0x0100 -#define ASCWHBABSTAT_SETDETWAIT 0x0200 - -/* TXFCON register's bits and bitfields */ -#define ASCTXFCON_TXFEN 0x0001 -#define ASCTXFCON_TXFFLU 0x0002 -#define ASCTXFCON_TXTMEN 0x0004 -#define ASCTXFCON_TXFITLMASK 0x3F00 -#define ASCTXFCON_TXFITLOFF 8 - -/* RXFCON register's bits and bitfields */ -#define ASCRXFCON_RXFEN 0x0001 -#define ASCRXFCON_RXFFLU 0x0002 -#define ASCRXFCON_RXTMEN 0x0004 -#define ASCRXFCON_RXFITLMASK 0x3F00 -#define ASCRXFCON_RXFITLOFF 8 - -/* FSTAT register's bits and bitfields */ -#define ASCFSTAT_RXFFLMASK 0x003F -#define ASCFSTAT_TXFFLMASK 0x3F00 -#define ASCFSTAT_TXFFLOFF 8 - -#define INCAASC_PMU_ENABLE(BIT) *((volatile ulong*)0xBF102000) |= (0x1 << BIT); - -typedef struct /* incaAsc_t */ -{ - volatile unsigned long asc_clc; /*0x0000*/ - volatile unsigned long asc_pisel; /*0x0004*/ - volatile unsigned long asc_rsvd1[2]; /* for mapping */ /*0x0008*/ - volatile unsigned long asc_con; /*0x0010*/ - volatile unsigned long asc_bg; /*0x0014*/ - volatile unsigned long asc_fdv; /*0x0018*/ - volatile unsigned long asc_pmw; /* not used */ /*0x001C*/ - volatile unsigned long asc_tbuf; /*0x0020*/ - volatile unsigned long asc_rbuf; /*0x0024*/ - volatile unsigned long asc_rsvd2[2]; /* for mapping */ /*0x0028*/ - volatile unsigned long asc_abcon; /*0x0030*/ - volatile unsigned long asc_abstat; /* not used */ /*0x0034*/ - volatile unsigned long asc_rsvd3[2]; /* for mapping */ /*0x0038*/ - volatile unsigned long asc_rxfcon; /*0x0040*/ - volatile unsigned long asc_txfcon; /*0x0044*/ - volatile unsigned long asc_fstat; /*0x0048*/ - volatile unsigned long asc_rsvd4; /* for mapping */ /*0x004C*/ - volatile unsigned long asc_whbcon; /*0x0050*/ - volatile unsigned long asc_whbabcon; /*0x0054*/ - volatile unsigned long asc_whbabstat; /* not used */ /*0x0058*/ - -} incaAsc_t; - -#endif /* __INCincaAscSioh */ diff --git a/arch/mips/cpu/mips32/incaip/config.mk b/arch/mips/cpu/mips32/incaip/config.mk deleted file mode 100644 index 5c89129d8c..0000000000 --- a/arch/mips/cpu/mips32/incaip/config.mk +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2011 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_CPPFLAGS += -mtune=4kc diff --git a/arch/mips/cpu/mips32/incaip/incaip_clock.c b/arch/mips/cpu/mips32/incaip/incaip_clock.c deleted file mode 100644 index efada9f6f8..0000000000 --- a/arch/mips/cpu/mips32/incaip/incaip_clock.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - - -/******************************************************************************* -* -* get_cpuclk - returns the frequency of the CPU. -* -* Gets the value directly from the INCA-IP hardware. -* -* RETURNS: -* 150.000.000 for 150 MHz -* 133.333.333 for 133 MHz (= 400MHz/3) -* 100.000.000 for 100 MHz (= 400MHz/4) -* NOTE: -* This functions should be used by the hardware driver to get the correct -* frequency of the CPU. Don't use the macros, which are set to init the CPU -* frequency in the ROM code. -*/ -uint incaip_get_cpuclk (void) -{ - /*-------------------------------------------------------------------------*/ - /* CPU Clock Input Multiplexer (MUX I) */ - /* Multiplexer MUX I selects the maximum input clock to the CPU. */ - /*-------------------------------------------------------------------------*/ - if (*((volatile ulong *) INCA_IP_CGU_CGU_MUXCR) & - INCA_IP_CGU_CGU_MUXCR_MUXI) { - /* MUX I set to 150 MHz clock */ - return 150000000; - } else { - /* MUX I set to 100/133 MHz clock */ - if (*((volatile ulong *) INCA_IP_CGU_CGU_DIVCR) & 0x40) { - /* Division value is 1/3, maximum CPU operating */ - /* frequency is 133.3 MHz */ - return 133333333; - } else { - /* Division value is 1/4, maximum CPU operating */ - /* frequency is 100 MHz */ - return 100000000; - } - } -} - -/******************************************************************************* -* -* get_fpiclk - returns the frequency of the FPI bus. -* -* Gets the value directly from the INCA-IP hardware. -* -* RETURNS: Frquency in Hz -* -* NOTE: -* This functions should be used by the hardware driver to get the correct -* frequency of the CPU. Don't use the macros, which are set to init the CPU -* frequency in the ROM code. -* The calculation for the -*/ -uint incaip_get_fpiclk (void) -{ - uint clkCPU; - - clkCPU = incaip_get_cpuclk (); - - switch (*((volatile ulong *) INCA_IP_CGU_CGU_DIVCR) & 0xC) { - case 0x4: - return clkCPU >> 1; /* devided by 2 */ - break; - case 0x8: - return clkCPU >> 2; /* devided by 4 */ - break; - default: - return clkCPU; - break; - } -} - -int incaip_set_cpuclk (void) -{ - extern void ebu_init(long); - extern void cgu_init(long); - extern void sdram_init(long); - char tmp[64]; - ulong cpuclk; - - if (getenv_f("cpuclk", tmp, sizeof (tmp)) > 0) { - cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000; - cgu_init (cpuclk); - ebu_init (cpuclk); - sdram_init (cpuclk); - } - - return 0; -} diff --git a/arch/mips/cpu/mips32/incaip/incaip_wdt.S b/arch/mips/cpu/mips32/incaip/incaip_wdt.S deleted file mode 100644 index b15320a57c..0000000000 --- a/arch/mips/cpu/mips32/incaip/incaip_wdt.S +++ /dev/null @@ -1,55 +0,0 @@ -/* - * INCA-IP Watchdog timer management code. - * - * Copyright (c) 2003 Wolfgang Denk - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include -#include - - -#define WD_BASE 0xb8000000 -#define WD_CON0(value) 0x0020(value) -#define WD_CON1(value) 0x0024(value) -#define WD_DISABLE 0x00000008 -#define WD_ENABLE 0x00000000 -#define WD_WRITE_PW 0xFFFC00F8 -#define WD_WRITE_ENDINIT 0xFFFC00F3 -#define WD_WRITE_INIT 0xFFFC00F2 - - - .globl disable_incaip_wdt -disable_incaip_wdt: - li t0, WD_BASE - - /* Calculate password. - */ - lw t2, WD_CON1(t0) - and t2, 0xC - - lw t3, WD_CON0(t0) - and t3, 0xFFFFFF01 - - or t3, t2 - or t3, 0xF0 - - sw t3, WD_CON0(t0) /* write password */ - - /* Clear ENDINIT. - */ - li t1, WD_WRITE_INIT - sw t1, WD_CON0(t0) - - - li t1, WD_DISABLE - sw t1, WD_CON1(t0) /* disable watchdog */ - li t1, WD_WRITE_PW - sw t1, WD_CON0(t0) /* write password */ - li t1, WD_WRITE_ENDINIT - sw t1, WD_CON0(t0) /* end command */ - - jr ra - nop diff --git a/arch/mips/include/asm/inca-ip.h b/arch/mips/include/asm/inca-ip.h deleted file mode 100644 index 5f03e2aa20..0000000000 --- a/arch/mips/include/asm/inca-ip.h +++ /dev/null @@ -1,2430 +0,0 @@ -/****************************************************************************** - Copyright (c) 2002, Infineon Technologies. All rights reserved. - - No Warranty - Because the program is licensed free of charge, there is no warranty for - the program, to the extent permitted by applicable law. Except when - otherwise stated in writing the copyright holders and/or other parties - provide the program "as is" without warranty of any kind, either - expressed or implied, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose. The - entire risk as to the quality and performance of the program is with - you. should the program prove defective, you assume the cost of all - necessary servicing, repair or correction. - - In no event unless required by applicable law or agreed to in writing - will any copyright holder, or any other party who may modify and/or - redistribute the program as permitted above, be liable to you for - damages, including any general, special, incidental or consequential - damages arising out of the use or inability to use the program - (including but not limited to loss of data or data being rendered - inaccurate or losses sustained by you or third parties or a failure of - the program to operate with any other programs), even if such holder or - other party has been advised of the possibility of such damages. -******************************************************************************/ - - -/***********************************************************************/ -/* Module : WDT register address and bits */ -/***********************************************************************/ - -#define INCA_IP_WDT (0xB8000000) -/***********************************************************************/ - - -/***Reset Status Register Power On***/ -#define INCA_IP_WDT_RST_SR ((volatile u32*)(INCA_IP_WDT+ 0x0014)) - -/***Reset Request Register***/ -#define INCA_IP_WDT_RST_REQ ((volatile u32*)(INCA_IP_WDT+ 0x0010)) -#define INCA_IP_WDT_RST_REQ_SWBOOT (1 << 24) -#define INCA_IP_WDT_RST_REQ_SWCFG (1 << 16) -#define INCA_IP_WDT_RST_REQ_RRPHY (1 << 5) -#define INCA_IP_WDT_RST_REQ_RRHSP (1 << 4) -#define INCA_IP_WDT_RST_REQ_RRFPI (1 << 3) -#define INCA_IP_WDT_RST_REQ_RREXT (1 << 2) -#define INCA_IP_WDT_RST_REQ_RRDSP (1 << 1) -#define INCA_IP_WDT_RST_REQ_RRCPU (1 << 0) - -/***NMI Status Register***/ -#define INCA_IP_WDT_NMISR ((volatile u32*)(INCA_IP_WDT+ 0x002C)) -#define INCA_IP_WDT_NMISR_NMIWDT (1 << 2) -#define INCA_IP_WDT_NMISR_NMIPLL (1 << 1) -#define INCA_IP_WDT_NMISR_NMIEXT (1 << 0) - -/***Manufacturer Identification Register***/ -#define INCA_IP_WDT_MANID ((volatile u32*)(INCA_IP_WDT+ 0x0070)) -#define INCA_IP_WDT_MANID_MANUF (value) (((( 1 << 11) - 1) & (value)) << 5) - -/***Chip Identification Register***/ -#define INCA_IP_WDT_CHIPID ((volatile u32*)(INCA_IP_WDT+ 0x0074)) -#define INCA_IP_WDT_CHIPID_VERSION (value) (((( 1 << 4) - 1) & (value)) << 28) -#define INCA_IP_WDT_CHIPID_PART_NUMBER (value) (((( 1 << 16) - 1) & (value)) << 12) -#define INCA_IP_WDT_CHIPID_MANID (value) (((( 1 << 11) - 1) & (value)) << 1) - -/***Redesign Tracing Identification Register***/ -#define INCA_IP_WDT_RTID ((volatile u32*)(INCA_IP_WDT+ 0x0078)) -#define INCA_IP_WDT_RTID_LC (1 << 15) -#define INCA_IP_WDT_RTID_RIX (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Watchdog Timer Control Register 0***/ -#define INCA_IP_WDT_WDT_CON0 ((volatile u32*)(INCA_IP_WDT+ 0x0020)) - -/***Watchdog Timer Control Register 1***/ -#define INCA_IP_WDT_WDT_CON1 ((volatile u32*)(INCA_IP_WDT+ 0x0024)) -#define INCA_IP_WDT_WDT_CON1_WDTDR (1 << 3) -#define INCA_IP_WDT_WDT_CON1_WDTIR (1 << 2) - -/***Watchdog Timer Status Register***/ -#define INCA_IP_WDT_WDT_SR ((volatile u32*)(INCA_IP_WDT+ 0x0028)) -#define INCA_IP_WDT_WDT_SR_WDTTIM (value) (((( 1 << 16) - 1) & (value)) << 16) -#define INCA_IP_WDT_WDT_SR_WDTPR (1 << 5) -#define INCA_IP_WDT_WDT_SR_WDTTO (1 << 4) -#define INCA_IP_WDT_WDT_SR_WDTDS (1 << 3) -#define INCA_IP_WDT_WDT_SR_WDTIS (1 << 2) -#define INCA_IP_WDT_WDT_SR_WDTOE (1 << 1) -#define INCA_IP_WDT_WDT_SR_WDTAE (1 << 0) - -/***********************************************************************/ -/* Module : CGU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_CGU (0xBF107000) -/***********************************************************************/ - - -/***CGU PLL1 Control Register***/ -#define INCA_IP_CGU_CGU_PLL1CR ((volatile u32*)(INCA_IP_CGU+ 0x0008)) -#define INCA_IP_CGU_CGU_PLL1CR_SWRST (1 << 31) -#define INCA_IP_CGU_CGU_PLL1CR_EN (1 << 30) -#define INCA_IP_CGU_CGU_PLL1CR_NDIV (value) (((( 1 << 6) - 1) & (value)) << 16) -#define INCA_IP_CGU_CGU_PLL1CR_MDIV (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***CGU PLL0 Control Register***/ -#define INCA_IP_CGU_CGU_PLL0CR ((volatile u32*)(INCA_IP_CGU+ 0x0000)) -#define INCA_IP_CGU_CGU_PLL0CR_SWRST (1 << 31) -#define INCA_IP_CGU_CGU_PLL0CR_EN (1 << 30) -#define INCA_IP_CGU_CGU_PLL0CR_NDIV (value) (((( 1 << 6) - 1) & (value)) << 16) -#define INCA_IP_CGU_CGU_PLL0CR_MDIV (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***CGU PLL0 Status Register***/ -#define INCA_IP_CGU_CGU_PLL0SR ((volatile u32*)(INCA_IP_CGU+ 0x0004)) -#define INCA_IP_CGU_CGU_PLL0SR_LOCK (1 << 31) -#define INCA_IP_CGU_CGU_PLL0SR_RCF (1 << 29) -#define INCA_IP_CGU_CGU_PLL0SR_PLLBYP (1 << 15) - -/***CGU PLL1 Status Register***/ -#define INCA_IP_CGU_CGU_PLL1SR ((volatile u32*)(INCA_IP_CGU+ 0x000C)) -#define INCA_IP_CGU_CGU_PLL1SR_LOCK (1 << 31) -#define INCA_IP_CGU_CGU_PLL1SR_RCF (1 << 29) -#define INCA_IP_CGU_CGU_PLL1SR_PLLBYP (1 << 15) - -/***CGU Divider Control Register***/ -#define INCA_IP_CGU_CGU_DIVCR ((volatile u32*)(INCA_IP_CGU+ 0x0010)) - -/***CGU Multiplexer Control Register***/ -#define INCA_IP_CGU_CGU_MUXCR ((volatile u32*)(INCA_IP_CGU+ 0x0014)) -#define INCA_IP_CGU_CGU_MUXCR_SWRST (1 << 31) -#define INCA_IP_CGU_CGU_MUXCR_MUXII (1 << 1) -#define INCA_IP_CGU_CGU_MUXCR_MUXI (1 << 0) - -/***CGU Fractional Divider Control Register***/ -#define INCA_IP_CGU_CGU_FDCR ((volatile u32*)(INCA_IP_CGU+ 0x0018)) -#define INCA_IP_CGU_CGU_FDCR_FDEN (1 << 31) -#define INCA_IP_CGU_CGU_FDCR_INTEGER (value) (((( 1 << 12) - 1) & (value)) << 16) -#define INCA_IP_CGU_CGU_FDCR_FRACTION (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : PMU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_PMU (0xBF102000) -/***********************************************************************/ - - -/***PM Global Enable Register***/ -#define INCA_IP_PMU_PM_GEN ((volatile u32*)(INCA_IP_PMU+ 0x0000)) -#define INCA_IP_PMU_PM_GEN_EN16 (1 << 16) -#define INCA_IP_PMU_PM_GEN_EN15 (1 << 15) -#define INCA_IP_PMU_PM_GEN_EN14 (1 << 14) -#define INCA_IP_PMU_PM_GEN_EN13 (1 << 13) -#define INCA_IP_PMU_PM_GEN_EN12 (1 << 12) -#define INCA_IP_PMU_PM_GEN_EN11 (1 << 11) -#define INCA_IP_PMU_PM_GEN_EN10 (1 << 10) -#define INCA_IP_PMU_PM_GEN_EN9 (1 << 9) -#define INCA_IP_PMU_PM_GEN_EN8 (1 << 8) -#define INCA_IP_PMU_PM_GEN_EN7 (1 << 7) -#define INCA_IP_PMU_PM_GEN_EN6 (1 << 6) -#define INCA_IP_PMU_PM_GEN_EN5 (1 << 5) -#define INCA_IP_PMU_PM_GEN_EN4 (1 << 4) -#define INCA_IP_PMU_PM_GEN_EN3 (1 << 3) -#define INCA_IP_PMU_PM_GEN_EN2 (1 << 2) -#define INCA_IP_PMU_PM_GEN_EN0 (1 << 0) - -/***PM Power Down Enable Register***/ -#define INCA_IP_PMU_PM_PDEN ((volatile u32*)(INCA_IP_PMU+ 0x0008)) -#define INCA_IP_PMU_PM_PDEN_EN16 (1 << 16) -#define INCA_IP_PMU_PM_PDEN_EN15 (1 << 15) -#define INCA_IP_PMU_PM_PDEN_EN14 (1 << 14) -#define INCA_IP_PMU_PM_PDEN_EN13 (1 << 13) -#define INCA_IP_PMU_PM_PDEN_EN12 (1 << 12) -#define INCA_IP_PMU_PM_PDEN_EN11 (1 << 11) -#define INCA_IP_PMU_PM_PDEN_EN10 (1 << 10) -#define INCA_IP_PMU_PM_PDEN_EN9 (1 << 9) -#define INCA_IP_PMU_PM_PDEN_EN8 (1 << 8) -#define INCA_IP_PMU_PM_PDEN_EN7 (1 << 7) -#define INCA_IP_PMU_PM_PDEN_EN5 (1 << 5) -#define INCA_IP_PMU_PM_PDEN_EN4 (1 << 4) -#define INCA_IP_PMU_PM_PDEN_EN3 (1 << 3) -#define INCA_IP_PMU_PM_PDEN_EN2 (1 << 2) -#define INCA_IP_PMU_PM_PDEN_EN0 (1 << 0) - -/***PM Wake-Up from Power Down Register***/ -#define INCA_IP_PMU_PM_WUP ((volatile u32*)(INCA_IP_PMU+ 0x0010)) -#define INCA_IP_PMU_PM_WUP_WUP16 (1 << 16) -#define INCA_IP_PMU_PM_WUP_WUP15 (1 << 15) -#define INCA_IP_PMU_PM_WUP_WUP14 (1 << 14) -#define INCA_IP_PMU_PM_WUP_WUP13 (1 << 13) -#define INCA_IP_PMU_PM_WUP_WUP12 (1 << 12) -#define INCA_IP_PMU_PM_WUP_WUP11 (1 << 11) -#define INCA_IP_PMU_PM_WUP_WUP10 (1 << 10) -#define INCA_IP_PMU_PM_WUP_WUP9 (1 << 9) -#define INCA_IP_PMU_PM_WUP_WUP8 (1 << 8) -#define INCA_IP_PMU_PM_WUP_WUP7 (1 << 7) -#define INCA_IP_PMU_PM_WUP_WUP5 (1 << 5) -#define INCA_IP_PMU_PM_WUP_WUP4 (1 << 4) -#define INCA_IP_PMU_PM_WUP_WUP3 (1 << 3) -#define INCA_IP_PMU_PM_WUP_WUP2 (1 << 2) -#define INCA_IP_PMU_PM_WUP_WUP0 (1 << 0) - -/***PM Control Register***/ -#define INCA_IP_PMU_PM_CR ((volatile u32*)(INCA_IP_PMU+ 0x0014)) -#define INCA_IP_PMU_PM_CR_AWEN (1 << 31) -#define INCA_IP_PMU_PM_CR_SWRST (1 << 30) -#define INCA_IP_PMU_PM_CR_SWCR (1 << 2) -#define INCA_IP_PMU_PM_CR_CRD (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : BCU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_BCU (0xB8000100) -/***********************************************************************/ - - -/***BCU Control Register (0010H)***/ -#define INCA_IP_BCU_BCU_CON ((volatile u32*)(INCA_IP_BCU+ 0x0010)) -#define INCA_IP_BCU_BCU_CON_SPC (value) (((( 1 << 8) - 1) & (value)) << 24) -#define INCA_IP_BCU_BCU_CON_SPE (1 << 19) -#define INCA_IP_BCU_BCU_CON_PSE (1 << 18) -#define INCA_IP_BCU_BCU_CON_DBG (1 << 16) -#define INCA_IP_BCU_BCU_CON_TOUT (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***BCU Error Control Capture Register (0020H)***/ -#define INCA_IP_BCU_BCU_ECON ((volatile u32*)(INCA_IP_BCU+ 0x0020)) -#define INCA_IP_BCU_BCU_ECON_TAG (value) (((( 1 << 4) - 1) & (value)) << 24) -#define INCA_IP_BCU_BCU_ECON_RDN (1 << 23) -#define INCA_IP_BCU_BCU_ECON_WRN (1 << 22) -#define INCA_IP_BCU_BCU_ECON_SVM (1 << 21) -#define INCA_IP_BCU_BCU_ECON_ACK (value) (((( 1 << 2) - 1) & (value)) << 19) -#define INCA_IP_BCU_BCU_ECON_ABT (1 << 18) -#define INCA_IP_BCU_BCU_ECON_RDY (1 << 17) -#define INCA_IP_BCU_BCU_ECON_TOUT (1 << 16) -#define INCA_IP_BCU_BCU_ECON_ERRCNT (value) (((( 1 << 16) - 1) & (value)) << 0) -#define INCA_IP_BCU_BCU_ECON_OPC (value) (((( 1 << 4) - 1) & (value)) << 28) - -/***BCU Error Address Capture Register (0024 H)***/ -#define INCA_IP_BCU_BCU_EADD ((volatile u32*)(INCA_IP_BCU+ 0x0024)) -#define INCA_IP_BCU_BCU_EADD_FPIADR - -/***BCU Error Data Capture Register (0028H)***/ -#define INCA_IP_BCU_BCU_EDAT ((volatile u32*)(INCA_IP_BCU+ 0x0028)) -#define INCA_IP_BCU_BCU_EDAT_FPIDAT - -/***********************************************************************/ -/* Module : MBC register address and bits */ -/***********************************************************************/ - -#define INCA_IP_MBC (0xBF103000) -/***********************************************************************/ - - -/***Mailbox CPU Configuration Register***/ -#define INCA_IP_MBC_MBC_CFG ((volatile u32*)(INCA_IP_MBC+ 0x0080)) -#define INCA_IP_MBC_MBC_CFG_SWAP (value) (((( 1 << 2) - 1) & (value)) << 6) -#define INCA_IP_MBC_MBC_CFG_RES (1 << 5) -#define INCA_IP_MBC_MBC_CFG_FWID (value) (((( 1 << 4) - 1) & (value)) << 1) -#define INCA_IP_MBC_MBC_CFG_SIZE (1 << 0) - -/***Mailbox CPU Interrupt Status Register***/ -#define INCA_IP_MBC_MBC_ISR ((volatile u32*)(INCA_IP_MBC+ 0x0084)) -#define INCA_IP_MBC_MBC_ISR_B3DA (1 << 31) -#define INCA_IP_MBC_MBC_ISR_B2DA (1 << 30) -#define INCA_IP_MBC_MBC_ISR_B1E (1 << 29) -#define INCA_IP_MBC_MBC_ISR_B0E (1 << 28) -#define INCA_IP_MBC_MBC_ISR_WDT (1 << 27) -#define INCA_IP_MBC_MBC_ISR_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Mask Register***/ -#define INCA_IP_MBC_MBC_MSK ((volatile u32*)(INCA_IP_MBC+ 0x0088)) -#define INCA_IP_MBC_MBC_MSK_B3DA (1 << 31) -#define INCA_IP_MBC_MBC_MSK_B2DA (1 << 30) -#define INCA_IP_MBC_MBC_MSK_B1E (1 << 29) -#define INCA_IP_MBC_MBC_MSK_B0E (1 << 28) -#define INCA_IP_MBC_MBC_MSK_WDT (1 << 27) -#define INCA_IP_MBC_MBC_MSK_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Mask 01 Register***/ -#define INCA_IP_MBC_MBC_MSK01 ((volatile u32*)(INCA_IP_MBC+ 0x008C)) -#define INCA_IP_MBC_MBC_MSK01_B3DA (1 << 31) -#define INCA_IP_MBC_MBC_MSK01_B2DA (1 << 30) -#define INCA_IP_MBC_MBC_MSK01_B1E (1 << 29) -#define INCA_IP_MBC_MBC_MSK01_B0E (1 << 28) -#define INCA_IP_MBC_MBC_MSK01_WDT (1 << 27) -#define INCA_IP_MBC_MBC_MSK01_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Mask 10 Register***/ -#define INCA_IP_MBC_MBC_MSK10 ((volatile u32*)(INCA_IP_MBC+ 0x0090)) -#define INCA_IP_MBC_MBC_MSK10_B3DA (1 << 31) -#define INCA_IP_MBC_MBC_MSK10_B2DA (1 << 30) -#define INCA_IP_MBC_MBC_MSK10_B1E (1 << 29) -#define INCA_IP_MBC_MBC_MSK10_B0E (1 << 28) -#define INCA_IP_MBC_MBC_MSK10_WDT (1 << 27) -#define INCA_IP_MBC_MBC_MSK10_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Short Command Register***/ -#define INCA_IP_MBC_MBC_CMD ((volatile u32*)(INCA_IP_MBC+ 0x0094)) -#define INCA_IP_MBC_MBC_CMD_CS270 (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***Mailbox CPU Input Data of Buffer 0***/ -#define INCA_IP_MBC_MBC_ID0 ((volatile u32*)(INCA_IP_MBC+ 0x0000)) -#define INCA_IP_MBC_MBC_ID0_INDATA - -/***Mailbox CPU Input Data of Buffer 1***/ -#define INCA_IP_MBC_MBC_ID1 ((volatile u32*)(INCA_IP_MBC+ 0x0020)) -#define INCA_IP_MBC_MBC_ID1_INDATA - -/***Mailbox CPU Output Data of Buffer 2***/ -#define INCA_IP_MBC_MBC_OD2 ((volatile u32*)(INCA_IP_MBC+ 0x0040)) -#define INCA_IP_MBC_MBC_OD2_OUTDATA - -/***Mailbox CPU Output Data of Buffer 3***/ -#define INCA_IP_MBC_MBC_OD3 ((volatile u32*)(INCA_IP_MBC+ 0x0060)) -#define INCA_IP_MBC_MBC_OD3_OUTDATA - -/***Mailbox CPU Control Register of Buffer 0***/ -#define INCA_IP_MBC_MBC_CR0 ((volatile u32*)(INCA_IP_MBC+ 0x0004)) -#define INCA_IP_MBC_MBC_CR0_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Control Register of Buffer 1***/ -#define INCA_IP_MBC_MBC_CR1 ((volatile u32*)(INCA_IP_MBC+ 0x0024)) -#define INCA_IP_MBC_MBC_CR1_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Control Register of Buffer 2***/ -#define INCA_IP_MBC_MBC_CR2 ((volatile u32*)(INCA_IP_MBC+ 0x0044)) -#define INCA_IP_MBC_MBC_CR2_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Control Register of Buffer 3***/ -#define INCA_IP_MBC_MBC_CR3 ((volatile u32*)(INCA_IP_MBC+ 0x0064)) -#define INCA_IP_MBC_MBC_CR3_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Free Space of Buffer 0***/ -#define INCA_IP_MBC_MBC_FS0 ((volatile u32*)(INCA_IP_MBC+ 0x0008)) -#define INCA_IP_MBC_MBC_FS0_FS - -/***Mailbox CPU Free Space of Buffer 1***/ -#define INCA_IP_MBC_MBC_FS1 ((volatile u32*)(INCA_IP_MBC+ 0x0028)) -#define INCA_IP_MBC_MBC_FS1_FS - -/***Mailbox CPU Free Space of Buffer 2***/ -#define INCA_IP_MBC_MBC_FS2 ((volatile u32*)(INCA_IP_MBC+ 0x0048)) -#define INCA_IP_MBC_MBC_FS2_FS - -/***Mailbox CPU Free Space of Buffer 3***/ -#define INCA_IP_MBC_MBC_FS3 ((volatile u32*)(INCA_IP_MBC+ 0x0068)) -#define INCA_IP_MBC_MBC_FS3_FS - -/***Mailbox CPU Data Available in Buffer 0***/ -#define INCA_IP_MBC_MBC_DA0 ((volatile u32*)(INCA_IP_MBC+ 0x000C)) -#define INCA_IP_MBC_MBC_DA0_DA - -/***Mailbox CPU Data Available in Buffer 1***/ -#define INCA_IP_MBC_MBC_DA1 ((volatile u32*)(INCA_IP_MBC+ 0x002C)) -#define INCA_IP_MBC_MBC_DA1_DA - -/***Mailbox CPU Data Available in Buffer 2***/ -#define INCA_IP_MBC_MBC_DA2 ((volatile u32*)(INCA_IP_MBC+ 0x004C)) -#define INCA_IP_MBC_MBC_DA2_DA - -/***Mailbox CPU Data Available in Buffer 3***/ -#define INCA_IP_MBC_MBC_DA3 ((volatile u32*)(INCA_IP_MBC+ 0x006C)) -#define INCA_IP_MBC_MBC_DA3_DA - -/***Mailbox CPU Input Absolute Pointer of Buffer 0***/ -#define INCA_IP_MBC_MBC_IABS0 ((volatile u32*)(INCA_IP_MBC+ 0x0010)) -#define INCA_IP_MBC_MBC_IABS0_IABS - -/***Mailbox CPU Input Absolute Pointer of Buffer 1***/ -#define INCA_IP_MBC_MBC_IABS1 ((volatile u32*)(INCA_IP_MBC+ 0x0030)) -#define INCA_IP_MBC_MBC_IABS1_IABS - -/***Mailbox CPU Input Absolute Pointer of Buffer 2***/ -#define INCA_IP_MBC_MBC_IABS2 ((volatile u32*)(INCA_IP_MBC+ 0x0050)) -#define INCA_IP_MBC_MBC_IABS2_IABS - -/***Mailbox CPU Input Absolute Pointer of Buffer 3***/ -#define INCA_IP_MBC_MBC_IABS3 ((volatile u32*)(INCA_IP_MBC+ 0x0070)) -#define INCA_IP_MBC_MBC_IABS3_IABS - -/***Mailbox CPU Input Temporary Pointer of Buffer 0***/ -#define INCA_IP_MBC_MBC_ITMP0 ((volatile u32*)(INCA_IP_MBC+ 0x0014)) -#define INCA_IP_MBC_MBC_ITMP0_ITMP - -/***Mailbox CPU Input Temporary Pointer of Buffer 1***/ -#define INCA_IP_MBC_MBC_ITMP1 ((volatile u32*)(INCA_IP_MBC+ 0x0034)) -#define INCA_IP_MBC_MBC_ITMP1_ITMP - -/***Mailbox CPU Input Temporary Pointer of Buffer 2***/ -#define INCA_IP_MBC_MBC_ITMP2 ((volatile u32*)(INCA_IP_MBC+ 0x0054)) -#define INCA_IP_MBC_MBC_ITMP2_ITMP - -/***Mailbox CPU Input Temporary Pointer of Buffer 3***/ -#define INCA_IP_MBC_MBC_ITMP3 ((volatile u32*)(INCA_IP_MBC+ 0x0074)) -#define INCA_IP_MBC_MBC_ITMP3_ITMP - -/***Mailbox CPU Output Absolute Pointer of Buffer 0***/ -#define INCA_IP_MBC_MBC_OABS0 ((volatile u32*)(INCA_IP_MBC+ 0x0018)) -#define INCA_IP_MBC_MBC_OABS0_OABS - -/***Mailbox CPU Output Absolute Pointer of Buffer 1***/ -#define INCA_IP_MBC_MBC_OABS1 ((volatile u32*)(INCA_IP_MBC+ 0x0038)) -#define INCA_IP_MBC_MBC_OABS1_OABS - -/***Mailbox CPU Output Absolute Pointer of Buffer 2***/ -#define INCA_IP_MBC_MBC_OABS2 ((volatile u32*)(INCA_IP_MBC+ 0x0058)) -#define INCA_IP_MBC_MBC_OABS2_OABS - -/***Mailbox CPU Output Absolute Pointer of Buffer 3***/ -#define INCA_IP_MBC_MBC_OABS3 ((volatile u32*)(INCA_IP_MBC+ 0x0078)) -#define INCA_IP_MBC_MBC_OABS3_OABS - -/***Mailbox CPU Output Temporary Pointer of Buffer 0***/ -#define INCA_IP_MBC_MBC_OTMP0 ((volatile u32*)(INCA_IP_MBC+ 0x001C)) -#define INCA_IP_MBC_MBC_OTMP0_OTMP - -/***Mailbox CPU Output Temporary Pointer of Buffer 1***/ -#define INCA_IP_MBC_MBC_OTMP1 ((volatile u32*)(INCA_IP_MBC+ 0x003C)) -#define INCA_IP_MBC_MBC_OTMP1_OTMP - -/***Mailbox CPU Output Temporary Pointer of Buffer 2***/ -#define INCA_IP_MBC_MBC_OTMP2 ((volatile u32*)(INCA_IP_MBC+ 0x005C)) -#define INCA_IP_MBC_MBC_OTMP2_OTMP - -/***Mailbox CPU Output Temporary Pointer of Buffer 3***/ -#define INCA_IP_MBC_MBC_OTMP3 ((volatile u32*)(INCA_IP_MBC+ 0x007C)) -#define INCA_IP_MBC_MBC_OTMP3_OTMP - -/***DSP Control Register***/ -#define INCA_IP_MBC_DCTRL ((volatile u32*)(INCA_IP_MBC+ 0x00A0)) -#define INCA_IP_MBC_DCTRL_BA (1 << 0) -#define INCA_IP_MBC_DCTRL_BMOD (value) (((( 1 << 3) - 1) & (value)) << 1) -#define INCA_IP_MBC_DCTRL_IDL (1 << 4) -#define INCA_IP_MBC_DCTRL_RES (1 << 15) - -/***DSP Status Register***/ -#define INCA_IP_MBC_DSTA ((volatile u32*)(INCA_IP_MBC+ 0x00A4)) -#define INCA_IP_MBC_DSTA_IDLE (1 << 0) -#define INCA_IP_MBC_DSTA_PD (1 << 1) - -/***DSP Test 1 Register***/ -#define INCA_IP_MBC_DTST1 ((volatile u32*)(INCA_IP_MBC+ 0x00A8)) -#define INCA_IP_MBC_DTST1_ABORT (1 << 0) -#define INCA_IP_MBC_DTST1_HWF32 (1 << 1) -#define INCA_IP_MBC_DTST1_HWF4M (1 << 2) -#define INCA_IP_MBC_DTST1_HWFOP (1 << 3) - -/***********************************************************************/ -/* Module : Switch register address and bits */ -/***********************************************************************/ - -#define INCA_IP_Switch (0xBF104000) -/***********************************************************************/ - - -/***Unknown Destination Register***/ -#define INCA_IP_Switch_UN_DEST ((volatile u32*)(INCA_IP_Switch+ 0x0000)) -#define INCA_IP_Switch_UN_DEST_CB (1 << 8) -#define INCA_IP_Switch_UN_DEST_LB (1 << 7) -#define INCA_IP_Switch_UN_DEST_PB (1 << 6) -#define INCA_IP_Switch_UN_DEST_CM (1 << 5) -#define INCA_IP_Switch_UN_DEST_LM (1 << 4) -#define INCA_IP_Switch_UN_DEST_PM (1 << 3) -#define INCA_IP_Switch_UN_DEST_CU (1 << 2) -#define INCA_IP_Switch_UN_DEST_LU (1 << 1) -#define INCA_IP_Switch_UN_DEST_PU (1 << 0) - -/***VLAN Control Register***/ -#define INCA_IP_Switch_VLAN_CTRL ((volatile u32*)(INCA_IP_Switch+ 0x0004)) -#define INCA_IP_Switch_VLAN_CTRL_SC (1 << 6) -#define INCA_IP_Switch_VLAN_CTRL_SL (1 << 5) -#define INCA_IP_Switch_VLAN_CTRL_SP (1 << 4) -#define INCA_IP_Switch_VLAN_CTRL_TC (1 << 3) -#define INCA_IP_Switch_VLAN_CTRL_TL (1 << 2) -#define INCA_IP_Switch_VLAN_CTRL_TP (1 << 1) -#define INCA_IP_Switch_VLAN_CTRL_VA (1 << 0) - -/***PC VLAN Configuration Register***/ -#define INCA_IP_Switch_PC_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0008)) -#define INCA_IP_Switch_PC_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12) -#define INCA_IP_Switch_PC_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0) - -/***LAN VLAN Configuration Register***/ -#define INCA_IP_Switch_LAN_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x000C)) -#define INCA_IP_Switch_LAN_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12) -#define INCA_IP_Switch_LAN_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0) - -/***CPU VLAN Configuration Register***/ -#define INCA_IP_Switch_CPU_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0010)) -#define INCA_IP_Switch_CPU_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 12) -#define INCA_IP_Switch_CPU_VLAN_VLAN_ID (value) (((( 1 << 12) - 1) & (value)) << 0) - -/***Priority CoS Mapping Register***/ -#define INCA_IP_Switch_PRI_CoS ((volatile u32*)(INCA_IP_Switch+ 0x0014)) -#define INCA_IP_Switch_PRI_CoS_P7 (1 << 7) -#define INCA_IP_Switch_PRI_CoS_P6 (1 << 6) -#define INCA_IP_Switch_PRI_CoS_P5 (1 << 5) -#define INCA_IP_Switch_PRI_CoS_P4 (1 << 4) -#define INCA_IP_Switch_PRI_CoS_P3 (1 << 3) -#define INCA_IP_Switch_PRI_CoS_P2 (1 << 2) -#define INCA_IP_Switch_PRI_CoS_P1 (1 << 1) -#define INCA_IP_Switch_PRI_CoS_P0 (1 << 0) - -/***Spanning Tree Port Status Register***/ -#define INCA_IP_Switch_ST_PT ((volatile u32*)(INCA_IP_Switch+ 0x0018)) -#define INCA_IP_Switch_ST_PT_CPS (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_Switch_ST_PT_LPS (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_Switch_ST_PT_PPS (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***ARL Control Register***/ -#define INCA_IP_Switch_ARL_CTL ((volatile u32*)(INCA_IP_Switch+ 0x001C)) -#define INCA_IP_Switch_ARL_CTL_CHCC (1 << 15) -#define INCA_IP_Switch_ARL_CTL_CHCL (1 << 14) -#define INCA_IP_Switch_ARL_CTL_CHCP (1 << 13) -#define INCA_IP_Switch_ARL_CTL_CC (1 << 12) -#define INCA_IP_Switch_ARL_CTL_CL (1 << 11) -#define INCA_IP_Switch_ARL_CTL_CP (1 << 10) -#define INCA_IP_Switch_ARL_CTL_CG (1 << 9) -#define INCA_IP_Switch_ARL_CTL_PS (1 << 8) -#define INCA_IP_Switch_ARL_CTL_MRO (1 << 7) -#define INCA_IP_Switch_ARL_CTL_SRC (1 << 6) -#define INCA_IP_Switch_ARL_CTL_ATS (1 << 5) -#define INCA_IP_Switch_ARL_CTL_AGE_TICK_SEL (value) (((( 1 << 3) - 1) & (value)) << 2) -#define INCA_IP_Switch_ARL_CTL_MAF (1 << 1) -#define INCA_IP_Switch_ARL_CTL_ENL (1 << 0) -#define INCA_IP_Switch_ARL_CTL_Res (value) (((( 1 << 19) - 1) & (value)) << 13) - -/***CPU Access Control Register***/ -#define INCA_IP_Switch_CPU_ACTL ((volatile u32*)(INCA_IP_Switch+ 0x0020)) -#define INCA_IP_Switch_CPU_ACTL_RA (1 << 31) -#define INCA_IP_Switch_CPU_ACTL_RW (1 << 30) -#define INCA_IP_Switch_CPU_ACTL_Res (value) (((( 1 << 21) - 1) & (value)) << 9) -#define INCA_IP_Switch_CPU_ACTL_AVA (1 << 8) -#define INCA_IP_Switch_CPU_ACTL_IDX (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***CPU Access Data Register 1***/ -#define INCA_IP_Switch_DATA1 ((volatile u32*)(INCA_IP_Switch+ 0x0024)) -#define INCA_IP_Switch_DATA1_Data (value) (((( 1 << 24) - 1) & (value)) << 0) - -/***CPU Access Data Register 2***/ -#define INCA_IP_Switch_DATA2 ((volatile u32*)(INCA_IP_Switch+ 0x0028)) -#define INCA_IP_Switch_DATA2_Data - -/***CPU Port Control Register***/ -#define INCA_IP_Switch_CPU_PCTL ((volatile u32*)(INCA_IP_Switch+ 0x002C)) -#define INCA_IP_Switch_CPU_PCTL_DA_PORTS (value) (((( 1 << 3) - 1) & (value)) << 11) -#define INCA_IP_Switch_CPU_PCTL_DAC (1 << 10) -#define INCA_IP_Switch_CPU_PCTL_MA_STATE (value) (((( 1 << 3) - 1) & (value)) << 7) -#define INCA_IP_Switch_CPU_PCTL_MAM (1 << 6) -#define INCA_IP_Switch_CPU_PCTL_MA_Ports (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_Switch_CPU_PCTL_MAC (1 << 2) -#define INCA_IP_Switch_CPU_PCTL_EML (1 << 1) -#define INCA_IP_Switch_CPU_PCTL_EDL (1 << 0) -#define INCA_IP_Switch_CPU_PCTL_Res (value) (((( 1 << 18) - 1) & (value)) << 14) - -/***DSCP CoS Mapping Register 1***/ -#define INCA_IP_Switch_DSCP_COS1 ((volatile u32*)(INCA_IP_Switch+ 0x0030)) -#define INCA_IP_Switch_DSCP_COS1_DSCP - -/***DSCP CoS Mapping Register 1***/ -#define INCA_IP_Switch_DSCP_COS2 ((volatile u32*)(INCA_IP_Switch+ 0x0034)) -#define INCA_IP_Switch_DSCP_COS2_DSCP - -/***PC WFQ Control Register***/ -#define INCA_IP_Switch_PC_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0080)) -#define INCA_IP_Switch_PC_WFQ_CTL_P1 (1 << 9) -#define INCA_IP_Switch_PC_WFQ_CTL_P0 (1 << 8) -#define INCA_IP_Switch_PC_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5) -#define INCA_IP_Switch_PC_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2) -#define INCA_IP_Switch_PC_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***PC TX Control Register***/ -#define INCA_IP_Switch_PC_TX_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0084)) -#define INCA_IP_Switch_PC_TX_CTL_ELR (1 << 1) -#define INCA_IP_Switch_PC_TX_CTL_EER (1 << 0) - -/***LAN WFQ Control Register***/ -#define INCA_IP_Switch_LAN_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0100)) -#define INCA_IP_Switch_LAN_WFQ_CTL_P1 (1 << 9) -#define INCA_IP_Switch_LAN_WFQ_CTL_P0 (1 << 8) -#define INCA_IP_Switch_LAN_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5) -#define INCA_IP_Switch_LAN_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2) -#define INCA_IP_Switch_LAN_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***LAN TX Control Register***/ -#define INCA_IP_Switch_LAN_TX_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0104)) -#define INCA_IP_Switch_LAN_TX_CTL_ELR (1 << 1) -#define INCA_IP_Switch_LAN_TX_CTL_EER (1 << 0) - -/***CPU WFQ Control Register***/ -#define INCA_IP_Switch_CPU_WFQ_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0180)) -#define INCA_IP_Switch_CPU_WFQ_CTL_P1 (1 << 9) -#define INCA_IP_Switch_CPU_WFQ_CTL_P0 (1 << 8) -#define INCA_IP_Switch_CPU_WFQ_CTL_WT1 (value) (((( 1 << 3) - 1) & (value)) << 5) -#define INCA_IP_Switch_CPU_WFQ_CTL_WT0 (value) (((( 1 << 3) - 1) & (value)) << 2) -#define INCA_IP_Switch_CPU_WFQ_CTL_SCH_SEL (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***PM PC RX Watermark Register***/ -#define INCA_IP_Switch_PC_WM ((volatile u32*)(INCA_IP_Switch+ 0x0200)) -#define INCA_IP_Switch_PC_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) -#define INCA_IP_Switch_PC_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) -#define INCA_IP_Switch_PC_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_Switch_PC_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***PM LAN RX Watermark Register***/ -#define INCA_IP_Switch_LAN_WM ((volatile u32*)(INCA_IP_Switch+ 0x0204)) -#define INCA_IP_Switch_LAN_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) -#define INCA_IP_Switch_LAN_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) -#define INCA_IP_Switch_LAN_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_Switch_LAN_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***PM CPU RX Watermark Register***/ -#define INCA_IP_Switch_CPU_WM ((volatile u32*)(INCA_IP_Switch+ 0x0208)) -#define INCA_IP_Switch_CPU_WM_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) -#define INCA_IP_Switch_CPU_WM_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) -#define INCA_IP_Switch_CPU_WM_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_Switch_CPU_WM_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***PM CPU RX Watermark Register***/ -#define INCA_IP_Switch_GBL_WM ((volatile u32*)(INCA_IP_Switch+ 0x020C)) -#define INCA_IP_Switch_GBL_WM_GBL_RX_WM1 (value) (((( 1 << 8) - 1) & (value)) << 24) -#define INCA_IP_Switch_GBL_WM_GBL_RX_WM2 (value) (((( 1 << 8) - 1) & (value)) << 16) -#define INCA_IP_Switch_GBL_WM_GBL_RX_WM3 (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_Switch_GBL_WM_GBL_RX_WM4 (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***PM Control Register***/ -#define INCA_IP_Switch_PM_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0210)) -#define INCA_IP_Switch_PM_CTL_GDN (1 << 3) -#define INCA_IP_Switch_PM_CTL_CDN (1 << 2) -#define INCA_IP_Switch_PM_CTL_LDN (1 << 1) -#define INCA_IP_Switch_PM_CTL_PDN (1 << 0) - -/***PM Header Control Register***/ -#define INCA_IP_Switch_PMAC_HD_CTL ((volatile u32*)(INCA_IP_Switch+ 0x0280)) -#define INCA_IP_Switch_PMAC_HD_CTL_RL2 (1 << 21) -#define INCA_IP_Switch_PMAC_HD_CTL_RC (1 << 20) -#define INCA_IP_Switch_PMAC_HD_CTL_CM (1 << 19) -#define INCA_IP_Switch_PMAC_HD_CTL_CV (1 << 18) -#define INCA_IP_Switch_PMAC_HD_CTL_TYPE_LEN (value) (((( 1 << 16) - 1) & (value)) << 2) -#define INCA_IP_Switch_PMAC_HD_CTL_TAG (1 << 1) -#define INCA_IP_Switch_PMAC_HD_CTL_ADD (1 << 0) - -/***PM Source Address Register 1***/ -#define INCA_IP_Switch_PMAC_SA1 ((volatile u32*)(INCA_IP_Switch+ 0x0284)) -#define INCA_IP_Switch_PMAC_SA1_SA_47_32 (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***PM Source Address Register 2***/ -#define INCA_IP_Switch_PMAC_SA2 ((volatile u32*)(INCA_IP_Switch+ 0x0288)) -#define INCA_IP_Switch_PMAC_SA2_SA_31_0 - -/***PM Dest Address Register 1***/ -#define INCA_IP_Switch_PMAC_DA1 ((volatile u32*)(INCA_IP_Switch+ 0x028C)) -#define INCA_IP_Switch_PMAC_DA1_DA_47_32 (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***PM Dest Address Register 2***/ -#define INCA_IP_Switch_PMAC_DA2 ((volatile u32*)(INCA_IP_Switch+ 0x0290)) -#define INCA_IP_Switch_PMAC_DA2_DA_31_0 - -/***PM VLAN Register***/ -#define INCA_IP_Switch_PMAC_VLAN ((volatile u32*)(INCA_IP_Switch+ 0x0294)) -#define INCA_IP_Switch_PMAC_VLAN_PRI (value) (((( 1 << 3) - 1) & (value)) << 13) -#define INCA_IP_Switch_PMAC_VLAN_CFI (1 << 12) -#define INCA_IP_Switch_PMAC_VLAN_VLANID (value) (((( 1 << 12) - 1) & (value)) << 0) - -/***PM TX IPG Counter Register***/ -#define INCA_IP_Switch_PMAC_TX_IPG ((volatile u32*)(INCA_IP_Switch+ 0x0298)) -#define INCA_IP_Switch_PMAC_TX_IPG_IPGCNT (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***PM RX IPG Counter Register***/ -#define INCA_IP_Switch_PMAC_RX_IPG ((volatile u32*)(INCA_IP_Switch+ 0x029C)) -#define INCA_IP_Switch_PMAC_RX_IPG_IPGCNT (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Mirror Register***/ -#define INCA_IP_Switch_MRR ((volatile u32*)(INCA_IP_Switch+ 0x0300)) -#define INCA_IP_Switch_MRR_MRR (value) (((( 1 << 2) - 1) & (value)) << 6) -#define INCA_IP_Switch_MRR_EC (1 << 5) -#define INCA_IP_Switch_MRR_EL (1 << 4) -#define INCA_IP_Switch_MRR_EP (1 << 3) -#define INCA_IP_Switch_MRR_IC (1 << 2) -#define INCA_IP_Switch_MRR_IL (1 << 1) -#define INCA_IP_Switch_MRR_IP (1 << 0) - -/***Packet Length Register***/ -#define INCA_IP_Switch_PKT_LEN ((volatile u32*)(INCA_IP_Switch+ 0x0304)) -#define INCA_IP_Switch_PKT_LEN_ADD (1 << 11) -#define INCA_IP_Switch_PKT_LEN_MAX_PKT_LEN (value) (((( 1 << 11) - 1) & (value)) << 0) - -/***MDIO Access Register***/ -#define INCA_IP_Switch_MDIO_ACC ((volatile u32*)(INCA_IP_Switch+ 0x0480)) -#define INCA_IP_Switch_MDIO_ACC_RA (1 << 31) -#define INCA_IP_Switch_MDIO_ACC_RW (1 << 30) -#define INCA_IP_Switch_MDIO_ACC_PHY_ADDR (value) (((( 1 << 5) - 1) & (value)) << 21) -#define INCA_IP_Switch_MDIO_ACC_REG_ADDR (value) (((( 1 << 5) - 1) & (value)) << 16) -#define INCA_IP_Switch_MDIO_ACC_PHY_DATA (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***Ethernet PHY Register***/ -#define INCA_IP_Switch_EPHY ((volatile u32*)(INCA_IP_Switch+ 0x0484)) -#define INCA_IP_Switch_EPHY_SL (1 << 7) -#define INCA_IP_Switch_EPHY_SP (1 << 6) -#define INCA_IP_Switch_EPHY_LL (1 << 5) -#define INCA_IP_Switch_EPHY_LP (1 << 4) -#define INCA_IP_Switch_EPHY_DL (1 << 3) -#define INCA_IP_Switch_EPHY_DP (1 << 2) -#define INCA_IP_Switch_EPHY_PL (1 << 1) -#define INCA_IP_Switch_EPHY_PP (1 << 0) - -/***Pause Write Enable Register***/ -#define INCA_IP_Switch_PWR_EN ((volatile u32*)(INCA_IP_Switch+ 0x0488)) -#define INCA_IP_Switch_PWR_EN_PL (1 << 1) -#define INCA_IP_Switch_PWR_EN_PP (1 << 0) - -/***MDIO Configuration Register***/ -#define INCA_IP_Switch_MDIO_CFG ((volatile u32*)(INCA_IP_Switch+ 0x048C)) -#define INCA_IP_Switch_MDIO_CFG_MDS (value) (((( 1 << 2) - 1) & (value)) << 14) -#define INCA_IP_Switch_MDIO_CFG_PHY_LAN_ADDR (value) (((( 1 << 5) - 1) & (value)) << 9) -#define INCA_IP_Switch_MDIO_CFG_PHY_PC_ADDR (value) (((( 1 << 5) - 1) & (value)) << 4) -#define INCA_IP_Switch_MDIO_CFG_UEP (1 << 3) -#define INCA_IP_Switch_MDIO_CFG_PS (1 << 2) -#define INCA_IP_Switch_MDIO_CFG_PT (1 << 1) -#define INCA_IP_Switch_MDIO_CFG_UMM (1 << 0) - -/***Clock Configuration Register***/ -#define INCA_IP_Switch_CLK_CFG ((volatile u32*)(INCA_IP_Switch+ 0x0500)) -#define INCA_IP_Switch_CLK_CFG_ARL_ID (1 << 9) -#define INCA_IP_Switch_CLK_CFG_CPU_ID (1 << 8) -#define INCA_IP_Switch_CLK_CFG_LAN_ID (1 << 7) -#define INCA_IP_Switch_CLK_CFG_PC_ID (1 << 6) -#define INCA_IP_Switch_CLK_CFG_SE_ID (1 << 5) - -/***********************************************************************/ -/* Module : SSC1 register address and bits */ -/***********************************************************************/ - -#define INCA_IP_SSC1 (0xB8000500) -/***********************************************************************/ - - -/***Control Register (Programming Mode)***/ -#define INCA_IP_SSC1_SCC_CON_PRG ((volatile u32*)(INCA_IP_SSC1+ 0x0010)) -#define INCA_IP_SSC1_SCC_CON_PRG_EN (1 << 15) -#define INCA_IP_SSC1_SCC_CON_PRG_MS (1 << 14) -#define INCA_IP_SSC1_SCC_CON_PRG_AREN (1 << 12) -#define INCA_IP_SSC1_SCC_CON_PRG_BEN (1 << 11) -#define INCA_IP_SSC1_SCC_CON_PRG_PEN (1 << 10) -#define INCA_IP_SSC1_SCC_CON_PRG_REN (1 << 9) -#define INCA_IP_SSC1_SCC_CON_PRG_TEN (1 << 8) -#define INCA_IP_SSC1_SCC_CON_PRG_LB (1 << 7) -#define INCA_IP_SSC1_SCC_CON_PRG_PO (1 << 6) -#define INCA_IP_SSC1_SCC_CON_PRG_PH (1 << 5) -#define INCA_IP_SSC1_SCC_CON_PRG_HB (1 << 4) -#define INCA_IP_SSC1_SCC_CON_PRG_BM (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***SCC Control Register (Operating Mode)***/ -#define INCA_IP_SSC1_SCC_CON_OPR ((volatile u32*)(INCA_IP_SSC1+ 0x0010)) -#define INCA_IP_SSC1_SCC_CON_OPR_EN (1 << 15) -#define INCA_IP_SSC1_SCC_CON_OPR_MS (1 << 14) -#define INCA_IP_SSC1_SCC_CON_OPR_BSY (1 << 12) -#define INCA_IP_SSC1_SCC_CON_OPR_BE (1 << 11) -#define INCA_IP_SSC1_SCC_CON_OPR_PE (1 << 10) -#define INCA_IP_SSC1_SCC_CON_OPR_RE (1 << 9) -#define INCA_IP_SSC1_SCC_CON_OPR_TE (1 << 8) -#define INCA_IP_SSC1_SCC_CON_OPR_BC (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***SSC Write Hardware Modified Control Register***/ -#define INCA_IP_SSC1_SSC_WHBCON ((volatile u32*)(INCA_IP_SSC1+ 0x0040)) -#define INCA_IP_SSC1_SSC_WHBCON_SETBE (1 << 15) -#define INCA_IP_SSC1_SSC_WHBCON_SETPE (1 << 14) -#define INCA_IP_SSC1_SSC_WHBCON_SETRE (1 << 13) -#define INCA_IP_SSC1_SSC_WHBCON_SETTE (1 << 12) -#define INCA_IP_SSC1_SSC_WHBCON_CLRBE (1 << 11) -#define INCA_IP_SSC1_SSC_WHBCON_CLRPE (1 << 10) -#define INCA_IP_SSC1_SSC_WHBCON_CLRRE (1 << 9) -#define INCA_IP_SSC1_SSC_WHBCON_CLRTE (1 << 8) - -/***SSC Baudrate Timer Reload Register***/ -#define INCA_IP_SSC1_SSC_BR ((volatile u32*)(INCA_IP_SSC1+ 0x0014)) -#define INCA_IP_SSC1_SSC_BR_BR_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Transmitter Buffer Register***/ -#define INCA_IP_SSC1_SSC_TB ((volatile u32*)(INCA_IP_SSC1+ 0x0020)) -#define INCA_IP_SSC1_SSC_TB_TB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Receiver Buffer Register***/ -#define INCA_IP_SSC1_SSC_RB ((volatile u32*)(INCA_IP_SSC1+ 0x0024)) -#define INCA_IP_SSC1_SSC_RB_RB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Receive FIFO Control Register***/ -#define INCA_IP_SSC1_SSC_RXFCON ((volatile u32*)(INCA_IP_SSC1+ 0x0030)) -#define INCA_IP_SSC1_SSC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_SSC1_SSC_RXFCON_RXTMEN (1 << 2) -#define INCA_IP_SSC1_SSC_RXFCON_RXFLU (1 << 1) -#define INCA_IP_SSC1_SSC_RXFCON_RXFEN (1 << 0) - -/***SSC Transmit FIFO Control Register***/ -#define INCA_IP_SSC1_SSC_TXFCON ((volatile u32*)(INCA_IP_SSC1+ 0x0034)) -#define INCA_IP_SSC1_SSC_TXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_SSC1_SSC_TXFCON_TXTMEN (1 << 2) -#define INCA_IP_SSC1_SSC_TXFCON_TXFLU (1 << 1) -#define INCA_IP_SSC1_SSC_TXFCON_TXFEN (1 << 0) - -/***SSC FIFO Status Register***/ -#define INCA_IP_SSC1_SSC_FSTAT ((volatile u32*)(INCA_IP_SSC1+ 0x0038)) -#define INCA_IP_SSC1_SSC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_SSC1_SSC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0) - -/***SSC Clock Control Register***/ -#define INCA_IP_SSC1_SSC_CLC ((volatile u32*)(INCA_IP_SSC1+ 0x0000)) -#define INCA_IP_SSC1_SSC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_SSC1_SSC_CLC_DISS (1 << 1) -#define INCA_IP_SSC1_SSC_CLC_DISR (1 << 0) - -/***********************************************************************/ -/* Module : SSC2 register address and bits */ -/***********************************************************************/ - -#define INCA_IP_SSC2 (0xB8000600) -/***********************************************************************/ - - -/***Control Register (Programming Mode)***/ -#define INCA_IP_SSC2_SCC_CON_PRG ((volatile u32*)(INCA_IP_SSC2+ 0x0010)) -#define INCA_IP_SSC2_SCC_CON_PRG_EN (1 << 15) -#define INCA_IP_SSC2_SCC_CON_PRG_MS (1 << 14) -#define INCA_IP_SSC2_SCC_CON_PRG_AREN (1 << 12) -#define INCA_IP_SSC2_SCC_CON_PRG_BEN (1 << 11) -#define INCA_IP_SSC2_SCC_CON_PRG_PEN (1 << 10) -#define INCA_IP_SSC2_SCC_CON_PRG_REN (1 << 9) -#define INCA_IP_SSC2_SCC_CON_PRG_TEN (1 << 8) -#define INCA_IP_SSC2_SCC_CON_PRG_LB (1 << 7) -#define INCA_IP_SSC2_SCC_CON_PRG_PO (1 << 6) -#define INCA_IP_SSC2_SCC_CON_PRG_PH (1 << 5) -#define INCA_IP_SSC2_SCC_CON_PRG_HB (1 << 4) -#define INCA_IP_SSC2_SCC_CON_PRG_BM (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***SCC Control Register (Operating Mode)***/ -#define INCA_IP_SSC2_SCC_CON_OPR ((volatile u32*)(INCA_IP_SSC2+ 0x0010)) -#define INCA_IP_SSC2_SCC_CON_OPR_EN (1 << 15) -#define INCA_IP_SSC2_SCC_CON_OPR_MS (1 << 14) -#define INCA_IP_SSC2_SCC_CON_OPR_BSY (1 << 12) -#define INCA_IP_SSC2_SCC_CON_OPR_BE (1 << 11) -#define INCA_IP_SSC2_SCC_CON_OPR_PE (1 << 10) -#define INCA_IP_SSC2_SCC_CON_OPR_RE (1 << 9) -#define INCA_IP_SSC2_SCC_CON_OPR_TE (1 << 8) -#define INCA_IP_SSC2_SCC_CON_OPR_BC (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***SSC Write Hardware Modified Control Register***/ -#define INCA_IP_SSC2_SSC_WHBCON ((volatile u32*)(INCA_IP_SSC2+ 0x0040)) -#define INCA_IP_SSC2_SSC_WHBCON_SETBE (1 << 15) -#define INCA_IP_SSC2_SSC_WHBCON_SETPE (1 << 14) -#define INCA_IP_SSC2_SSC_WHBCON_SETRE (1 << 13) -#define INCA_IP_SSC2_SSC_WHBCON_SETTE (1 << 12) -#define INCA_IP_SSC2_SSC_WHBCON_CLRBE (1 << 11) -#define INCA_IP_SSC2_SSC_WHBCON_CLRPE (1 << 10) -#define INCA_IP_SSC2_SSC_WHBCON_CLRRE (1 << 9) -#define INCA_IP_SSC2_SSC_WHBCON_CLRTE (1 << 8) - -/***SSC Baudrate Timer Reload Register***/ -#define INCA_IP_SSC2_SSC_BR ((volatile u32*)(INCA_IP_SSC2+ 0x0014)) -#define INCA_IP_SSC2_SSC_BR_BR_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Transmitter Buffer Register***/ -#define INCA_IP_SSC2_SSC_TB ((volatile u32*)(INCA_IP_SSC2+ 0x0020)) -#define INCA_IP_SSC2_SSC_TB_TB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Receiver Buffer Register***/ -#define INCA_IP_SSC2_SSC_RB ((volatile u32*)(INCA_IP_SSC2+ 0x0024)) -#define INCA_IP_SSC2_SSC_RB_RB_VALUE (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***SSC Receive FIFO Control Register***/ -#define INCA_IP_SSC2_SSC_RXFCON ((volatile u32*)(INCA_IP_SSC2+ 0x0030)) -#define INCA_IP_SSC2_SSC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_SSC2_SSC_RXFCON_RXTMEN (1 << 2) -#define INCA_IP_SSC2_SSC_RXFCON_RXFLU (1 << 1) -#define INCA_IP_SSC2_SSC_RXFCON_RXFEN (1 << 0) - -/***SSC Transmit FIFO Control Register***/ -#define INCA_IP_SSC2_SSC_TXFCON ((volatile u32*)(INCA_IP_SSC2+ 0x0034)) -#define INCA_IP_SSC2_SSC_TXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_SSC2_SSC_TXFCON_TXTMEN (1 << 2) -#define INCA_IP_SSC2_SSC_TXFCON_TXFLU (1 << 1) -#define INCA_IP_SSC2_SSC_TXFCON_TXFEN (1 << 0) - -/***SSC FIFO Status Register***/ -#define INCA_IP_SSC2_SSC_FSTAT ((volatile u32*)(INCA_IP_SSC2+ 0x0038)) -#define INCA_IP_SSC2_SSC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_SSC2_SSC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0) - -/***SSC Clock Control Register***/ -#define INCA_IP_SSC2_SSC_CLC ((volatile u32*)(INCA_IP_SSC2+ 0x0000)) -#define INCA_IP_SSC2_SSC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_SSC2_SSC_CLC_DISS (1 << 1) -#define INCA_IP_SSC2_SSC_CLC_DISR (1 << 0) - -/***********************************************************************/ -/* Module : EBU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_EBU (0xB8000200) -/***********************************************************************/ - - -/***EBU Clock Control Register***/ -#define INCA_IP_EBU_EBU_CLC ((volatile u32*)(INCA_IP_EBU+ 0x0000)) -#define INCA_IP_EBU_EBU_CLC_DISS (1 << 1) -#define INCA_IP_EBU_EBU_CLC_DISR (1 << 0) - -/***EBU Global Control Register***/ -#define INCA_IP_EBU_EBU_CON ((volatile u32*)(INCA_IP_EBU+ 0x0010)) -#define INCA_IP_EBU_EBU_CON_DTACS (value) (((( 1 << 3) - 1) & (value)) << 20) -#define INCA_IP_EBU_EBU_CON_DTARW (value) (((( 1 << 3) - 1) & (value)) << 16) -#define INCA_IP_EBU_EBU_CON_TOUTC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_EBU_EBU_CON_ARBMODE (value) (((( 1 << 2) - 1) & (value)) << 6) -#define INCA_IP_EBU_EBU_CON_ARBSYNC (1 << 5) -#define INCA_IP_EBU_EBU_CON_1 (1 << 3) - -/***EBU Address Select Register 0***/ -#define INCA_IP_EBU_EBU_ADDSEL0 ((volatile u32*)(INCA_IP_EBU+ 0x0020)) -#define INCA_IP_EBU_EBU_ADDSEL0_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) -#define INCA_IP_EBU_EBU_ADDSEL0_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_EBU_EBU_ADDSEL0_MIRRORE (1 << 1) -#define INCA_IP_EBU_EBU_ADDSEL0_REGEN (1 << 0) - -/***EBU Address Select Register 1***/ -#define INCA_IP_EBU_EBU_ADDSEL1 ((volatile u32*)(INCA_IP_EBU+ 0x0024)) -#define INCA_IP_EBU_EBU_ADDSEL1_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) -#define INCA_IP_EBU_EBU_ADDSEL1_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_EBU_EBU_ADDSEL1_MIRRORE (1 << 1) -#define INCA_IP_EBU_EBU_ADDSEL1_REGEN (1 << 0) - -/***EBU Address Select Register 2***/ -#define INCA_IP_EBU_EBU_ADDSEL2 ((volatile u32*)(INCA_IP_EBU+ 0x0028)) -#define INCA_IP_EBU_EBU_ADDSEL2_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) -#define INCA_IP_EBU_EBU_ADDSEL2_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_EBU_EBU_ADDSEL2_MIRRORE (1 << 1) -#define INCA_IP_EBU_EBU_ADDSEL2_REGEN (1 << 0) - -/***EBU Bus Configuration Register 0***/ -#define INCA_IP_EBU_EBU_BUSCON0 ((volatile u32*)(INCA_IP_EBU+ 0x0060)) -#define INCA_IP_EBU_EBU_BUSCON0_WRDIS (1 << 31) -#define INCA_IP_EBU_EBU_BUSCON0_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) -#define INCA_IP_EBU_EBU_BUSCON0_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) -#define INCA_IP_EBU_EBU_BUSCON0_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) -#define INCA_IP_EBU_EBU_BUSCON0_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) -#define INCA_IP_EBU_EBU_BUSCON0_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) -#define INCA_IP_EBU_EBU_BUSCON0_WAITINV (1 << 19) -#define INCA_IP_EBU_EBU_BUSCON0_SETUP (1 << 18) -#define INCA_IP_EBU_EBU_BUSCON0_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) -#define INCA_IP_EBU_EBU_BUSCON0_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) -#define INCA_IP_EBU_EBU_BUSCON0_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) -#define INCA_IP_EBU_EBU_BUSCON0_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_EBU_EBU_BUSCON0_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_EBU_EBU_BUSCON0_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***EBU Bus Configuration Register 1***/ -#define INCA_IP_EBU_EBU_BUSCON1 ((volatile u32*)(INCA_IP_EBU+ 0x0064)) -#define INCA_IP_EBU_EBU_BUSCON1_WRDIS (1 << 31) -#define INCA_IP_EBU_EBU_BUSCON1_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) -#define INCA_IP_EBU_EBU_BUSCON1_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) -#define INCA_IP_EBU_EBU_BUSCON1_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) -#define INCA_IP_EBU_EBU_BUSCON1_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) -#define INCA_IP_EBU_EBU_BUSCON1_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) -#define INCA_IP_EBU_EBU_BUSCON1_WAITINV (1 << 19) -#define INCA_IP_EBU_EBU_BUSCON1_SETUP (1 << 18) -#define INCA_IP_EBU_EBU_BUSCON1_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) -#define INCA_IP_EBU_EBU_BUSCON1_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) -#define INCA_IP_EBU_EBU_BUSCON1_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) -#define INCA_IP_EBU_EBU_BUSCON1_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_EBU_EBU_BUSCON1_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_EBU_EBU_BUSCON1_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***EBU Bus Configuration Register 2***/ -#define INCA_IP_EBU_EBU_BUSCON2 ((volatile u32*)(INCA_IP_EBU+ 0x0068)) -#define INCA_IP_EBU_EBU_BUSCON2_WRDIS (1 << 31) -#define INCA_IP_EBU_EBU_BUSCON2_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) -#define INCA_IP_EBU_EBU_BUSCON2_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) -#define INCA_IP_EBU_EBU_BUSCON2_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) -#define INCA_IP_EBU_EBU_BUSCON2_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) -#define INCA_IP_EBU_EBU_BUSCON2_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) -#define INCA_IP_EBU_EBU_BUSCON2_WAITINV (1 << 19) -#define INCA_IP_EBU_EBU_BUSCON2_SETUP (1 << 18) -#define INCA_IP_EBU_EBU_BUSCON2_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) -#define INCA_IP_EBU_EBU_BUSCON2_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) -#define INCA_IP_EBU_EBU_BUSCON2_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) -#define INCA_IP_EBU_EBU_BUSCON2_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_EBU_EBU_BUSCON2_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_EBU_EBU_BUSCON2_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : SDRAM register address and bits */ -/***********************************************************************/ - -#define INCA_IP_SDRAM (0xBF800000) -/***********************************************************************/ - - -/***MC Access Error Cause Register***/ -#define INCA_IP_SDRAM_MC_ERRCAUSE ((volatile u32*)(INCA_IP_SDRAM+ 0x0100)) -#define INCA_IP_SDRAM_MC_ERRCAUSE_ERR (1 << 31) -#define INCA_IP_SDRAM_MC_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) -#define INCA_IP_SDRAM_MC_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) -#define INCA_IP_SDRAM_MC_ERRCAUSE_Res (value) (((( 1 << NaN) - 1) & (value)) << NaN) - -/***MC Access Error Address Register***/ -#define INCA_IP_SDRAM_MC_ERRADDR ((volatile u32*)(INCA_IP_SDRAM+ 0x0108)) -#define INCA_IP_SDRAM_MC_ERRADDR_ADDR - -/***MC I/O General Purpose Register***/ -#define INCA_IP_SDRAM_MC_IOGP ((volatile u32*)(INCA_IP_SDRAM+ 0x0800)) -#define INCA_IP_SDRAM_MC_IOGP_GPR6 (value) (((( 1 << 4) - 1) & (value)) << 28) -#define INCA_IP_SDRAM_MC_IOGP_GPR5 (value) (((( 1 << 4) - 1) & (value)) << 24) -#define INCA_IP_SDRAM_MC_IOGP_GPR4 (value) (((( 1 << 4) - 1) & (value)) << 20) -#define INCA_IP_SDRAM_MC_IOGP_GPR3 (value) (((( 1 << 4) - 1) & (value)) << 16) -#define INCA_IP_SDRAM_MC_IOGP_GPR2 (value) (((( 1 << 4) - 1) & (value)) << 12) -#define INCA_IP_SDRAM_MC_IOGP_CPS (1 << 11) -#define INCA_IP_SDRAM_MC_IOGP_CLKDELAY (value) (((( 1 << 3) - 1) & (value)) << 8) -#define INCA_IP_SDRAM_MC_IOGP_CLKRAT (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_SDRAM_MC_IOGP_RDDEL (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***MC Self Refresh Register***/ -#define INCA_IP_SDRAM_MC_SELFRFSH ((volatile u32*)(INCA_IP_SDRAM+ 0x0A00)) -#define INCA_IP_SDRAM_MC_SELFRFSH_PWDS (1 << 1) -#define INCA_IP_SDRAM_MC_SELFRFSH_PWD (1 << 0) -#define INCA_IP_SDRAM_MC_SELFRFSH_Res (value) (((( 1 << 30) - 1) & (value)) << 2) - -/***MC Enable Register***/ -#define INCA_IP_SDRAM_MC_CTRLENA ((volatile u32*)(INCA_IP_SDRAM+ 0x1000)) -#define INCA_IP_SDRAM_MC_CTRLENA_ENA (1 << 0) -#define INCA_IP_SDRAM_MC_CTRLENA_Res (value) (((( 1 << 31) - 1) & (value)) << 1) - -/***MC Mode Register Setup Code***/ -#define INCA_IP_SDRAM_MC_MRSCODE ((volatile u32*)(INCA_IP_SDRAM+ 0x1008)) -#define INCA_IP_SDRAM_MC_MRSCODE_UMC (value) (((( 1 << 5) - 1) & (value)) << 7) -#define INCA_IP_SDRAM_MC_MRSCODE_CL (value) (((( 1 << 3) - 1) & (value)) << 4) -#define INCA_IP_SDRAM_MC_MRSCODE_WT (1 << 3) -#define INCA_IP_SDRAM_MC_MRSCODE_BL (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***MC Configuration Data-word Width Register***/ -#define INCA_IP_SDRAM_MC_CFGDW ((volatile u32*)(INCA_IP_SDRAM+ 0x1010)) -#define INCA_IP_SDRAM_MC_CFGDW_DW (value) (((( 1 << 4) - 1) & (value)) << 0) -#define INCA_IP_SDRAM_MC_CFGDW_Res (value) (((( 1 << 28) - 1) & (value)) << 4) - -/***MC Configuration Physical Bank 0 Register***/ -#define INCA_IP_SDRAM_MC_CFGPB0 ((volatile u32*)(INCA_IP_SDRAM+ 0x1018)) -#define INCA_IP_SDRAM_MC_CFGPB0_MCSEN0 (value) (((( 1 << 4) - 1) & (value)) << 12) -#define INCA_IP_SDRAM_MC_CFGPB0_BANKN0 (value) (((( 1 << 4) - 1) & (value)) << 8) -#define INCA_IP_SDRAM_MC_CFGPB0_ROWW0 (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_SDRAM_MC_CFGPB0_COLW0 (value) (((( 1 << 4) - 1) & (value)) << 0) -#define INCA_IP_SDRAM_MC_CFGPB0_Res (value) (((( 1 << 16) - 1) & (value)) << 16) - -/***MC Latency Register***/ -#define INCA_IP_SDRAM_MC_LATENCY ((volatile u32*)(INCA_IP_SDRAM+ 0x1038)) -#define INCA_IP_SDRAM_MC_LATENCY_TRP (value) (((( 1 << 4) - 1) & (value)) << 16) -#define INCA_IP_SDRAM_MC_LATENCY_TRAS (value) (((( 1 << 4) - 1) & (value)) << 12) -#define INCA_IP_SDRAM_MC_LATENCY_TRCD (value) (((( 1 << 4) - 1) & (value)) << 8) -#define INCA_IP_SDRAM_MC_LATENCY_TDPL (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_SDRAM_MC_LATENCY_TDAL (value) (((( 1 << 4) - 1) & (value)) << 0) -#define INCA_IP_SDRAM_MC_LATENCY_Res (value) (((( 1 << 12) - 1) & (value)) << 20) - -/***MC Refresh Cycle Time Register***/ -#define INCA_IP_SDRAM_MC_TREFRESH ((volatile u32*)(INCA_IP_SDRAM+ 0x1040)) -#define INCA_IP_SDRAM_MC_TREFRESH_TREF (value) (((( 1 << 13) - 1) & (value)) << 0) -#define INCA_IP_SDRAM_MC_TREFRESH_Res (value) (((( 1 << 19) - 1) & (value)) << 13) - -/***********************************************************************/ -/* Module : GPTU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_GPTU (0xB8000300) -/***********************************************************************/ - - -/***GPT Clock Control Register***/ -#define INCA_IP_GPTU_GPT_CLC ((volatile u32*)(INCA_IP_GPTU+ 0x0000)) -#define INCA_IP_GPTU_GPT_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_GPTU_GPT_CLC_DISS (1 << 1) -#define INCA_IP_GPTU_GPT_CLC_DISR (1 << 0) - -/***GPT Timer 3 Control Register***/ -#define INCA_IP_GPTU_GPT_T3CON ((volatile u32*)(INCA_IP_GPTU+ 0x0014)) -#define INCA_IP_GPTU_GPT_T3CON_T3RDIR (1 << 15) -#define INCA_IP_GPTU_GPT_T3CON_T3CHDIR (1 << 14) -#define INCA_IP_GPTU_GPT_T3CON_T3EDGE (1 << 13) -#define INCA_IP_GPTU_GPT_T3CON_BPS1 (value) (((( 1 << 2) - 1) & (value)) << 11) -#define INCA_IP_GPTU_GPT_T3CON_T3OTL (1 << 10) -#define INCA_IP_GPTU_GPT_T3CON_T3UD (1 << 7) -#define INCA_IP_GPTU_GPT_T3CON_T3R (1 << 6) -#define INCA_IP_GPTU_GPT_T3CON_T3M (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_GPTU_GPT_T3CON_T3I (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write Hardware Modified Timer 3 Control Register -If set and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define INCA_IP_GPTU_GPT_WHBT3CON ((volatile u32*)(INCA_IP_GPTU+ 0x004C)) -#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3CHDIR (1 << 15) -#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3CHDIR (1 << 14) -#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3EDGE (1 << 13) -#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3EDGE (1 << 12) -#define INCA_IP_GPTU_GPT_WHBT3CON_SETT3OTL (1 << 11) -#define INCA_IP_GPTU_GPT_WHBT3CON_CLRT3OTL (1 << 10) - -/***GPT Timer 2 Control Register***/ -#define INCA_IP_GPTU_GPT_T2CON ((volatile u32*)(INCA_IP_GPTU+ 0x0010)) -#define INCA_IP_GPTU_GPT_T2CON_TxRDIR (1 << 15) -#define INCA_IP_GPTU_GPT_T2CON_TxCHDIR (1 << 14) -#define INCA_IP_GPTU_GPT_T2CON_TxEDGE (1 << 13) -#define INCA_IP_GPTU_GPT_T2CON_TxIRDIS (1 << 12) -#define INCA_IP_GPTU_GPT_T2CON_TxRC (1 << 9) -#define INCA_IP_GPTU_GPT_T2CON_TxUD (1 << 7) -#define INCA_IP_GPTU_GPT_T2CON_TxR (1 << 6) -#define INCA_IP_GPTU_GPT_T2CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_GPTU_GPT_T2CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Timer 4 Control Register***/ -#define INCA_IP_GPTU_GPT_T4CON ((volatile u32*)(INCA_IP_GPTU+ 0x0018)) -#define INCA_IP_GPTU_GPT_T4CON_TxRDIR (1 << 15) -#define INCA_IP_GPTU_GPT_T4CON_TxCHDIR (1 << 14) -#define INCA_IP_GPTU_GPT_T4CON_TxEDGE (1 << 13) -#define INCA_IP_GPTU_GPT_T4CON_TxIRDIS (1 << 12) -#define INCA_IP_GPTU_GPT_T4CON_TxRC (1 << 9) -#define INCA_IP_GPTU_GPT_T4CON_TxUD (1 << 7) -#define INCA_IP_GPTU_GPT_T4CON_TxR (1 << 6) -#define INCA_IP_GPTU_GPT_T4CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_GPTU_GPT_T4CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write HW Modified Timer 2 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define INCA_IP_GPTU_GPT_WHBT2CON ((volatile u32*)(INCA_IP_GPTU+ 0x0048)) -#define INCA_IP_GPTU_GPT_WHBT2CON_SETTxCHDIR (1 << 15) -#define INCA_IP_GPTU_GPT_WHBT2CON_CLRTxCHDIR (1 << 14) -#define INCA_IP_GPTU_GPT_WHBT2CON_SETTxEDGE (1 << 13) -#define INCA_IP_GPTU_GPT_WHBT2CON_CLRTxEDGE (1 << 12) - -/***GPT Write HW Modified Timer 4 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define INCA_IP_GPTU_GPT_WHBT4CON ((volatile u32*)(INCA_IP_GPTU+ 0x0050)) -#define INCA_IP_GPTU_GPT_WHBT4CON_SETTxCHDIR (1 << 15) -#define INCA_IP_GPTU_GPT_WHBT4CON_CLRTxCHDIR (1 << 14) -#define INCA_IP_GPTU_GPT_WHBT4CON_SETTxEDGE (1 << 13) -#define INCA_IP_GPTU_GPT_WHBT4CON_CLRTxEDGE (1 << 12) - -/***GPT Capture Reload Register***/ -#define INCA_IP_GPTU_GPT_CAPREL ((volatile u32*)(INCA_IP_GPTU+ 0x0030)) -#define INCA_IP_GPTU_GPT_CAPREL_CAPREL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 2 Register***/ -#define INCA_IP_GPTU_GPT_T2 ((volatile u32*)(INCA_IP_GPTU+ 0x0034)) -#define INCA_IP_GPTU_GPT_T2_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 3 Register***/ -#define INCA_IP_GPTU_GPT_T3 ((volatile u32*)(INCA_IP_GPTU+ 0x0038)) -#define INCA_IP_GPTU_GPT_T3_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 4 Register***/ -#define INCA_IP_GPTU_GPT_T4 ((volatile u32*)(INCA_IP_GPTU+ 0x003C)) -#define INCA_IP_GPTU_GPT_T4_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 5 Register***/ -#define INCA_IP_GPTU_GPT_T5 ((volatile u32*)(INCA_IP_GPTU+ 0x0040)) -#define INCA_IP_GPTU_GPT_T5_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 6 Register***/ -#define INCA_IP_GPTU_GPT_T6 ((volatile u32*)(INCA_IP_GPTU+ 0x0044)) -#define INCA_IP_GPTU_GPT_T6_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 6 Control Register***/ -#define INCA_IP_GPTU_GPT_T6CON ((volatile u32*)(INCA_IP_GPTU+ 0x0020)) -#define INCA_IP_GPTU_GPT_T6CON_T6SR (1 << 15) -#define INCA_IP_GPTU_GPT_T6CON_T6CLR (1 << 14) -#define INCA_IP_GPTU_GPT_T6CON_BPS2 (value) (((( 1 << 2) - 1) & (value)) << 11) -#define INCA_IP_GPTU_GPT_T6CON_T6OTL (1 << 10) -#define INCA_IP_GPTU_GPT_T6CON_T6UD (1 << 7) -#define INCA_IP_GPTU_GPT_T6CON_T6R (1 << 6) -#define INCA_IP_GPTU_GPT_T6CON_T6M (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_GPTU_GPT_T6CON_T6I (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write HW Modified Timer 6 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define INCA_IP_GPTU_GPT_WHBT6CON ((volatile u32*)(INCA_IP_GPTU+ 0x0054)) -#define INCA_IP_GPTU_GPT_WHBT6CON_SETT6OTL (1 << 11) -#define INCA_IP_GPTU_GPT_WHBT6CON_CLRT6OTL (1 << 10) - -/***GPT Timer 5 Control Register***/ -#define INCA_IP_GPTU_GPT_T5CON ((volatile u32*)(INCA_IP_GPTU+ 0x001C)) -#define INCA_IP_GPTU_GPT_T5CON_T5SC (1 << 15) -#define INCA_IP_GPTU_GPT_T5CON_T5CLR (1 << 14) -#define INCA_IP_GPTU_GPT_T5CON_CI (value) (((( 1 << 2) - 1) & (value)) << 12) -#define INCA_IP_GPTU_GPT_T5CON_T5CC (1 << 11) -#define INCA_IP_GPTU_GPT_T5CON_CT3 (1 << 10) -#define INCA_IP_GPTU_GPT_T5CON_T5RC (1 << 9) -#define INCA_IP_GPTU_GPT_T5CON_T5UDE (1 << 8) -#define INCA_IP_GPTU_GPT_T5CON_T5UD (1 << 7) -#define INCA_IP_GPTU_GPT_T5CON_T5R (1 << 6) -#define INCA_IP_GPTU_GPT_T5CON_T5M (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_GPTU_GPT_T5CON_T5I (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : IOM register address and bits */ -/***********************************************************************/ - -#define INCA_IP_IOM (0xBF105000) -/***********************************************************************/ - - -/***Receive FIFO***/ -#define INCA_IP_IOM_RFIFO ((volatile u32*)(INCA_IP_IOM+ 0x0000)) -#define INCA_IP_IOM_RFIFO_RXD (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Transmit FIFO***/ -#define INCA_IP_IOM_XFIFO ((volatile u32*)(INCA_IP_IOM+ 0x0000)) -#define INCA_IP_IOM_XFIFO_TXD (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Interrupt Status Register HDLC***/ -#define INCA_IP_IOM_ISTAH ((volatile u32*)(INCA_IP_IOM+ 0x0080)) -#define INCA_IP_IOM_ISTAH_RME (1 << 7) -#define INCA_IP_IOM_ISTAH_RPF (1 << 6) -#define INCA_IP_IOM_ISTAH_RFO (1 << 5) -#define INCA_IP_IOM_ISTAH_XPR (1 << 4) -#define INCA_IP_IOM_ISTAH_XMR (1 << 3) -#define INCA_IP_IOM_ISTAH_XDU (1 << 2) - -/***Interrupt Mask Register HDLC***/ -#define INCA_IP_IOM_MASKH ((volatile u32*)(INCA_IP_IOM+ 0x0080)) -#define INCA_IP_IOM_MASKH_RME (1 << 7) -#define INCA_IP_IOM_MASKH_RPF (1 << 6) -#define INCA_IP_IOM_MASKH_RFO (1 << 5) -#define INCA_IP_IOM_MASKH_XPR (1 << 4) -#define INCA_IP_IOM_MASKH_XMR (1 << 3) -#define INCA_IP_IOM_MASKH_XDU (1 << 2) - -/***Status Register***/ -#define INCA_IP_IOM_STAR ((volatile u32*)(INCA_IP_IOM+ 0x0084)) -#define INCA_IP_IOM_STAR_XDOV (1 << 7) -#define INCA_IP_IOM_STAR_XFW (1 << 6) -#define INCA_IP_IOM_STAR_RACI (1 << 3) -#define INCA_IP_IOM_STAR_XACI (1 << 1) - -/***Command Register***/ -#define INCA_IP_IOM_CMDR ((volatile u32*)(INCA_IP_IOM+ 0x0084)) -#define INCA_IP_IOM_CMDR_RMC (1 << 7) -#define INCA_IP_IOM_CMDR_RRES (1 << 6) -#define INCA_IP_IOM_CMDR_XTF (1 << 3) -#define INCA_IP_IOM_CMDR_XME (1 << 1) -#define INCA_IP_IOM_CMDR_XRES (1 << 0) - -/***Mode Register***/ -#define INCA_IP_IOM_MODEH ((volatile u32*)(INCA_IP_IOM+ 0x0088)) -#define INCA_IP_IOM_MODEH_MDS2 (1 << 7) -#define INCA_IP_IOM_MODEH_MDS1 (1 << 6) -#define INCA_IP_IOM_MODEH_MDS0 (1 << 5) -#define INCA_IP_IOM_MODEH_RAC (1 << 3) -#define INCA_IP_IOM_MODEH_DIM2 (1 << 2) -#define INCA_IP_IOM_MODEH_DIM1 (1 << 1) -#define INCA_IP_IOM_MODEH_DIM0 (1 << 0) - -/***Extended Mode Register***/ -#define INCA_IP_IOM_EXMR ((volatile u32*)(INCA_IP_IOM+ 0x008C)) -#define INCA_IP_IOM_EXMR_XFBS (1 << 7) -#define INCA_IP_IOM_EXMR_RFBS (value) (((( 1 << 2) - 1) & (value)) << 5) -#define INCA_IP_IOM_EXMR_SRA (1 << 4) -#define INCA_IP_IOM_EXMR_XCRC (1 << 3) -#define INCA_IP_IOM_EXMR_RCRC (1 << 2) -#define INCA_IP_IOM_EXMR_ITF (1 << 0) - -/***SAPI1 Register***/ -#define INCA_IP_IOM_SAP1 ((volatile u32*)(INCA_IP_IOM+ 0x0094)) -#define INCA_IP_IOM_SAP1_SAPI1 (value) (((( 1 << 6) - 1) & (value)) << 2) -#define INCA_IP_IOM_SAP1_MHA (1 << 0) - -/***Receive Frame Byte Count Low***/ -#define INCA_IP_IOM_RBCL ((volatile u32*)(INCA_IP_IOM+ 0x0098)) -#define INCA_IP_IOM_RBCL_RBC(value) (1 << value) - - -/***SAPI2 Register***/ -#define INCA_IP_IOM_SAP2 ((volatile u32*)(INCA_IP_IOM+ 0x0098)) -#define INCA_IP_IOM_SAP2_SAPI2 (value) (((( 1 << 6) - 1) & (value)) << 2) -#define INCA_IP_IOM_SAP2_MLA (1 << 0) - -/***Receive Frame Byte Count High***/ -#define INCA_IP_IOM_RBCH ((volatile u32*)(INCA_IP_IOM+ 0x009C)) -#define INCA_IP_IOM_RBCH_OV (1 << 4) -#define INCA_IP_IOM_RBCH_RBC11 (1 << 3) -#define INCA_IP_IOM_RBCH_RBC10 (1 << 2) -#define INCA_IP_IOM_RBCH_RBC9 (1 << 1) -#define INCA_IP_IOM_RBCH_RBC8 (1 << 0) - -/***TEI1 Register 1***/ -#define INCA_IP_IOM_TEI1 ((volatile u32*)(INCA_IP_IOM+ 0x009C)) -#define INCA_IP_IOM_TEI1_TEI1 (value) (((( 1 << 7) - 1) & (value)) << 1) -#define INCA_IP_IOM_TEI1_EA (1 << 0) - -/***Receive Status Register***/ -#define INCA_IP_IOM_RSTA ((volatile u32*)(INCA_IP_IOM+ 0x00A0)) -#define INCA_IP_IOM_RSTA_VFR (1 << 7) -#define INCA_IP_IOM_RSTA_RDO (1 << 6) -#define INCA_IP_IOM_RSTA_CRC (1 << 5) -#define INCA_IP_IOM_RSTA_RAB (1 << 4) -#define INCA_IP_IOM_RSTA_SA1 (1 << 3) -#define INCA_IP_IOM_RSTA_SA0 (1 << 2) -#define INCA_IP_IOM_RSTA_TA (1 << 0) -#define INCA_IP_IOM_RSTA_CR (1 << 1) - -/***TEI2 Register***/ -#define INCA_IP_IOM_TEI2 ((volatile u32*)(INCA_IP_IOM+ 0x00A0)) -#define INCA_IP_IOM_TEI2_TEI2 (value) (((( 1 << 7) - 1) & (value)) << 1) -#define INCA_IP_IOM_TEI2_EA (1 << 0) - -/***Test Mode Register HDLC***/ -#define INCA_IP_IOM_TMH ((volatile u32*)(INCA_IP_IOM+ 0x00A4)) -#define INCA_IP_IOM_TMH_TLP (1 << 0) - -/***Command/Indication Receive 0***/ -#define INCA_IP_IOM_CIR0 ((volatile u32*)(INCA_IP_IOM+ 0x00B8)) -#define INCA_IP_IOM_CIR0_CODR0 (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_IOM_CIR0_CIC0 (1 << 3) -#define INCA_IP_IOM_CIR0_CIC1 (1 << 2) -#define INCA_IP_IOM_CIR0_SG (1 << 1) -#define INCA_IP_IOM_CIR0_BAS (1 << 0) - -/***Command/Indication Transmit 0***/ -#define INCA_IP_IOM_CIX0 ((volatile u32*)(INCA_IP_IOM+ 0x00B8)) -#define INCA_IP_IOM_CIX0_CODX0 (value) (((( 1 << 4) - 1) & (value)) << 4) -#define INCA_IP_IOM_CIX0_TBA2 (1 << 3) -#define INCA_IP_IOM_CIX0_TBA1 (1 << 2) -#define INCA_IP_IOM_CIX0_TBA0 (1 << 1) -#define INCA_IP_IOM_CIX0_BAC (1 << 0) - -/***Command/Indication Receive 1***/ -#define INCA_IP_IOM_CIR1 ((volatile u32*)(INCA_IP_IOM+ 0x00BC)) -#define INCA_IP_IOM_CIR1_CODR1 (value) (((( 1 << 6) - 1) & (value)) << 2) - -/***Command/Indication Transmit 1***/ -#define INCA_IP_IOM_CIX1 ((volatile u32*)(INCA_IP_IOM+ 0x00BC)) -#define INCA_IP_IOM_CIX1_CODX1 (value) (((( 1 << 6) - 1) & (value)) << 2) -#define INCA_IP_IOM_CIX1_CICW (1 << 1) -#define INCA_IP_IOM_CIX1_CI1E (1 << 0) - -/***Controller Data Access Reg. (CH10)***/ -#define INCA_IP_IOM_CDA10 ((volatile u32*)(INCA_IP_IOM+ 0x0100)) -#define INCA_IP_IOM_CDA10_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Controller Data Access Reg. (CH11)***/ -#define INCA_IP_IOM_CDA11 ((volatile u32*)(INCA_IP_IOM+ 0x0104)) -#define INCA_IP_IOM_CDA11_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Controller Data Access Reg. (CH20)***/ -#define INCA_IP_IOM_CDA20 ((volatile u32*)(INCA_IP_IOM+ 0x0108)) -#define INCA_IP_IOM_CDA20_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Controller Data Access Reg. (CH21)***/ -#define INCA_IP_IOM_CDA21 ((volatile u32*)(INCA_IP_IOM+ 0x010C)) -#define INCA_IP_IOM_CDA21_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH10)***/ -#define INCA_IP_IOM_CDA_TSDP10 ((volatile u32*)(INCA_IP_IOM+ 0x0110)) -#define INCA_IP_IOM_CDA_TSDP10_DPS (1 << 7) -#define INCA_IP_IOM_CDA_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH11)***/ -#define INCA_IP_IOM_CDA_TSDP11 ((volatile u32*)(INCA_IP_IOM+ 0x0114)) -#define INCA_IP_IOM_CDA_TSDP11_DPS (1 << 7) -#define INCA_IP_IOM_CDA_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH20)***/ -#define INCA_IP_IOM_CDA_TSDP20 ((volatile u32*)(INCA_IP_IOM+ 0x0118)) -#define INCA_IP_IOM_CDA_TSDP20_DPS (1 << 7) -#define INCA_IP_IOM_CDA_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH21)***/ -#define INCA_IP_IOM_CDA_TSDP21 ((volatile u32*)(INCA_IP_IOM+ 0x011C)) -#define INCA_IP_IOM_CDA_TSDP21_DPS (1 << 7) -#define INCA_IP_IOM_CDA_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH10)***/ -#define INCA_IP_IOM_CO_TSDP10 ((volatile u32*)(INCA_IP_IOM+ 0x0120)) -#define INCA_IP_IOM_CO_TSDP10_DPS (1 << 7) -#define INCA_IP_IOM_CO_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH11)***/ -#define INCA_IP_IOM_CO_TSDP11 ((volatile u32*)(INCA_IP_IOM+ 0x0124)) -#define INCA_IP_IOM_CO_TSDP11_DPS (1 << 7) -#define INCA_IP_IOM_CO_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH20)***/ -#define INCA_IP_IOM_CO_TSDP20 ((volatile u32*)(INCA_IP_IOM+ 0x0128)) -#define INCA_IP_IOM_CO_TSDP20_DPS (1 << 7) -#define INCA_IP_IOM_CO_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH21)***/ -#define INCA_IP_IOM_CO_TSDP21 ((volatile u32*)(INCA_IP_IOM+ 0x012C)) -#define INCA_IP_IOM_CO_TSDP21_DPS (1 << 7) -#define INCA_IP_IOM_CO_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Ctrl. Reg. Contr. Data Access CH1x***/ -#define INCA_IP_IOM_CDA1_CR ((volatile u32*)(INCA_IP_IOM+ 0x0138)) -#define INCA_IP_IOM_CDA1_CR_EN_TBM (1 << 5) -#define INCA_IP_IOM_CDA1_CR_EN_I1 (1 << 4) -#define INCA_IP_IOM_CDA1_CR_EN_I0 (1 << 3) -#define INCA_IP_IOM_CDA1_CR_EN_O1 (1 << 2) -#define INCA_IP_IOM_CDA1_CR_EN_O0 (1 << 1) -#define INCA_IP_IOM_CDA1_CR_SWAP (1 << 0) - -/***Ctrl. Reg. Contr. Data Access CH1x***/ -#define INCA_IP_IOM_CDA2_CR ((volatile u32*)(INCA_IP_IOM+ 0x013C)) -#define INCA_IP_IOM_CDA2_CR_EN_TBM (1 << 5) -#define INCA_IP_IOM_CDA2_CR_EN_I1 (1 << 4) -#define INCA_IP_IOM_CDA2_CR_EN_I0 (1 << 3) -#define INCA_IP_IOM_CDA2_CR_EN_O1 (1 << 2) -#define INCA_IP_IOM_CDA2_CR_EN_O0 (1 << 1) -#define INCA_IP_IOM_CDA2_CR_SWAP (1 << 0) - -/***Control Register B-Channel Data***/ -#define INCA_IP_IOM_BCHA_CR ((volatile u32*)(INCA_IP_IOM+ 0x0144)) -#define INCA_IP_IOM_BCHA_CR_EN_BC2 (1 << 4) -#define INCA_IP_IOM_BCHA_CR_EN_BC1 (1 << 3) - -/***Control Register B-Channel Data***/ -#define INCA_IP_IOM_BCHB_CR ((volatile u32*)(INCA_IP_IOM+ 0x0148)) -#define INCA_IP_IOM_BCHB_CR_EN_BC2 (1 << 4) -#define INCA_IP_IOM_BCHB_CR_EN_BC1 (1 << 3) - -/***Control Reg. for HDLC and CI1 Data***/ -#define INCA_IP_IOM_DCI_CR ((volatile u32*)(INCA_IP_IOM+ 0x014C)) -#define INCA_IP_IOM_DCI_CR_DPS_CI1 (1 << 7) -#define INCA_IP_IOM_DCI_CR_EN_CI1 (1 << 6) -#define INCA_IP_IOM_DCI_CR_EN_D (1 << 5) - -/***Control Reg. for HDLC and CI1 Data***/ -#define INCA_IP_IOM_DCIC_CR ((volatile u32*)(INCA_IP_IOM+ 0x014C)) -#define INCA_IP_IOM_DCIC_CR_DPS_CI0 (1 << 7) -#define INCA_IP_IOM_DCIC_CR_EN_CI0 (1 << 6) -#define INCA_IP_IOM_DCIC_CR_DPS_D (1 << 5) - -/***Control Reg. Serial Data Strobe x***/ -#define INCA_IP_IOM_SDS_CR ((volatile u32*)(INCA_IP_IOM+ 0x0154)) -#define INCA_IP_IOM_SDS_CR_ENS_TSS (1 << 7) -#define INCA_IP_IOM_SDS_CR_ENS_TSS_1 (1 << 6) -#define INCA_IP_IOM_SDS_CR_ENS_TSS_3 (1 << 5) -#define INCA_IP_IOM_SDS_CR_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Control Register IOM Data***/ -#define INCA_IP_IOM_IOM_CR ((volatile u32*)(INCA_IP_IOM+ 0x015C)) -#define INCA_IP_IOM_IOM_CR_SPU (1 << 7) -#define INCA_IP_IOM_IOM_CR_CI_CS (1 << 5) -#define INCA_IP_IOM_IOM_CR_TIC_DIS (1 << 4) -#define INCA_IP_IOM_IOM_CR_EN_BCL (1 << 3) -#define INCA_IP_IOM_IOM_CR_CLKM (1 << 2) -#define INCA_IP_IOM_IOM_CR_Res (1 << 1) -#define INCA_IP_IOM_IOM_CR_DIS_IOM (1 << 0) - -/***Synchronous Transfer Interrupt***/ -#define INCA_IP_IOM_STI ((volatile u32*)(INCA_IP_IOM+ 0x0160)) -#define INCA_IP_IOM_STI_STOV21 (1 << 7) -#define INCA_IP_IOM_STI_STOV20 (1 << 6) -#define INCA_IP_IOM_STI_STOV11 (1 << 5) -#define INCA_IP_IOM_STI_STOV10 (1 << 4) -#define INCA_IP_IOM_STI_STI21 (1 << 3) -#define INCA_IP_IOM_STI_STI20 (1 << 2) -#define INCA_IP_IOM_STI_STI11 (1 << 1) -#define INCA_IP_IOM_STI_STI10 (1 << 0) - -/***Acknowledge Synchronous Transfer Interrupt***/ -#define INCA_IP_IOM_ASTI ((volatile u32*)(INCA_IP_IOM+ 0x0160)) -#define INCA_IP_IOM_ASTI_ACK21 (1 << 3) -#define INCA_IP_IOM_ASTI_ACK20 (1 << 2) -#define INCA_IP_IOM_ASTI_ACK11 (1 << 1) -#define INCA_IP_IOM_ASTI_ACK10 (1 << 0) - -/***Mask Synchronous Transfer Interrupt***/ -#define INCA_IP_IOM_MSTI ((volatile u32*)(INCA_IP_IOM+ 0x0164)) -#define INCA_IP_IOM_MSTI_STOV21 (1 << 7) -#define INCA_IP_IOM_MSTI_STOV20 (1 << 6) -#define INCA_IP_IOM_MSTI_STOV11 (1 << 5) -#define INCA_IP_IOM_MSTI_STOV10 (1 << 4) -#define INCA_IP_IOM_MSTI_STI21 (1 << 3) -#define INCA_IP_IOM_MSTI_STI20 (1 << 2) -#define INCA_IP_IOM_MSTI_STI11 (1 << 1) -#define INCA_IP_IOM_MSTI_STI10 (1 << 0) - -/***Configuration Register for Serial Data Strobes***/ -#define INCA_IP_IOM_SDS_CONF ((volatile u32*)(INCA_IP_IOM+ 0x0168)) -#define INCA_IP_IOM_SDS_CONF_SDS_BCL (1 << 0) - -/***Monitoring CDA Bits***/ -#define INCA_IP_IOM_MCDA ((volatile u32*)(INCA_IP_IOM+ 0x016C)) -#define INCA_IP_IOM_MCDA_MCDA21 (value) (((( 1 << 2) - 1) & (value)) << 6) -#define INCA_IP_IOM_MCDA_MCDA20 (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_IOM_MCDA_MCDA11 (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_IOM_MCDA_MCDA10 (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : ASC register address and bits */ -/***********************************************************************/ - -#define INCA_IP_ASC (0xB8000400) -/***********************************************************************/ - - -/***ASC Port Input Select Register***/ -#define INCA_IP_ASC_ASC_PISEL ((volatile u32*)(INCA_IP_ASC+ 0x0004)) -#define INCA_IP_ASC_ASC_PISEL_RIS (1 << 0) - -/***ASC Control Register***/ -#define INCA_IP_ASC_ASC_CON ((volatile u32*)(INCA_IP_ASC+ 0x0010)) -#define INCA_IP_ASC_ASC_CON_R (1 << 15) -#define INCA_IP_ASC_ASC_CON_LB (1 << 14) -#define INCA_IP_ASC_ASC_CON_BRS (1 << 13) -#define INCA_IP_ASC_ASC_CON_ODD (1 << 12) -#define INCA_IP_ASC_ASC_CON_FDE (1 << 11) -#define INCA_IP_ASC_ASC_CON_OE (1 << 10) -#define INCA_IP_ASC_ASC_CON_FE (1 << 9) -#define INCA_IP_ASC_ASC_CON_PE (1 << 8) -#define INCA_IP_ASC_ASC_CON_OEN (1 << 7) -#define INCA_IP_ASC_ASC_CON_FEN (1 << 6) -#define INCA_IP_ASC_ASC_CON_PENRXDI (1 << 5) -#define INCA_IP_ASC_ASC_CON_REN (1 << 4) -#define INCA_IP_ASC_ASC_CON_STP (1 << 3) -#define INCA_IP_ASC_ASC_CON_M (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***ASC Write Hardware Modified Control Register***/ -#define INCA_IP_ASC_ASC_WHBCON ((volatile u32*)(INCA_IP_ASC+ 0x0050)) -#define INCA_IP_ASC_ASC_WHBCON_SETOE (1 << 13) -#define INCA_IP_ASC_ASC_WHBCON_SETFE (1 << 12) -#define INCA_IP_ASC_ASC_WHBCON_SETPE (1 << 11) -#define INCA_IP_ASC_ASC_WHBCON_CLROE (1 << 10) -#define INCA_IP_ASC_ASC_WHBCON_CLRFE (1 << 9) -#define INCA_IP_ASC_ASC_WHBCON_CLRPE (1 << 8) -#define INCA_IP_ASC_ASC_WHBCON_SETREN (1 << 5) -#define INCA_IP_ASC_ASC_WHBCON_CLRREN (1 << 4) - -/***ASC Baudrate Timer/Reload Register***/ -#define INCA_IP_ASC_ASC_BTR ((volatile u32*)(INCA_IP_ASC+ 0x0014)) -#define INCA_IP_ASC_ASC_BTR_BR_VALUE (value) (((( 1 << 13) - 1) & (value)) << 0) - -/***ASC Fractional Divider Register***/ -#define INCA_IP_ASC_ASC_FDV ((volatile u32*)(INCA_IP_ASC+ 0x0018)) -#define INCA_IP_ASC_ASC_FDV_FD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0) - -/***ASC IrDA Pulse Mode/Width Register***/ -#define INCA_IP_ASC_ASC_PMW ((volatile u32*)(INCA_IP_ASC+ 0x001C)) -#define INCA_IP_ASC_ASC_PMW_IRPW (1 << 8) -#define INCA_IP_ASC_ASC_PMW_PW_VALUE (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***ASC Transmit Buffer Register***/ -#define INCA_IP_ASC_ASC_TBUF ((volatile u32*)(INCA_IP_ASC+ 0x0020)) -#define INCA_IP_ASC_ASC_TBUF_TD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0) - -/***ASC Receive Buffer Register***/ -#define INCA_IP_ASC_ASC_RBUF ((volatile u32*)(INCA_IP_ASC+ 0x0024)) -#define INCA_IP_ASC_ASC_RBUF_RD_VALUE (value) (((( 1 << 9) - 1) & (value)) << 0) - -/***ASC Autobaud Control Register***/ -#define INCA_IP_ASC_ASC_ABCON ((volatile u32*)(INCA_IP_ASC+ 0x0030)) -#define INCA_IP_ASC_ASC_ABCON_RXINV (1 << 11) -#define INCA_IP_ASC_ASC_ABCON_TXINV (1 << 10) -#define INCA_IP_ASC_ASC_ABCON_ABEM (value) (((( 1 << 2) - 1) & (value)) << 8) -#define INCA_IP_ASC_ASC_ABCON_FCDETEN (1 << 4) -#define INCA_IP_ASC_ASC_ABCON_ABDETEN (1 << 3) -#define INCA_IP_ASC_ASC_ABCON_ABSTEN (1 << 2) -#define INCA_IP_ASC_ASC_ABCON_AUREN (1 << 1) -#define INCA_IP_ASC_ASC_ABCON_ABEN (1 << 0) - -/***Receive FIFO Control Register***/ -#define INCA_IP_ASC_RXFCON ((volatile u32*)(INCA_IP_ASC+ 0x0040)) -#define INCA_IP_ASC_RXFCON_RXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_ASC_RXFCON_RXTMEN (1 << 2) -#define INCA_IP_ASC_RXFCON_RXFFLU (1 << 1) -#define INCA_IP_ASC_RXFCON_RXFEN (1 << 0) - -/***Transmit FIFO Control Register***/ -#define INCA_IP_ASC_TXFCON ((volatile u32*)(INCA_IP_ASC+ 0x0044)) -#define INCA_IP_ASC_TXFCON_TXFITL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_ASC_TXFCON_TXTMEN (1 << 2) -#define INCA_IP_ASC_TXFCON_TXFFLU (1 << 1) -#define INCA_IP_ASC_TXFCON_TXFEN (1 << 0) - -/***FIFO Status Register***/ -#define INCA_IP_ASC_FSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0048)) -#define INCA_IP_ASC_FSTAT_TXFFL (value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP_ASC_FSTAT_RXFFL (value) (((( 1 << 6) - 1) & (value)) << 0) - -/***ASC Write HW Modified Autobaud Control Register***/ -#define INCA_IP_ASC_ASC_WHBABCON ((volatile u32*)(INCA_IP_ASC+ 0x0054)) -#define INCA_IP_ASC_ASC_WHBABCON_SETABEN (1 << 1) -#define INCA_IP_ASC_ASC_WHBABCON_CLRABEN (1 << 0) - -/***ASC Autobaud Status Register***/ -#define INCA_IP_ASC_ASC_ABSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0034)) -#define INCA_IP_ASC_ASC_ABSTAT_DETWAIT (1 << 4) -#define INCA_IP_ASC_ASC_ABSTAT_SCCDET (1 << 3) -#define INCA_IP_ASC_ASC_ABSTAT_SCSDET (1 << 2) -#define INCA_IP_ASC_ASC_ABSTAT_FCCDET (1 << 1) -#define INCA_IP_ASC_ASC_ABSTAT_FCSDET (1 << 0) - -/***ASC Write HW Modified Autobaud Status Register***/ -#define INCA_IP_ASC_ASC_WHBABSTAT ((volatile u32*)(INCA_IP_ASC+ 0x0058)) -#define INCA_IP_ASC_ASC_WHBABSTAT_SETDETWAIT (1 << 9) -#define INCA_IP_ASC_ASC_WHBABSTAT_CLRDETWAIT (1 << 8) -#define INCA_IP_ASC_ASC_WHBABSTAT_SETSCCDET (1 << 7) -#define INCA_IP_ASC_ASC_WHBABSTAT_CLRSCCDET (1 << 6) -#define INCA_IP_ASC_ASC_WHBABSTAT_SETSCSDET (1 << 5) -#define INCA_IP_ASC_ASC_WHBABSTAT_CLRSCSDET (1 << 4) -#define INCA_IP_ASC_ASC_WHBABSTAT_SETFCCDET (1 << 3) -#define INCA_IP_ASC_ASC_WHBABSTAT_CLRFCCDET (1 << 2) -#define INCA_IP_ASC_ASC_WHBABSTAT_SETFCSDET (1 << 1) -#define INCA_IP_ASC_ASC_WHBABSTAT_CLRFCSDET (1 << 0) - -/***ASC Clock Control Register***/ -#define INCA_IP_ASC_ASC_CLC ((volatile u32*)(INCA_IP_ASC+ 0x0000)) -#define INCA_IP_ASC_ASC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_ASC_ASC_CLC_DISS (1 << 1) -#define INCA_IP_ASC_ASC_CLC_DISR (1 << 0) - -/***********************************************************************/ -/* Module : DMA register address and bits */ -/***********************************************************************/ - -#define INCA_IP_DMA (0xBF108000) -/***********************************************************************/ - - -/***DMA RX Channel 0 Command Register***/ -#define INCA_IP_DMA_DMA_RXCCR0 ((volatile u32*)(INCA_IP_DMA+ 0x0800)) -#define INCA_IP_DMA_DMA_RXCCR0_LBE (1 << 31) -#define INCA_IP_DMA_DMA_RXCCR0_HPEN (1 << 30) -#define INCA_IP_DMA_DMA_RXCCR0_INIT (1 << 2) -#define INCA_IP_DMA_DMA_RXCCR0_OFF (1 << 1) -#define INCA_IP_DMA_DMA_RXCCR0_HR (1 << 0) - -/***DMA RX Channel 1 Command Register***/ -#define INCA_IP_DMA_DMA_RXCCR1 ((volatile u32*)(INCA_IP_DMA+ 0x0804)) -#define INCA_IP_DMA_DMA_RXCCR1_LBE (1 << 31) -#define INCA_IP_DMA_DMA_RXCCR1_HPEN (1 << 30) -#define INCA_IP_DMA_DMA_RXCCR1_INIT (1 << 2) -#define INCA_IP_DMA_DMA_RXCCR1_OFF (1 << 1) -#define INCA_IP_DMA_DMA_RXCCR1_HR (1 << 0) - -/***DMA Receive Interrupt Status Register***/ -#define INCA_IP_DMA_DMA_RXISR ((volatile u32*)(INCA_IP_DMA+ 0x0808)) -#define INCA_IP_DMA_DMA_RXISR_RDERRx (value) (((( 1 << 2) - 1) & (value)) << 8) -#define INCA_IP_DMA_DMA_RXISR_CMDCPTx (value) (((( 1 << 2) - 1) & (value)) << 6) -#define INCA_IP_DMA_DMA_RXISR_EOPx (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_DMA_DMA_RXISR_CPTx (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_DMA_DMA_RXISR_HLDx (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***DMA Receive Interrupt Mask Register***/ -#define INCA_IP_DMA_DMA_RXIMR ((volatile u32*)(INCA_IP_DMA+ 0x080C)) -#define INCA_IP_DMA_DMA_RXIMR_RDERRx (value) (((( 1 << 2) - 1) & (value)) << 8) -#define INCA_IP_DMA_DMA_RXIMR_CMDCPTx (value) (((( 1 << 2) - 1) & (value)) << 6) -#define INCA_IP_DMA_DMA_RXIMR_EOPx (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_DMA_DMA_RXIMR_CPTx (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_DMA_DMA_RXIMR_HLDx (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***DMA First Receive Descriptor Addr. for Rx Channel 0 -***/ -#define INCA_IP_DMA_DMA_RXFRDA0 ((volatile u32*)(INCA_IP_DMA+ 0x0810)) -#define INCA_IP_DMA_DMA_RXFRDA0_RXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***DMA First Receive Descriptor Addr. for Rx Channel 1 -***/ -#define INCA_IP_DMA_DMA_RXFRDA1 ((volatile u32*)(INCA_IP_DMA+ 0x0814)) -#define INCA_IP_DMA_DMA_RXFRDA1_RXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***DMA Receive Channel Polling Time***/ -#define INCA_IP_DMA_DMA_RXPOLL ((volatile u32*)(INCA_IP_DMA+ 0x0818)) -#define INCA_IP_DMA_DMA_RXPOLL_BSZ1 (value) (((( 1 << 2) - 1) & (value)) << 30) -#define INCA_IP_DMA_DMA_RXPOLL_BSZ0 (value) (((( 1 << 2) - 1) & (value)) << 28) -#define INCA_IP_DMA_DMA_RXPOLL_RXPOLLTIME (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***DMA TX Channel 0 Command Register (Voice Port)***/ -#define INCA_IP_DMA_DMA_TXCCR0 ((volatile u32*)(INCA_IP_DMA+ 0x0880)) -#define INCA_IP_DMA_DMA_TXCCR0_LBE (1 << 31) -#define INCA_IP_DMA_DMA_TXCCR0_HPEN (1 << 30) -#define INCA_IP_DMA_DMA_TXCCR0_HR (1 << 2) -#define INCA_IP_DMA_DMA_TXCCR0_OFF (1 << 1) -#define INCA_IP_DMA_DMA_TXCCR0_INIT (1 << 0) - -/***DMA TX Channel 1 Command Register (Mangmt Port)***/ -#define INCA_IP_DMA_DMA_TXCCR1 ((volatile u32*)(INCA_IP_DMA+ 0x0884)) -#define INCA_IP_DMA_DMA_TXCCR1_LBE (1 << 31) -#define INCA_IP_DMA_DMA_TXCCR1_HPEN (1 << 30) -#define INCA_IP_DMA_DMA_TXCCR1_HR (1 << 2) -#define INCA_IP_DMA_DMA_TXCCR1_OFF (1 << 1) -#define INCA_IP_DMA_DMA_TXCCR1_INIT (1 << 0) - -/***DMA TX Channel 2 Command Register (SSC Port)***/ -#define INCA_IP_DMA_DMA_TXCCR2 ((volatile u32*)(INCA_IP_DMA+ 0x0888)) -#define INCA_IP_DMA_DMA_TXCCR2_LBE (1 << 31) -#define INCA_IP_DMA_DMA_TXCCR2_HPEN (1 << 30) -#define INCA_IP_DMA_DMA_TXCCR2_HBF (1 << 29) -#define INCA_IP_DMA_DMA_TXCCR2_HR (1 << 2) -#define INCA_IP_DMA_DMA_TXCCR2_OFF (1 << 1) -#define INCA_IP_DMA_DMA_TXCCR2_INIT (1 << 0) - -/***DMA First Receive Descriptor Addr. for Tx Channel 0 -***/ -#define INCA_IP_DMA_DMA_TXFRDA0 ((volatile u32*)(INCA_IP_DMA+ 0x08A0)) -#define INCA_IP_DMA_DMA_TXFRDA0_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***DMA First Receive Descriptor Addr. for Tx Channel 1 -***/ -#define INCA_IP_DMA_DMA_TXFRDA1 ((volatile u32*)(INCA_IP_DMA+ 0x08A4)) -#define INCA_IP_DMA_DMA_TXFRDA1_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***DMA First Receive Descriptor Addr. for Tx Channel 2 -***/ -#define INCA_IP_DMA_DMA_TXFRDA2 ((volatile u32*)(INCA_IP_DMA+ 0x08A8)) -#define INCA_IP_DMA_DMA_TXFRDA2_TXFRDA (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***DMA Transmit Channel Arbitration Register***/ -#define INCA_IP_DMA_DMA_TXWGT ((volatile u32*)(INCA_IP_DMA+ 0x08C0)) -#define INCA_IP_DMA_DMA_TXWGT_TX2PR (value) (((( 1 << 2) - 1) & (value)) << 4) -#define INCA_IP_DMA_DMA_TXWGT_TX1PRI (value) (((( 1 << 2) - 1) & (value)) << 2) -#define INCA_IP_DMA_DMA_TXWGT_TX0PRI (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***DMA Transmit Channel Polling Time***/ -#define INCA_IP_DMA_DMA_TXPOLL ((volatile u32*)(INCA_IP_DMA+ 0x08C4)) -#define INCA_IP_DMA_DMA_TXPOLL_BSZ2 (value) (((( 1 << 2) - 1) & (value)) << 30) -#define INCA_IP_DMA_DMA_TXPOLL_BSZ1 (value) (((( 1 << 2) - 1) & (value)) << 28) -#define INCA_IP_DMA_DMA_TXPOLL_BSZ0 (value) (((( 1 << 2) - 1) & (value)) << 26) -#define INCA_IP_DMA_DMA_TXPOLL_TXPOLLTIME (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***DMA Transmit Interrupt Status Register***/ -#define INCA_IP_DMA_DMA_TXISR ((volatile u32*)(INCA_IP_DMA+ 0x08C8)) -#define INCA_IP_DMA_DMA_TXISR_RDERRx (value) (((( 1 << 3) - 1) & (value)) << 12) -#define INCA_IP_DMA_DMA_TXISR_HLDx (value) (((( 1 << 3) - 1) & (value)) << 9) -#define INCA_IP_DMA_DMA_TXISR_CPTx (value) (((( 1 << 3) - 1) & (value)) << 6) -#define INCA_IP_DMA_DMA_TXISR_EOPx (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_DMA_DMA_TXISR_CMDCPTx (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***DMA Transmit Interrupt Mask Register***/ -#define INCA_IP_DMA_DMA_TXIMR ((volatile u32*)(INCA_IP_DMA+ 0x08CC)) -#define INCA_IP_DMA_DMA_TXIMR_RDERRx (value) (((( 1 << 3) - 1) & (value)) << 12) -#define INCA_IP_DMA_DMA_TXIMR_HLDx (value) (((( 1 << 3) - 1) & (value)) << 9) -#define INCA_IP_DMA_DMA_TXIMR_CPTx (value) (((( 1 << 3) - 1) & (value)) << 6) -#define INCA_IP_DMA_DMA_TXIMR_EOPx (value) (((( 1 << 3) - 1) & (value)) << 3) -#define INCA_IP_DMA_DMA_TXIMR_CMDCPTx (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : Debug register address and bits */ -/***********************************************************************/ - -#define INCA_IP_Debug (0xBF106000) -/***********************************************************************/ - - -/***MCD Break Bus Switch Register***/ -#define INCA_IP_Debug_MCD_BBS ((volatile u32*)(INCA_IP_Debug+ 0x0000)) -#define INCA_IP_Debug_MCD_BBS_BTP1 (1 << 19) -#define INCA_IP_Debug_MCD_BBS_BTP0 (1 << 18) -#define INCA_IP_Debug_MCD_BBS_BSP1 (1 << 17) -#define INCA_IP_Debug_MCD_BBS_BSP0 (1 << 16) -#define INCA_IP_Debug_MCD_BBS_BT5EN (1 << 15) -#define INCA_IP_Debug_MCD_BBS_BT4EN (1 << 14) -#define INCA_IP_Debug_MCD_BBS_BT5 (1 << 13) -#define INCA_IP_Debug_MCD_BBS_BT4 (1 << 12) -#define INCA_IP_Debug_MCD_BBS_BS5EN (1 << 7) -#define INCA_IP_Debug_MCD_BBS_BS4EN (1 << 6) -#define INCA_IP_Debug_MCD_BBS_BS5 (1 << 5) -#define INCA_IP_Debug_MCD_BBS_BS4 (1 << 4) - -/***MCD Multiplexer Control Register***/ -#define INCA_IP_Debug_MCD_MCR ((volatile u32*)(INCA_IP_Debug+ 0x0008)) -#define INCA_IP_Debug_MCD_MCR_MUX5 (1 << 4) -#define INCA_IP_Debug_MCD_MCR_MUX4 (1 << 3) -#define INCA_IP_Debug_MCD_MCR_MUX1 (1 << 0) - -/***********************************************************************/ -/* Module : TSF register address and bits */ -/***********************************************************************/ - -#define INCA_IP_TSF (0xB8000900) -/***********************************************************************/ - - -/***TSF Configuration Register (0000H)***/ -#define INCA_IP_TSF_TSF_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0000)) -#define INCA_IP_TSF_TSF_CONF_PWMEN (1 << 2) -#define INCA_IP_TSF_TSF_CONF_LEDEN (1 << 1) -#define INCA_IP_TSF_TSF_CONF_KEYEN (1 << 0) - -/***Key scan Configuration Register (0004H)***/ -#define INCA_IP_TSF_KEY_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0004)) -#define INCA_IP_TSF_KEY_CONF_SL (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Scan Register Line 0 and 1 (0008H)***/ -#define INCA_IP_TSF_SREG01 ((volatile u32*)(INCA_IP_TSF+ 0x0008)) -#define INCA_IP_TSF_SREG01_RES1x (value) (((( 1 << 12) - 1) & (value)) << 16) -#define INCA_IP_TSF_SREG01_RES0x (value) (((( 1 << 13) - 1) & (value)) << 0) - -/***Scan Register Line 2 and 3 (000CH)***/ -#define INCA_IP_TSF_SREG23 ((volatile u32*)(INCA_IP_TSF+ 0x000C)) -#define INCA_IP_TSF_SREG23_RES3x (value) (((( 1 << 10) - 1) & (value)) << 16) -#define INCA_IP_TSF_SREG23_RES2x (value) (((( 1 << 11) - 1) & (value)) << 0) - -/***Scan Register Line 4, 5 and 6 (0010H)***/ -#define INCA_IP_TSF_SREG456 ((volatile u32*)(INCA_IP_TSF+ 0x0010)) -#define INCA_IP_TSF_SREG456_RES6x (value) (((( 1 << 7) - 1) & (value)) << 24) -#define INCA_IP_TSF_SREG456_RES5x (value) (((( 1 << 8) - 1) & (value)) << 16) -#define INCA_IP_TSF_SREG456_RES4x (value) (((( 1 << 9) - 1) & (value)) << 0) - -/***Scan Register Line 7 to 12 (0014H)***/ -#define INCA_IP_TSF_SREG7to12 ((volatile u32*)(INCA_IP_TSF+ 0x0014)) -#define INCA_IP_TSF_SREG7to12_RES12x (1 << 28) -#define INCA_IP_TSF_SREG7to12_RES11x (value) (((( 1 << 2) - 1) & (value)) << 24) -#define INCA_IP_TSF_SREG7to12_RES10x (value) (((( 1 << 3) - 1) & (value)) << 20) -#define INCA_IP_TSF_SREG7to12_RES9x (value) (((( 1 << 4) - 1) & (value)) << 16) -#define INCA_IP_TSF_SREG7to12_RES8x (value) (((( 1 << 5) - 1) & (value)) << 8) -#define INCA_IP_TSF_SREG7to12_RES7x (value) (((( 1 << 6) - 1) & (value)) << 0) - -/***LEDMUX Configuration Register (0018H)***/ -#define INCA_IP_TSF_LEDMUX_CONF ((volatile u32*)(INCA_IP_TSF+ 0x0018)) -#define INCA_IP_TSF_LEDMUX_CONF_ETL1 (1 << 25) -#define INCA_IP_TSF_LEDMUX_CONF_ESTA1 (1 << 24) -#define INCA_IP_TSF_LEDMUX_CONF_EDPX1 (1 << 23) -#define INCA_IP_TSF_LEDMUX_CONF_EACT1 (1 << 22) -#define INCA_IP_TSF_LEDMUX_CONF_ESPD1 (1 << 21) -#define INCA_IP_TSF_LEDMUX_CONF_ETL0 (1 << 20) -#define INCA_IP_TSF_LEDMUX_CONF_ESTA0 (1 << 19) -#define INCA_IP_TSF_LEDMUX_CONF_EDPX0 (1 << 18) -#define INCA_IP_TSF_LEDMUX_CONF_EACT0 (1 << 17) -#define INCA_IP_TSF_LEDMUX_CONF_ESPD0 (1 << 16) -#define INCA_IP_TSF_LEDMUX_CONF_INV (1 << 1) -#define INCA_IP_TSF_LEDMUX_CONF_NCOL (1 << 0) - -/***LED Register (001CH)***/ -#define INCA_IP_TSF_LED_REG ((volatile u32*)(INCA_IP_TSF+ 0x001C)) -#define INCA_IP_TSF_LED_REG_Lxy (value) (((( 1 << 24) - 1) & (value)) << 0) - -/***Pulse Width Modulator 1 and 2 Register (0020H)***/ -#define INCA_IP_TSF_PWM12 ((volatile u32*)(INCA_IP_TSF+ 0x0020)) -#define INCA_IP_TSF_PWM12_PW2PW1 (value) (((( 1 << NaN) - 1) & (value)) << NaN) - -/***********************************************************************/ -/* Module : Ports register address and bits */ -/***********************************************************************/ - -#define INCA_IP_Ports (0xB8000A00) -/***********************************************************************/ - - -/***Port 1 Data Output Register (0020H)***/ -#define INCA_IP_Ports_P1_OUT ((volatile u32*)(INCA_IP_Ports+ 0x0020)) -#define INCA_IP_Ports_P1_OUT_P(value) (1 << value) - - -/***Port 2 Data Output Register (0040H)***/ -#define INCA_IP_Ports_P2_OUT ((volatile u32*)(INCA_IP_Ports+ 0x0040)) -#define INCA_IP_Ports_P2_OUT_P(value) (1 << value) - - -/***Port 1 Data Input Register (0024H)***/ -#define INCA_IP_Ports_P1_IN ((volatile u32*)(INCA_IP_Ports+ 0x0024)) -#define INCA_IP_Ports_P1_IN_P(value) (1 << value) - - -/***Port 2 Data Input Register (0044H)***/ -#define INCA_IP_Ports_P2_IN ((volatile u32*)(INCA_IP_Ports+ 0x0044)) -#define INCA_IP_Ports_P2_IN_P(value) (1 << value) - - -/***Port 1 Direction Register (0028H)***/ -#define INCA_IP_Ports_P1_DIR ((volatile u32*)(INCA_IP_Ports+ 0x0028)) -#define INCA_IP_Ports_P1_DIR_Port1P(value) (1 << value) - -#define INCA_IP_Ports_P1_DIR_Port2Pn (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***Port 2 Direction Register (0048H)***/ -#define INCA_IP_Ports_P2_DIR ((volatile u32*)(INCA_IP_Ports+ 0x0048)) -#define INCA_IP_Ports_P2_DIR_Port1P(value) (1 << value) - -#define INCA_IP_Ports_P2_DIR_Port2Pn (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***Port 0 Alternate Function Select Register 0 (000C H) -***/ -#define INCA_IP_Ports_P0_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x000C)) -#define INCA_IP_Ports_P0_ALTSEL_Port0P(value) (1 << value) - - -/***Port 1 Alternate Function Select Register 0 (002C H) -***/ -#define INCA_IP_Ports_P1_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x002C)) -#define INCA_IP_Ports_P1_ALTSEL_Port1P(value) (1 << value) - -#define INCA_IP_Ports_P1_ALTSEL_Port2P(value) (1 << value) - - -/***Port 2 Alternate Function Select Register 0 (004C H) -***/ -#define INCA_IP_Ports_P2_ALTSEL ((volatile u32*)(INCA_IP_Ports+ 0x004C)) -#define INCA_IP_Ports_P2_ALTSEL_Port1P(value) (1 << value) - -#define INCA_IP_Ports_P2_ALTSEL_Port2P(value) (1 << value) - - -/***Port 0 Input Schmitt-Trigger Off Register (0010 H) -***/ -#define INCA_IP_Ports_P0_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0010)) -#define INCA_IP_Ports_P0_STOFF_Port0P(value) (1 << value) - - -/***Port 1 Input Schmitt-Trigger Off Register (0030 H) -***/ -#define INCA_IP_Ports_P1_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0030)) -#define INCA_IP_Ports_P1_STOFF_Port1P(value) (1 << value) - -#define INCA_IP_Ports_P1_STOFF_Port2P(value) (1 << value) - - -/***Port 2 Input Schmitt-Trigger Off Register (0050 H) -***/ -#define INCA_IP_Ports_P2_STOFF ((volatile u32*)(INCA_IP_Ports+ 0x0050)) -#define INCA_IP_Ports_P2_STOFF_Port1P(value) (1 << value) - -#define INCA_IP_Ports_P2_STOFF_Port2P(value) (1 << value) - - -/***Port 2 Open Drain Control Register (0054H)***/ -#define INCA_IP_Ports_P2_OD ((volatile u32*)(INCA_IP_Ports+ 0x0054)) -#define INCA_IP_Ports_P2_OD_Port2P(value) (1 << value) - - -/***Port 0 Pull Up Device Enable Register (0018 H)***/ -#define INCA_IP_Ports_P0_PUDEN ((volatile u32*)(INCA_IP_Ports+ 0x0018)) -#define INCA_IP_Ports_P0_PUDEN_Port0P(value) (1 << value) - - -/***Port 2 Pull Up Device Enable Register (0058 H)***/ -#define INCA_IP_Ports_P2_PUDEN ((volatile u32*)(INCA_IP_Ports+ 0x0058)) -#define INCA_IP_Ports_P2_PUDEN_Port2P(value) (1 << value) - -#define INCA_IP_Ports_P2_PUDEN_Port2P(value) (1 << value) - - -/***Port 0 Pull Up/Pull Down Select Register (001C H)***/ -#define INCA_IP_Ports_P0_PUDSEL ((volatile u32*)(INCA_IP_Ports+ 0x001C)) -#define INCA_IP_Ports_P0_PUDSEL_Port0P(value) (1 << value) - - -/***Port 2 Pull Up/Pull Down Select Register (005C H)***/ -#define INCA_IP_Ports_P2_PUDSEL ((volatile u32*)(INCA_IP_Ports+ 0x005C)) -#define INCA_IP_Ports_P2_PUDSEL_Port2P(value) (1 << value) - -#define INCA_IP_Ports_P2_PUDSEL_Port2P(value) (1 << value) - - -/***********************************************************************/ -/* Module : DES/3DES register address and bits */ -/***********************************************************************/ - -#define INCA_IP_DES_3DES (0xB8000800) -/***********************************************************************/ - - -/***DES Input Data High Register***/ -#define INCA_IP_DES_3DES_DES_IHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0000)) -#define INCA_IP_DES_3DES_DES_IHR_IH(value) (1 << value) - - -/***DES Input Data Low Register***/ -#define INCA_IP_DES_3DES_DES_ILR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0004)) -#define INCA_IP_DES_3DES_DES_ILR_IL(value) (1 << value) - - -/***DES Key #1 High Register***/ -#define INCA_IP_DES_3DES_DES_K1HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0008)) -#define INCA_IP_DES_3DES_DES_K1HR_K1H(value) (1 << value) - - -/***DES Key #1 Low Register***/ -#define INCA_IP_DES_3DES_DES_K1LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x000C)) -#define INCA_IP_DES_3DES_DES_K1LR_K1L(value) (1 << value) - - -/***DES Key #2 High Register***/ -#define INCA_IP_DES_3DES_DES_K2HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0010)) -#define INCA_IP_DES_3DES_DES_K2HR_K2H(value) (1 << value) - - -/***DES Key #2 Low Register***/ -#define INCA_IP_DES_3DES_DES_K2LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0014)) -#define INCA_IP_DES_3DES_DES_K2LR_K2L(value) (1 << value) - - -/***DES Key #3 High Register***/ -#define INCA_IP_DES_3DES_DES_K3HR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0018)) -#define INCA_IP_DES_3DES_DES_K3HR_K3H(value) (1 << value) - - -/***DES Key #3 Low Register***/ -#define INCA_IP_DES_3DES_DES_K3LR ((volatile u32*)(INCA_IP_DES_3DES+ 0x001C)) -#define INCA_IP_DES_3DES_DES_K3LR_K3L(value) (1 << value) - - -/***DES Initialization Vector High Register***/ -#define INCA_IP_DES_3DES_DES_IVHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0020)) -#define INCA_IP_DES_3DES_DES_IVHR_IVH(value) (1 << value) - - -/***DES Initialization Vector Low Register***/ -#define INCA_IP_DES_3DES_DES_IVLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0024)) -#define INCA_IP_DES_3DES_DES_IVLR_IVL(value) (1 << value) - - -/***DES Control Register***/ -#define INCA_IP_DES_3DES_DES_CONTROLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0028)) -#define INCA_IP_DES_3DES_DES_CONTROLR_KRE (1 << 31) -#define INCA_IP_DES_3DES_DES_CONTROLR_DAU (1 << 16) -#define INCA_IP_DES_3DES_DES_CONTROLR_F(value) (1 << value) - -#define INCA_IP_DES_3DES_DES_CONTROLR_O(value) (1 << value) - -#define INCA_IP_DES_3DES_DES_CONTROLR_GO (1 << 8) -#define INCA_IP_DES_3DES_DES_CONTROLR_STP (1 << 7) -#define INCA_IP_DES_3DES_DES_CONTROLR_IEN (1 << 6) -#define INCA_IP_DES_3DES_DES_CONTROLR_BUS (1 << 5) -#define INCA_IP_DES_3DES_DES_CONTROLR_SM (1 << 4) -#define INCA_IP_DES_3DES_DES_CONTROLR_E_D (1 << 3) -#define INCA_IP_DES_3DES_DES_CONTROLR_M(value) (1 << value) - - -/***DES Output Data High Register***/ -#define INCA_IP_DES_3DES_DES_OHR ((volatile u32*)(INCA_IP_DES_3DES+ 0x002C)) -#define INCA_IP_DES_3DES_DES_OHR_OH(value) (1 << value) - - -/***DES Output Data Low Register***/ -#define INCA_IP_DES_3DES_DES_OLR ((volatile u32*)(INCA_IP_DES_3DES+ 0x0030)) -#define INCA_IP_DES_3DES_DES_OLR_OL(value) (1 << value) - - -/***********************************************************************/ -/* Module : AES register address and bits */ -/***********************************************************************/ - -#define INCA_IP_AES (0xB8000880) -/***********************************************************************/ - - -/***AES Input Data 3 Register***/ -#define INCA_IP_AES_AES_ID3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_ID3R_I(value) (1 << value) - - -/***AES Input Data 2 Register***/ -#define INCA_IP_AES_AES_ID2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_ID2R_I(value) (1 << value) - - -/***AES Input Data 1 Register***/ -#define INCA_IP_AES_AES_ID1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_ID1R_I(value) (1 << value) - - -/***AES Input Data 0 Register***/ -#define INCA_IP_AES_AES_ID0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_ID0R_I(value) (1 << value) - - -/***AES Output Data 3 Register***/ -#define INCA_IP_AES_AES_OD3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_OD3R_O(value) (1 << value) - - -/***AES Output Data 2 Register***/ -#define INCA_IP_AES_AES_OD2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_OD2R_O(value) (1 << value) - - -/***AES Output Data 1 Register***/ -#define INCA_IP_AES_AES_OD1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_OD1R_O(value) (1 << value) - - -/***AES Output Data 0 Register***/ -#define INCA_IP_AES_AES_OD0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_OD0R_O(value) (1 << value) - - -/***AES Key 7 Register***/ -#define INCA_IP_AES_AES_K7R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K7R_K(value) (1 << value) - - -/***AES Key 6 Register***/ -#define INCA_IP_AES_AES_K6R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K6R_K(value) (1 << value) - - -/***AES Key 5 Register***/ -#define INCA_IP_AES_AES_K5R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K5R_K(value) (1 << value) - - -/***AES Key 4 Register***/ -#define INCA_IP_AES_AES_K4R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K4R_K(value) (1 << value) - - -/***AES Key 3 Register***/ -#define INCA_IP_AES_AES_K3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K3R_K(value) (1 << value) - - -/***AES Key 2 Register***/ -#define INCA_IP_AES_AES_K2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K2R_K(value) (1 << value) - - -/***AES Key 1 Register***/ -#define INCA_IP_AES_AES_K1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K1R_K(value) (1 << value) - - -/***AES Key 0 Register***/ -#define INCA_IP_AES_AES_K0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_K0R_K(value) (1 << value) - - -/***AES Initialization Vector 3 Register***/ -#define INCA_IP_AES_AES_IV3R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_IV3R_IV(value) (1 << value) - - -/***AES Initialization Vector 2 Register***/ -#define INCA_IP_AES_AES_IV2R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_IV2R_IV(value) (1 << value) - - -/***AES Initialization Vector 1 Register***/ -#define INCA_IP_AES_AES_IV1R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_IV1R_IV(value) (1 << value) - - -/***AES Initialization Vector 0 Register***/ -#define INCA_IP_AES_AES_IV0R ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_IV0R_IV (value) (((( 1 << 32) - 1) &(value)) << 0) - -/***AES Control Register***/ -#define INCA_IP_AES_AES_CONTROLR ((volatile u32*)(INCA_IP_AES+ 0x0000)) -#define INCA_IP_AES_AES_CONTROLR_KRE (1 << 31) -#define INCA_IP_AES_AES_CONTROLR_DAU (1 << 16) -#define INCA_IP_AES_AES_CONTROLR_PNK (1 << 15) -#define INCA_IP_AES_AES_CONTROLR_F(value) (1 << value) - -#define INCA_IP_AES_AES_CONTROLR_O(value) (1 << value) - -#define INCA_IP_AES_AES_CONTROLR_GO (1 << 8) -#define INCA_IP_AES_AES_CONTROLR_STP (1 << 7) -#define INCA_IP_AES_AES_CONTROLR_IEN (1 << 6) -#define INCA_IP_AES_AES_CONTROLR_BUS (1 << 5) -#define INCA_IP_AES_AES_CONTROLR_SM (1 << 4) -#define INCA_IP_AES_AES_CONTROLR_E_D (1 << 3) -#define INCA_IP_AES_AES_CONTROLR_KV (1 << 2) -#define INCA_IP_AES_AES_CONTROLR_K(value) (1 << value) - - -/***********************************************************************/ -/* Module : I²C register address and bits */ -/***********************************************************************/ - -#define INCA_IP_IIC (0xB8000700) -/***********************************************************************/ - - -/***I²C Port Input Select Register***/ -#define INCA_IP_IIC_IIC_PISEL ((volatile u32*)(INCA_IP_IIC+ 0x0004)) -#define INCA_IP_IIC_IIC_PISEL_SDAIS(value) (1 << value) - -#define INCA_IP_IIC_IIC_PISEL_SCLIS(value) (1 << value) - - -/***I²C Clock Control Register***/ -#define INCA_IP_IIC_IIC_CLC ((volatile u32*)(INCA_IP_IIC+ 0x0000)) -#define INCA_IP_IIC_IIC_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_IIC_IIC_CLC_DISS (1 << 1) -#define INCA_IP_IIC_IIC_CLC_DISR (1 << 0) - -/***I²C System Control Register***/ -#define INCA_IP_IIC_IIC_SYSCON_0 ((volatile u32*)(INCA_IP_IIC+ 0x0010)) -#define INCA_IP_IIC_IIC_SYSCON_0_WMEN (1 << 31) -#define INCA_IP_IIC_IIC_SYSCON_0_CI (value) (((( 1 << 2) - 1) & (value)) << 26) -#define INCA_IP_IIC_IIC_SYSCON_0_STP (1 << 25) -#define INCA_IP_IIC_IIC_SYSCON_0_IGE (1 << 24) -#define INCA_IP_IIC_IIC_SYSCON_0_TRX (1 << 23) -#define INCA_IP_IIC_IIC_SYSCON_0_INT (1 << 22) -#define INCA_IP_IIC_IIC_SYSCON_0_ACKDIS (1 << 21) -#define INCA_IP_IIC_IIC_SYSCON_0_BUM (1 << 20) -#define INCA_IP_IIC_IIC_SYSCON_0_MOD (value) (((( 1 << 2) - 1) & (value)) << 18) -#define INCA_IP_IIC_IIC_SYSCON_0_RSC (1 << 17) -#define INCA_IP_IIC_IIC_SYSCON_0_M10 (1 << 16) -#define INCA_IP_IIC_IIC_SYSCON_0_RMEN (1 << 15) -#define INCA_IP_IIC_IIC_SYSCON_0_CO (value) (((( 1 << 3) - 1) & (value)) << 8) -#define INCA_IP_IIC_IIC_SYSCON_0_IRQE (1 << 7) -#define INCA_IP_IIC_IIC_SYSCON_0_IRQP (1 << 6) -#define INCA_IP_IIC_IIC_SYSCON_0_IRQD (1 << 5) -#define INCA_IP_IIC_IIC_SYSCON_0_BB (1 << 4) -#define INCA_IP_IIC_IIC_SYSCON_0_LRB (1 << 3) -#define INCA_IP_IIC_IIC_SYSCON_0_SLA (1 << 2) -#define INCA_IP_IIC_IIC_SYSCON_0_AL (1 << 1) -#define INCA_IP_IIC_IIC_SYSCON_0_ADR (1 << 0) - -/***I²C System Control Register***/ -#define INCA_IP_IIC_IIC_SYSCON_1 ((volatile u32*)(INCA_IP_IIC+ 0x0010)) -#define INCA_IP_IIC_IIC_SYSCON_1_RM (value) (((( 1 << 8) - 1) & (value)) << 24) -#define INCA_IP_IIC_IIC_SYSCON_1_TRX (1 << 23) -#define INCA_IP_IIC_IIC_SYSCON_1_INT (1 << 22) -#define INCA_IP_IIC_IIC_SYSCON_1_ACKDIS (1 << 21) -#define INCA_IP_IIC_IIC_SYSCON_1_BUM (1 << 20) -#define INCA_IP_IIC_IIC_SYSCON_1_MOD (value) (((( 1 << 2) - 1) & (value)) << 18) -#define INCA_IP_IIC_IIC_SYSCON_1_RSC (1 << 17) -#define INCA_IP_IIC_IIC_SYSCON_1_M10 (1 << 16) -#define INCA_IP_IIC_IIC_SYSCON_1_RMEN (1 << 15) -#define INCA_IP_IIC_IIC_SYSCON_1_CO (value) (((( 1 << 3) - 1) & (value)) << 8) -#define INCA_IP_IIC_IIC_SYSCON_1_IRQE (1 << 7) -#define INCA_IP_IIC_IIC_SYSCON_1_IRQP (1 << 6) -#define INCA_IP_IIC_IIC_SYSCON_1_IRQD (1 << 5) -#define INCA_IP_IIC_IIC_SYSCON_1_BB (1 << 4) -#define INCA_IP_IIC_IIC_SYSCON_1_LRB (1 << 3) -#define INCA_IP_IIC_IIC_SYSCON_1_SLA (1 << 2) -#define INCA_IP_IIC_IIC_SYSCON_1_AL (1 << 1) -#define INCA_IP_IIC_IIC_SYSCON_1_ADR (1 << 0) - -/***I²C System Control Register***/ -#define INCA_IP_IIC_IIC_SYSCON_2 ((volatile u32*)(INCA_IP_IIC+ 0x0010)) -#define INCA_IP_IIC_IIC_SYSCON_2_WMEN (1 << 31) -#define INCA_IP_IIC_IIC_SYSCON_2_CI (value) (((( 1 << 2) - 1) & (value)) << 26) -#define INCA_IP_IIC_IIC_SYSCON_2_STP (1 << 25) -#define INCA_IP_IIC_IIC_SYSCON_2_IGE (1 << 24) -#define INCA_IP_IIC_IIC_SYSCON_2_TRX (1 << 23) -#define INCA_IP_IIC_IIC_SYSCON_2_INT (1 << 22) -#define INCA_IP_IIC_IIC_SYSCON_2_ACKDIS (1 << 21) -#define INCA_IP_IIC_IIC_SYSCON_2_BUM (1 << 20) -#define INCA_IP_IIC_IIC_SYSCON_2_MOD (value) (((( 1 << 2) - 1) & (value)) << 18) -#define INCA_IP_IIC_IIC_SYSCON_2_RSC (1 << 17) -#define INCA_IP_IIC_IIC_SYSCON_2_M10 (1 << 16) -#define INCA_IP_IIC_IIC_SYSCON_2_WM (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_IIC_IIC_SYSCON_2_IRQE (1 << 7) -#define INCA_IP_IIC_IIC_SYSCON_2_IRQP (1 << 6) -#define INCA_IP_IIC_IIC_SYSCON_2_IRQD (1 << 5) -#define INCA_IP_IIC_IIC_SYSCON_2_BB (1 << 4) -#define INCA_IP_IIC_IIC_SYSCON_2_LRB (1 << 3) -#define INCA_IP_IIC_IIC_SYSCON_2_SLA (1 << 2) -#define INCA_IP_IIC_IIC_SYSCON_2_AL (1 << 1) -#define INCA_IP_IIC_IIC_SYSCON_2_ADR (1 << 0) - -/***I²C Write Hardware Modified System Control Register -***/ -#define INCA_IP_IIC_IIC_WHBSYSCON ((volatile u32*)(INCA_IP_IIC+ 0x0020)) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRWMEN (1 << 31) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETWMEN (1 << 30) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETSTP (1 << 26) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRSTP (1 << 25) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETTRX (1 << 24) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRTRX (1 << 23) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETACKDIS (1 << 22) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRACKDIS (1 << 21) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETBUM (1 << 20) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRBUM (1 << 19) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETRSC (1 << 17) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRRSC (1 << 16) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETRMEN (1 << 15) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRRMEN (1 << 14) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQE (1 << 10) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQP (1 << 9) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETIRQD (1 << 8) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQE (1 << 7) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQP (1 << 6) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRIRQD (1 << 5) -#define INCA_IP_IIC_IIC_WHBSYSCON_SETAL (1 << 2) -#define INCA_IP_IIC_IIC_WHBSYSCON_CLRAL (1 << 1) - -/***I²C Bus Control Register***/ -#define INCA_IP_IIC_IIC_BUSCON_0 ((volatile u32*)(INCA_IP_IIC+ 0x0014)) -#define INCA_IP_IIC_IIC_BUSCON_0_BRPMOD (1 << 31) -#define INCA_IP_IIC_IIC_BUSCON_0_PREDIV (value) (((( 1 << 2) - 1) & (value)) << 29) -#define INCA_IP_IIC_IIC_BUSCON_0_ICA9_0 (value) (((( 1 << 10) - 1) & (value)) << 16) -#define INCA_IP_IIC_IIC_BUSCON_0_BRP (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_IIC_IIC_BUSCON_0_SCLEN(value) (1 << value) - -#define INCA_IP_IIC_IIC_BUSCON_0_SDAEN(value) (1 << value) - - -/***I²C Bus Control Register***/ -#define INCA_IP_IIC_IIC_BUSCON_1 ((volatile u32*)(INCA_IP_IIC+ 0x0014)) -#define INCA_IP_IIC_IIC_BUSCON_1_BRPMOD (1 << 31) -#define INCA_IP_IIC_IIC_BUSCON_1_PREDIV (value) (((( 1 << 2) - 1) & (value)) << 29) -#define INCA_IP_IIC_IIC_BUSCON_1_ICA7_1 (value) (((( 1 << 7) - 1) & (value)) << 17) -#define INCA_IP_IIC_IIC_BUSCON_1_BRP (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_IIC_IIC_BUSCON_1_SCLEN(value) (1 << value) - -#define INCA_IP_IIC_IIC_BUSCON_1_SDAEN(value) (1 << value) - - -/***I²C Receive Transmit Buffer***/ -#define INCA_IP_IIC_IIC_RTB ((volatile u32*)(INCA_IP_IIC+ 0x0018)) -#define INCA_IP_IIC_IIC_RTB_RTB(value) (1 << value) - - -/***********************************************************************/ -/* Module : FB register address and bits */ -/***********************************************************************/ - -#define INCA_IP_FB (0xBF880000) -/***********************************************************************/ - - -/***FB Access Error Cause Register***/ -#define INCA_IP_FB_FB_ERRCAUSE ((volatile u32*)(INCA_IP_FB+ 0x0100)) -#define INCA_IP_FB_FB_ERRCAUSE_ERR (1 << 31) -#define INCA_IP_FB_FB_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) -#define INCA_IP_FB_FB_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***FB Access Error Address Register***/ -#define INCA_IP_FB_FB_ERRADDR ((volatile u32*)(INCA_IP_FB+ 0x0108)) -#define INCA_IP_FB_FB_ERRADDR_ADDR - -/***FB Configuration Register***/ -#define INCA_IP_FB_FB_CFG ((volatile u32*)(INCA_IP_FB+ 0x0800)) -#define INCA_IP_FB_FB_CFG_SVM (1 << 0) - -/***********************************************************************/ -/* Module : SRAM register address and bits */ -/***********************************************************************/ - -#define INCA_IP_SRAM (0xBF980000) -/***********************************************************************/ - - -/***SRAM Size Register***/ -#define INCA_IP_SRAM_SRAM_SIZE ((volatile u32*)(INCA_IP_SRAM+ 0x0800)) -#define INCA_IP_SRAM_SRAM_SIZE_SIZE (value) (((( 1 << 23) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : BIU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_BIU (0xBFA80000) -/***********************************************************************/ - - -/***BIU Identification Register***/ -#define INCA_IP_BIU_BIU_ID ((volatile u32*)(INCA_IP_BIU+ 0x0000)) -#define INCA_IP_BIU_BIU_ID_ARCH (1 << 16) -#define INCA_IP_BIU_BIU_ID_ID (value) (((( 1 << 8) - 1) & (value)) << 8) -#define INCA_IP_BIU_BIU_ID_REV (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***BIU Access Error Cause Register***/ -#define INCA_IP_BIU_BIU_ERRCAUSE ((volatile u32*)(INCA_IP_BIU+ 0x0100)) -#define INCA_IP_BIU_BIU_ERRCAUSE_ERR (1 << 31) -#define INCA_IP_BIU_BIU_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) -#define INCA_IP_BIU_BIU_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***BIU Access Error Address Register***/ -#define INCA_IP_BIU_BIU_ERRADDR ((volatile u32*)(INCA_IP_BIU+ 0x0108)) -#define INCA_IP_BIU_BIU_ERRADDR_ADDR - -/***********************************************************************/ -/* Module : ICU register address and bits */ -/***********************************************************************/ - -#define INCA_IP_ICU (0xBF101000) -/***********************************************************************/ - - -/***IM0 Interrupt Status Register***/ -#define INCA_IP_ICU_IM0_ISR ((volatile u32*)(INCA_IP_ICU+ 0x0000)) -#define INCA_IP_ICU_IM0_ISR_IR(value) (1 << value) - - -/***IM1 Interrupt Status Register***/ -#define INCA_IP_ICU_IM1_ISR ((volatile u32*)(INCA_IP_ICU+ 0x0200)) -#define INCA_IP_ICU_IM1_ISR_IR(value) (1 << value) - - -/***IM2 Interrupt Status Register***/ -#define INCA_IP_ICU_IM2_ISR ((volatile u32*)(INCA_IP_ICU+ 0x0400)) -#define INCA_IP_ICU_IM2_ISR_IR(value) (1 << value) - - -/***IM0 Interrupt Enable Register***/ -#define INCA_IP_ICU_IM0_IER ((volatile u32*)(INCA_IP_ICU+ 0x0008)) -#define INCA_IP_ICU_IM0_IER_IR(value) (1 << value) - - -/***IM1 Interrupt Enable Register***/ -#define INCA_IP_ICU_IM1_IER ((volatile u32*)(INCA_IP_ICU+ 0x0208)) -#define INCA_IP_ICU_IM1_IER_IR(value) (1 << value) - - -/***IM2 Interrupt Enable Register***/ -#define INCA_IP_ICU_IM2_IER ((volatile u32*)(INCA_IP_ICU+ 0x0408)) -#define INCA_IP_ICU_IM2_IER_IR(value) (1 << value) - - -/***IM0 Interrupt Output Status Register***/ -#define INCA_IP_ICU_IM0_IOSR ((volatile u32*)(INCA_IP_ICU+ 0x0010)) -#define INCA_IP_ICU_IM0_IOSR_IR(value) (1 << value) - - -/***IM1 Interrupt Output Status Register***/ -#define INCA_IP_ICU_IM1_IOSR ((volatile u32*)(INCA_IP_ICU+ 0x0210)) -#define INCA_IP_ICU_IM1_IOSR_IR(value) (1 << value) - - -/***IM2 Interrupt Output Status Register***/ -#define INCA_IP_ICU_IM2_IOSR ((volatile u32*)(INCA_IP_ICU+ 0x0410)) -#define INCA_IP_ICU_IM2_IOSR_IR(value) (1 << value) - - -/***IM0 Interrupt Request Set Register***/ -#define INCA_IP_ICU_IM0_IRSR ((volatile u32*)(INCA_IP_ICU+ 0x0018)) -#define INCA_IP_ICU_IM0_IRSR_IR(value) (1 << value) - - -/***IM1 Interrupt Request Set Register***/ -#define INCA_IP_ICU_IM1_IRSR ((volatile u32*)(INCA_IP_ICU+ 0x0218)) -#define INCA_IP_ICU_IM1_IRSR_IR(value) (1 << value) - - -/***IM2 Interrupt Request Set Register***/ -#define INCA_IP_ICU_IM2_IRSR ((volatile u32*)(INCA_IP_ICU+ 0x0418)) -#define INCA_IP_ICU_IM2_IRSR_IR(value) (1 << value) - - -/***External Interrupt Control Register***/ -#define INCA_IP_ICU_ICU_EICR ((volatile u32*)(INCA_IP_ICU+ 0x0B00)) -#define INCA_IP_ICU_ICU_EICR_EII5 (value) (((( 1 << 3) - 1) & (value)) << 20) -#define INCA_IP_ICU_ICU_EICR_EII4 (value) (((( 1 << 3) - 1) & (value)) << 16) -#define INCA_IP_ICU_ICU_EICR_EII3 (value) (((( 1 << 3) - 1) & (value)) << 12) -#define INCA_IP_ICU_ICU_EICR_EII2 (value) (((( 1 << 3) - 1) & (value)) << 8) -#define INCA_IP_ICU_ICU_EICR_EII1 (value) (((( 1 << 3) - 1) & (value)) << 4) -#define INCA_IP_ICU_ICU_EICR_EII0 (value) (((( 1 << 3) - 1) & (value)) << 0) diff --git a/arch/mips/include/asm/u-boot-mips.h b/arch/mips/include/asm/u-boot-mips.h index 9f3cce9a62..a5b2fc08f8 100644 --- a/arch/mips/include/asm/u-boot-mips.h +++ b/arch/mips/include/asm/u-boot-mips.h @@ -21,5 +21,3 @@ static inline unsigned long image_copy_end(void) extern char __image_copy_end[]; return (unsigned long) &__image_copy_end; } - -extern int incaip_set_cpuclk(void); diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c index 317c8258de..3200d87e30 100644 --- a/arch/mips/lib/board.c +++ b/arch/mips/lib/board.c @@ -103,9 +103,6 @@ init_fnc_t *init_sequence[] = { board_early_init_f, timer_init, env_init, /* initialize environment */ -#ifdef CONFIG_INCA_IP - incaip_set_cpuclk, /* set cpu clock according to env. variable */ -#endif init_baudrate, /* initialize baudrate settings */ serial_init, /* serial communications setup */ console_init_f, -- cgit From 46a346834b1857ded410f44e59da93a8793f19fc Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Fri, 11 Apr 2014 17:09:42 +0200 Subject: PPC: 85xx: Remove IVOR reset There is no need to set IVORs to anything but their default values, so let's leave them where they are. Suggested-by: Scott Wood Signed-off-by: Alexander Graf Acked-by: Scott Wood [York Sun: Add back $(obj)start.S section in mpc8572ds/Makefile] Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 4 --- arch/powerpc/cpu/mpc85xx/fixed_ivor.S | 63 ----------------------------------- arch/powerpc/cpu/mpc85xx/release.S | 3 -- arch/powerpc/cpu/mpc85xx/start.S | 6 ---- 4 files changed, 76 deletions(-) delete mode 100644 arch/powerpc/cpu/mpc85xx/fixed_ivor.S (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 81aeadd363..18366a744e 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -767,8 +767,6 @@ skip_l2: return 0; } -extern void setup_ivors(void); - void arch_preboot_os(void) { u32 msr; @@ -781,8 +779,6 @@ void arch_preboot_os(void) msr = mfmsr(); msr &= ~(MSR_ME|MSR_CE); mtmsr(msr); - - setup_ivors(); } #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) diff --git a/arch/powerpc/cpu/mpc85xx/fixed_ivor.S b/arch/powerpc/cpu/mpc85xx/fixed_ivor.S deleted file mode 100644 index ebbb8c0744..0000000000 --- a/arch/powerpc/cpu/mpc85xx/fixed_ivor.S +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * Kumar Gala - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* This file is intended to be included by other asm code since - * we will want to execute this on both the primary core when - * it does a bootm and the secondary core's that get released - * out of the spin table */ - -#define SET_IVOR(vector_number, vector_offset) \ - li r3,vector_offset@l; \ - mtspr SPRN_IVOR##vector_number,r3; - -#define SET_GIVOR(vector_number, vector_offset) \ - li r3,vector_offset@l; \ - mtspr SPRN_GIVOR##vector_number,r3; - - SET_IVOR(0, 0x020) /* Critical Input */ - SET_IVOR(1, 0x000) /* Machine Check */ - SET_IVOR(2, 0x060) /* Data Storage */ - SET_IVOR(3, 0x080) /* Instruction Storage */ - SET_IVOR(4, 0x0a0) /* External Input */ - SET_IVOR(5, 0x0c0) /* Alignment */ - SET_IVOR(6, 0x0e0) /* Program */ - SET_IVOR(7, 0x100) /* FP Unavailable */ - SET_IVOR(8, 0x120) /* System Call */ - SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */ - SET_IVOR(10, 0x160) /* Decrementer */ - SET_IVOR(11, 0x180) /* Fixed Interval Timer */ - SET_IVOR(12, 0x1a0) /* Watchdog Timer */ - SET_IVOR(13, 0x1c0) /* Data TLB Error */ - SET_IVOR(14, 0x1e0) /* Instruction TLB Error */ - SET_IVOR(15, 0x040) /* Debug */ - -/* e500v1 & e500v2 only */ -#ifndef CONFIG_E500MC - SET_IVOR(32, 0x200) /* SPE Unavailable */ - SET_IVOR(33, 0x220) /* Embedded FP Data */ - SET_IVOR(34, 0x240) /* Embedded FP Round */ -#endif - - SET_IVOR(35, 0x260) /* Performance monitor */ - -/* e500mc only */ -#ifdef CONFIG_E500MC - SET_IVOR(36, 0x280) /* Processor doorbell */ - SET_IVOR(37, 0x2a0) /* Processor doorbell critical */ - SET_IVOR(38, 0x2c0) /* Guest Processor doorbell */ - SET_IVOR(39, 0x2e0) /* Guest Processor critical & machine check */ - SET_IVOR(40, 0x300) /* Hypervisor system call */ - SET_IVOR(41, 0x320) /* Hypervisor Priviledge */ - - SET_GIVOR(2, 0x060) /* Guest Data Storage */ - SET_GIVOR(3, 0x080) /* Guest Instruction Storage */ - SET_GIVOR(4, 0x0a0) /* Guest External Input */ - SET_GIVOR(8, 0x120) /* Guest System Call */ - SET_GIVOR(13, 0x1c0) /* Guest Data TLB Error */ - SET_GIVOR(14, 0x1e0) /* Guest Instruction TLB Error */ -#endif diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index fcfba7ec19..a2c0ad4244 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -405,9 +405,6 @@ __second_half_boot_page: bne 3b isync - /* setup IVORs to match fixed offsets */ -#include "fixed_ivor.S" - /* get the upper bits of the addr */ lwz r11,ENTRY_ADDR_UPPER(r10) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index dbbd8e588c..691bd3a445 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1965,10 +1965,4 @@ flush_dcache: isync blr - -.globl setup_ivors -setup_ivors: - -#include "fixed_ivor.S" - blr #endif /* !MINIMAL_SPL */ -- cgit From f29f804a93e87c17670607641d120f431a3b0633 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Fri, 11 Apr 2014 17:09:43 +0200 Subject: PPC: 85xx: Generalize DDR TLB mapping function The DDR mapping function really is just a generic virtual -> physical mapping function. Generalize it so it can support any virtual starting offset and IO maps just the same. Signed-off-by: Alexander Graf Acked-by: Scott Wood Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/tlb.c | 47 ++++++++++++++++++++++++++++-------------- arch/powerpc/include/asm/mmu.h | 8 +++++++ 2 files changed, 40 insertions(+), 15 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 8748ecd144..fed8df938e 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -236,20 +236,26 @@ void init_addr_map(void) } #endif -unsigned int -setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) +uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size, + enum tlb_map_type map_type) { int i; unsigned int tlb_size; - unsigned int wimge = MAS2_M; - unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; + unsigned int wimge; + unsigned int perm; unsigned int max_cam, tsize_mask; - u64 size, memsize = (u64)memsize_in_meg << 20; + if (map_type == TLB_MAP_RAM) { + perm = MAS3_SX|MAS3_SW|MAS3_SR; + wimge = MAS2_M; #ifdef CONFIG_SYS_PPC_DDR_WIMGE - wimge = CONFIG_SYS_PPC_DDR_WIMGE; + wimge = CONFIG_SYS_PPC_DDR_WIMGE; #endif - size = min(memsize, CONFIG_MAX_MEM_MAPPED); + } else { + perm = MAS3_SW|MAS3_SR; + wimge = MAS2_I|MAS2_G; + } + if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) { /* Convert (4^max) kB to (2^max) bytes */ max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10; @@ -261,11 +267,11 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) } for (i = 0; size && i < 8; i++) { - int ram_tlb_index = find_free_tlbcam(); + int tlb_index = find_free_tlbcam(); u32 camsize = __ilog2_u64(size) & tsize_mask; - u32 align = __ilog2(ram_tlb_address) & tsize_mask; + u32 align = __ilog2(v_addr) & tsize_mask; - if (ram_tlb_index == -1) + if (tlb_index == -1) break; if (align == -2) align = max_cam; @@ -277,18 +283,29 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) tlb_size = camsize - 10; - set_tlb(1, ram_tlb_address, p_addr, - MAS3_SX|MAS3_SW|MAS3_SR, wimge, - 0, ram_tlb_index, tlb_size, 1); + set_tlb(1, v_addr, p_addr, perm, wimge, + 0, tlb_index, tlb_size, 1); size -= 1ULL << camsize; - memsize -= 1ULL << camsize; - ram_tlb_address += 1UL << camsize; + v_addr += 1UL << camsize; p_addr += 1UL << camsize; } + return size; +} + +unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr, + unsigned int memsize_in_meg) +{ + unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; + u64 memsize = (u64)memsize_in_meg << 20; + + memsize = min(memsize, CONFIG_MAX_MEM_MAPPED); + memsize = tlb_map_range(ram_tlb_address, p_addr, memsize, TLB_MAP_RAM); + if (memsize) print_size(memsize, " left unmapped\n"); + return memsize_in_meg; } diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index cadaeef85a..5aa916f2e2 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h @@ -509,6 +509,14 @@ extern void print_tlbcam(void); extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); extern void clear_ddr_tlbs(unsigned int memsize_in_meg); +enum tlb_map_type { + TLB_MAP_RAM, + TLB_MAP_IO, +}; + +extern uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size, + enum tlb_map_type map_type); + extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7); #define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \ -- cgit From fd96ea4dd9a22ee380f1c59939a42744aa196ad0 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Fri, 11 Apr 2014 17:09:44 +0200 Subject: PPC 85xx: Add ELF entry point We want to be able to directly execute the ELF binary without going through the u-boot.bin one. To know where we have to start executing this ELF binary we have to tell the linker where our entry point is. Signed-off-by: Alexander Graf Acked-by: Scott Wood Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/u-boot.lds | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 2af4c80f60..b34d2125f7 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -13,6 +13,7 @@ #endif OUTPUT_ARCH(powerpc) +ENTRY(_start_e500) PHDRS { -- cgit From fa08d39517773882b07965ca4330777c6d6697ae Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Fri, 11 Apr 2014 17:09:45 +0200 Subject: PPC 85xx: Add qemu-ppce500 machine For KVM we have a special PV machine type called "ppce500". This machine is inspired by the MPC8544DS board, but implements a lot less features than that one. It also provides more PCI slots and is supposed to be enumerated by device tree only. This patch adds support for the generic ppce500 machine and tries to rely solely on device tree for device enumeration. Signed-off-by: Alexander Graf Acked-by: Scott Wood Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/Makefile | 2 ++ arch/powerpc/cpu/mpc85xx/cpu.c | 5 +++-- arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 8 +++++++- arch/powerpc/cpu/mpc85xx/start.S | 11 +++++++++++ arch/powerpc/cpu/mpc85xx/tlb.c | 2 +- arch/powerpc/include/asm/config_mpc85xx.h | 4 ++++ 6 files changed, 28 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index ef7637a49c..409478539e 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -102,7 +102,9 @@ obj-y += cpu.o obj-y += cpu_init.o obj-y += cpu_init_early.o obj-y += interrupts.o +ifneq ($(CONFIG_QEMU_E500),y) obj-y += speed.o +endif obj-y += tlb.o obj-y += traps.o diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 3e99b079c7..2c8126c5f1 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -272,7 +272,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifndef CONFIG_SYS_FSL_TBCLK_DIV #define CONFIG_SYS_FSL_TBCLK_DIV 8 #endif -unsigned long get_tbclk (void) +__weak unsigned long get_tbclk (void) { unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV; @@ -338,7 +338,8 @@ void mpc85xx_reginfo(void) !defined(CONFIG_SYS_INIT_L2_ADDR) phys_size_t initdram(int board_type) { -#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) +#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \ + defined(CONFIG_QEMU_E500) return fsl_ddr_sdram_size(); #else return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 993b8b828b..998781b706 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -79,7 +79,7 @@ void setup_ifc(void) #endif /* We run cpu_init_early_f in AS = 1 */ -void cpu_init_early_f(void) +void cpu_init_early_f(void *fdt) { u32 mas0, mas1, mas2, mas3, mas7; int i; @@ -102,6 +102,12 @@ void cpu_init_early_f(void) for (i = 0; i < sizeof(gd_t); i++) ((char *)gd)[i] = 0; + /* + * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems, + * so we need to populate it before it accesses it. + */ + gd->fdt_blob = fdt; + mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13); mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M); mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G); diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 691bd3a445..6b0380f9f5 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -78,6 +78,13 @@ _start_e500: li r1,MSR_DE mtmsr r1 + /* + * If we got an ePAPR device tree pointer passed in as r3, we need that + * later in cpu_init_early_f(). Save it to a safe register before we + * clobber it so that we can fetch it from there later. + */ + mr r24, r3 + #ifdef CONFIG_SYS_FSL_ERRATUM_A004510 mfspr r3,SPRN_SVR rlwinm r3,r3,0,0xff @@ -1142,6 +1149,10 @@ _start_cont: mr r1,r3 /* Transfer to SP(r1) */ GET_GOT + + /* Pass our potential ePAPR device tree pointer to cpu_init_early_f */ + mr r3, r24 + bl cpu_init_early_f /* switch back to AS = 0 */ diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index fed8df938e..129ec662fe 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -24,7 +24,7 @@ void invalidate_tlb(u8 tlb) mtspr(MMUCSR0, 0x2); } -void init_tlbs(void) +__weak void init_tlbs(void) { int i; diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index df44451091..e376783963 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -797,6 +797,10 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_A005125 +#elif defined(CONFIG_QEMU_E500) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000 + #else #error Processor type not defined for this platform #endif -- cgit From 7efb4b51975409fb922e9f9bfec21a7affb6f83f Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Tue, 11 Mar 2014 23:21:45 +0530 Subject: powerpc/mpc8xxx: SECURE BOOT- Disable law 0 for non PBL platforms ISBC creates a LAW 0 entry for non PBL platforms, which is not disabled before transferring the control to uboot. The LAW 0 entry has to be disabled. Signed-off-by: Aneesh Bansal Reviewed-by: York Sun --- arch/powerpc/cpu/mpc8xxx/law.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index a401083107..55ee12573f 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -233,6 +233,16 @@ void init_laws(void) #error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes #endif +#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500) && \ + !defined(CONFIG_E500MC) + /* ISBC (Boot ROM) creates a LAW 0 entry for non PBL platforms, + * which is not disabled before transferring the control to uboot. + * Disable the LAW 0 entry here. + */ + disable_law(0); +#endif + + /* * Any LAWs that were set up before we booted assume they are meant to * be around and mark them used. -- cgit From f978f7c203a6ea8a9bdc101a12486d6903fd8162 Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Wed, 12 Mar 2014 00:07:27 +0530 Subject: powerpc/mpc85xx: SECURE BOOT- Add secure boot target for BSC9132QDS Add NOR, SPI and SD secure boot targets for BSC9132QDS. Changes: - Debug TLB entry is not required for Secure Boot Target. Signed-off-by: Aneesh Bansal Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/start.S | 9 ++------- arch/powerpc/include/asm/fsl_secure_boot.h | 2 ++ 2 files changed, 4 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 6b0380f9f5..9eee549f87 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -467,7 +467,8 @@ nexti: mflr r1 /* R1 = our PC */ 2: cmpw r3, r4 blt 1b -#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) +#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) && \ + !defined(CONFIG_SECURE_BOOT) /* * TLB entry for debuggging in AS1 * Create temporary TLB entry in AS0 to handle debug exception @@ -488,12 +489,6 @@ nexti: mflr r1 /* R1 = our PC */ 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6 -#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) - create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ - 0, BOOKE_PAGESZ_1M, \ - CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \ - CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \ - 0, r6 #else /* * TLB entry is created for IVPR + IVOR15 to map on valid OP code address diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 4c7f0b1cae..3dce1d2bac 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -10,6 +10,8 @@ #ifdef CONFIG_SECURE_BOOT #if defined(CONFIG_FSL_CORENET) #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 +#elif defined(CONFIG_BSC9132QDS) +#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000 #else #define CONFIG_SYS_PBI_FLASH_BASE 0xce000000 #endif -- cgit From fb4a2409b46c98672557bb07dec8e873bef1e23c Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Tue, 18 Mar 2014 23:40:26 +0530 Subject: powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS Changes: 1. L2 cache is being invalidated by Boot ROM code for e6500 core. So removing the invalidation from start.S 2. Clear the LAW and corresponding configuration for CPC. Boot ROM code uses it as hosekeeping area. 3. For Secure boot, CPC is configured as SRAM and used as house keeping area. This configuration is to be disabled once in uboot. Earlier this disabling of CPC as SRAM was happening in cpu_init_r. As a result cache invalidation function was getting skipped in case CPC is configured as SRAM.This was causing random crashes. Signed-off-by: Ruchika Gupta Signed-off-by: Aneesh Bansal Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 27 ++++++++++++++++++++++----- arch/powerpc/cpu/mpc85xx/start.S | 3 ++- arch/powerpc/include/asm/fsl_secure_boot.h | 6 ++++++ 3 files changed, 30 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 18366a744e..19df95fee2 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -173,17 +173,14 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) #endif #ifdef CONFIG_SYS_FSL_CPC -static void enable_cpc(void) +#if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F) +static void disable_cpc_sram(void) { int i; - u32 size = 0; cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { - u32 cpccfg0 = in_be32(&cpc->cpccfg0); - size += CPC_CFG0_SZ_K(cpccfg0); -#ifdef CONFIG_RAMBOOT_PBL if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { /* find and disable LAW of SRAM */ struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); @@ -198,8 +195,21 @@ static void enable_cpc(void) out_be32(&cpc->cpccsr0, 0); out_be32(&cpc->cpcsrcr0, 0); } + } +} #endif +static void enable_cpc(void) +{ + int i; + u32 size = 0; + + cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; + + for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + u32 cpccfg0 = in_be32(&cpc->cpccfg0); + size += CPC_CFG0_SZ_K(cpccfg0); + #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); #endif @@ -298,6 +308,10 @@ void cpu_init_f (void) law = find_law(CONFIG_SYS_PBI_FLASH_BASE); if (law.index != -1) disable_law(law.index); + +#if defined(CONFIG_SYS_CPC_REINIT_F) + disable_cpc_sram(); +#endif #endif #ifdef CONFIG_CPM2 @@ -598,6 +612,9 @@ skip_l2: puts("disabled\n"); #endif +#if defined(CONFIG_RAMBOOT_PBL) + disable_cpc_sram(); +#endif enable_cpc(); #ifndef CONFIG_SYS_FSL_NO_SERDES diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 9eee549f87..9a7881f6c0 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -122,7 +122,8 @@ _start_e500: #endif -#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) +#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \ + !defined(CONFIG_E6500) /* ISBC uses L2 as stack. * Disable L2 cache here so that u-boot can enable it later * as part of it's normal flow diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 3dce1d2bac..c705d5a05b 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -17,5 +17,11 @@ #endif #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 +#if defined(CONFIG_B4860QDS) +#define CONFIG_SYS_CPC_REINIT_F +#undef CONFIG_SYS_INIT_L3_ADDR +#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 +#endif + #endif #endif -- cgit From 796a78100166809f7e5515dd8806b2af703714a0 Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Tue, 18 Mar 2014 23:40:42 +0530 Subject: powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T4240QDS and T4160QDS Secure Boot Target is added for T4240QDS and T4160QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T4240QDS. Signed-off-by: Aneesh Bansal Reviewed-by: York Sun --- arch/powerpc/include/asm/fsl_secure_boot.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index c705d5a05b..b4a0f48719 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -17,7 +17,7 @@ #endif #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 -#if defined(CONFIG_B4860QDS) +#if defined(CONFIG_B4860QDS) || defined(CONFIG_T4240QDS) #define CONFIG_SYS_CPC_REINIT_F #undef CONFIG_SYS_INIT_L3_ADDR #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 -- cgit From ca4819df839dbe1b92f82766c1e7180c0496815a Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Tue, 18 Mar 2014 23:40:59 +0530 Subject: powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080QDS Secure Boot Target is added for T2080QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080QDS. Signed-off-by: Aneesh Bansal Reviewed-by: York Sun --- arch/powerpc/include/asm/fsl_secure_boot.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index b4a0f48719..43a719f21a 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -17,7 +17,9 @@ #endif #define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 -#if defined(CONFIG_B4860QDS) || defined(CONFIG_T4240QDS) +#if defined(CONFIG_B4860QDS) || \ + defined(CONFIG_T4240QDS) || \ + defined(CONFIG_T2080QDS) #define CONFIG_SYS_CPC_REINIT_F #undef CONFIG_SYS_INIT_L3_ADDR #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 -- cgit From 2d8db6d3158a8f2da99bde8c8aea3272292b4ae7 Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Tue, 18 Mar 2014 23:41:14 +0530 Subject: powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T1040QDS and T1040RDB Secure Boot Target is added for T1040QDS and T1040RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T1040QDS and CONFIG_T1040RDB Signed-off-by: Gaurav Rana Signed-off-by: Aneesh Bansal Reviewed-by: York Sun --- arch/powerpc/include/asm/fsl_secure_boot.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 43a719f21a..29bef910ed 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -19,7 +19,9 @@ #if defined(CONFIG_B4860QDS) || \ defined(CONFIG_T4240QDS) || \ - defined(CONFIG_T2080QDS) + defined(CONFIG_T2080QDS) || \ + defined(CONFIG_T1040QDS) || \ + defined(CONFIG_T1040RDB) #define CONFIG_SYS_CPC_REINIT_F #undef CONFIG_SYS_INIT_L3_ADDR #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 -- cgit From dcf1d774bf5c2612538658eac01931895b7a805f Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Fri, 21 Mar 2014 16:21:44 +0800 Subject: QE/FMAN: modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and CONFIG_SYS_QE_FW_ADDR CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address. Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address, and CONFIG_SYS_QE_FW_ADDR for QE microcode address. Signed-off-by: Zhao Qiang Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 19df95fee2..0b4d8eaff8 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -818,7 +818,7 @@ void cpu_secondary_init_r(void) /* load QE firmware from NAND flash to DDR first */ ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND, - &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR); + &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR); if (ret && ret == -EUCLEAN) { printf ("NAND read for QE firmware at offset %x failed %d\n", -- cgit From 2a44efeb217f1516052555bb66d7de962862bb51 Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Fri, 21 Mar 2014 16:21:45 +0800 Subject: QE/U-QE: Add U-QE support Modify code to adapt to both u-qe and qe. U_QE is a kind of cutted QE. the differences between U_QE and QE 1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs. 2. IMMR: have different immr base addr. 3. iopin: U_QE doesn't need to config iopin. Signed-off-by: Zhao Qiang Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 16 +++++++++++++--- arch/powerpc/cpu/mpc85xx/qe_io.c | 2 +- arch/powerpc/cpu/mpc85xx/speed.c | 4 ++++ arch/powerpc/cpu/mpc85xx/t1040_ids.c | 1 + arch/powerpc/include/asm/config_mpc85xx.h | 3 +++ arch/powerpc/include/asm/fsl_liodn.h | 4 ++++ arch/powerpc/include/asm/immap_85xx.h | 5 ++++- 7 files changed, 30 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 0b4d8eaff8..0a33e8dbc1 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -33,6 +33,9 @@ #endif #include "../../../../drivers/block/fsl_sata.h" +#ifdef CONFIG_U_QE +#include "../../../../drivers/qe/qe.h" +#endif DECLARE_GLOBAL_DATA_PTR; @@ -84,7 +87,7 @@ void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy) #endif -#ifdef CONFIG_QE +#if defined(CONFIG_QE) && !defined(CONFIG_U_QE) extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign); @@ -323,10 +326,12 @@ void cpu_init_f (void) #if defined(CONFIG_CPM2) m8560_cpm_reset(); #endif -#ifdef CONFIG_QE + +#if defined(CONFIG_QE) && !defined(CONFIG_U_QE) /* Config QE ioports */ config_qe_ioports(); #endif + #if defined(CONFIG_FSL_DMA) dma_init(); #endif @@ -810,8 +815,13 @@ int sata_initialize(void) void cpu_secondary_init_r(void) { -#ifdef CONFIG_QE +#ifdef CONFIG_U_QE + uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */ +#elif defined CONFIG_QE uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ +#endif + +#ifdef CONFIG_QE #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND int ret; size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; diff --git a/arch/powerpc/cpu/mpc85xx/qe_io.c b/arch/powerpc/cpu/mpc85xx/qe_io.c index 76c60da420..d2825ec36e 100644 --- a/arch/powerpc/cpu/mpc85xx/qe_io.c +++ b/arch/powerpc/cpu/mpc85xx/qe_io.c @@ -12,7 +12,7 @@ #include "asm/io.h" #include "asm/immap_85xx.h" -#if defined(CONFIG_QE) +#if defined(CONFIG_QE) && !defined(CONFIG_U_QE) #define NUM_OF_PINS 32 void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) { diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index adf09efa27..488fd5ea76 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -336,6 +336,10 @@ void get_sys_info(sys_info_t *sys_info) #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ +#ifdef CONFIG_U_QE + sys_info->freq_qe = sys_info->freq_systembus / 2; +#endif + #else /* CONFIG_FSL_CORENET */ uint plat_ratio, e500_ratio, half_freq_systembus; int i; diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c b/arch/powerpc/cpu/mpc85xx/t1040_ids.c index 68160a9512..1034cd4852 100644 --- a/arch/powerpc/cpu/mpc85xx/t1040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c @@ -46,6 +46,7 @@ struct liodn_id_table liodn_tbl[] = { SET_DMA_LIODN(2, 227), /* SET_NEXUS_LIODN(557), -- not yet implemented */ + SET_QE_LIODN(559), }; int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index e376783963..39035b68ac 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -736,6 +736,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE +#define QE_MURAM_SIZE 0x6000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define CONFIG_E6500 diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index 44bc88dcec..f658bcbc66 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -99,6 +99,10 @@ extern void fdt_fixup_liodn(void *blob); SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\ CONFIG_SYS_MPC85xx_ESDHC_OFFSET) +#define SET_QE_LIODN(liodn) \ + SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\ + CONFIG_SYS_MPC85xx_QE_OFFSET) + #define SET_QMAN_LIODN(liodn) \ SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \ CONFIG_SYS_FSL_QMAN_OFFSET, \ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 4b6f9d018e..4bda0f1934 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1889,7 +1889,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) u32 sata2liodnr; /* SATA 2 LIODN */ u32 sata3liodnr; /* SATA 3 LIODN */ u32 sata4liodnr; /* SATA 4 LIODN */ - u8 res22[32]; + u8 res22[24]; + u32 qeliodnr; /* QE LIODN */ + u8 res_57c[4]; u32 dma1liodnr; /* DMA 1 LIODN */ u32 dma2liodnr; /* DMA 2 LIODN */ u32 dma3liodnr; /* DMA 3 LIODN */ @@ -2877,6 +2879,7 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 +#define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\ && !defined(CONFIG_PPC_B4420) -- cgit From 8d451a7129ee6820cc126c77f0f0a175a2cb2e8d Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Wed, 26 Mar 2014 20:30:56 -0500 Subject: powerpc/85xx: Fix e6500 L2 cache stash IDs The value written to L2CSR1 didn't match the value written to the device tree. Signed-off-by: Scott Wood Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/fdt.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 33bc900167..31e63f7159 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -275,12 +275,16 @@ static inline void ft_fixup_l2cache(void *blob) u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) /* Only initialize every eighth thread */ - if (reg && !((*reg) % 8)) + if (reg && !((*reg) % 8)) { + fdt_setprop_cell(blob, l2_off, "cache-stash-id", + (*reg / 4) + 32 + 1); + } #else - if (reg) -#endif + if (reg) { fdt_setprop_cell(blob, l2_off, "cache-stash-id", - (*reg * 2) + 32 + 1); + (*reg * 2) + 32 + 1); + } +#endif #endif fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); -- cgit From 34e026f9b1eb3bcffb38e7787c2e6eac0e88ba85 Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 27 Mar 2014 17:54:47 -0700 Subject: driver/ddr/fsl: Add DDR4 support to Freescale DDR driver Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun --- arch/powerpc/include/asm/config_mpc85xx.h | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 39035b68ac..fe68e0e280 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -19,8 +19,8 @@ */ #define CONFIG_PPC_SPINTABLE_COMPATIBLE -#define FSL_DDR_VER_4_7 47 -#define FSL_DDR_VER_5_0 50 +#include +#define CONFIG_SYS_FSL_DDR_BE /* IP endianness */ #define CONFIG_SYS_FSL_IFC_BE @@ -401,6 +401,7 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" @@ -442,6 +443,7 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 @@ -490,6 +492,7 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 @@ -527,6 +530,7 @@ #define CONFIG_SYS_NUM_FM2_DTSEC 5 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 @@ -553,6 +557,7 @@ #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 @@ -571,6 +576,7 @@ #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 @@ -704,6 +710,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ +#ifdef CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_FSL_DDRC_GEN4 +#endif #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) #define CONFIG_MAX_CPUS 4 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) @@ -796,6 +805,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_SEC_COMPAT 6 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_A005125 @@ -820,7 +830,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ - !defined(CONFIG_SYS_FSL_DDRC_GEN3) + !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \ + !defined(CONFIG_SYS_FSL_DDRC_GEN4) #define CONFIG_SYS_FSL_DDRC_GEN3 #endif -- cgit From 11856919f267d00155f571c75dd68ba1bb98729b Mon Sep 17 00:00:00 2001 From: Nikhil Badola Date: Wed, 26 Feb 2014 17:43:15 +0530 Subject: fsl/usb: Workaround for USB erratum-A007075 Put a delay of 5 millisecond after reset so that ULPI phy gets enough time to come out of reset. Erratum A007075 applies to following SOCs and their variants, if any P1010 rev 1.0 B4860 rev 1.0, 2.0 P4080 rev 2.0, 3.0 Signed-off-by: Nikhil Badola Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 ++++ arch/powerpc/include/asm/config_mpc85xx.h | 3 +++ arch/powerpc/include/asm/fsl_errata.h | 16 ++++++++++++++++ 3 files changed, 23 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 8b79c05b1f..ee063fd8e9 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -268,6 +268,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A005125 puts("Work-around for Erratum A005125 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007075 + if (has_erratum_a007075()) + puts("Work-around for Erratum A007075 enabled\n"); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) || (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV)) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index fe68e0e280..502e7ccf25 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -154,6 +154,7 @@ #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_ERRATUM_A007075 #define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 #define CONFIG_ESDHC_HC_BLK_ADDR @@ -478,6 +479,7 @@ #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 #define CONFIG_SYS_FSL_ERRATUM_A005812 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_ERRATUM_A007075 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ @@ -674,6 +676,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A005871 #define CONFIG_SYS_FSL_ERRATUM_A006379 #define CONFIG_SYS_FSL_ERRATUM_A006593 +#define CONFIG_SYS_FSL_ERRATUM_A007075 #define CONFIG_SYS_FSL_ERRATUM_A006475 #define CONFIG_SYS_FSL_ERRATUM_A006384 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h index c9982cc8ec..4eba85cc34 100644 --- a/arch/powerpc/include/asm/fsl_errata.h +++ b/arch/powerpc/include/asm/fsl_errata.h @@ -60,4 +60,20 @@ static inline bool has_erratum_a006261(void) } #endif +static inline bool has_erratum_a007075(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + switch (soc) { + case SVR_B4860: + case SVR_B4420: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_P1010: + return IS_SVR_REV(svr, 1, 0); + case SVR_P4080: + return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0); + } + return false; +} #endif -- cgit From c3678b0937a0543280067fd8e08e6e2d278d90e2 Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 28 Mar 2014 15:07:27 -0700 Subject: powerpc/mpc85xx: Add workaround for erratum A007212 Erratum A007212 for DDR is about a runaway condition for DDR PLL oscilliator. Please refer to erratum document for detail. For this workaround to work, DDR PLL needs to be disabled in RCW. However, u-boot needs to know the expected PLL ratio. We put the ratio in a reserved field RCW[18:23]. U-boot will skip this workaround if DDR PLL ratio is set, or the reserved field is not set. Workaround for erratum A007212 applies to selected versions of B4/T4 SoCs. It is safe to apply the workaround to all versions. It is helpful for upgrading SoC without changing u-boot. In case DDR PLL is disabled by RCW (part of the erratum workaround), we need this u-boot workround to bring up DDR clock. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 19 +++++++++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 69 +++++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/speed.c | 7 ++++ arch/powerpc/include/asm/config_mpc85xx.h | 2 + arch/powerpc/include/asm/immap_85xx.h | 2 + 5 files changed, 99 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index ee063fd8e9..9d8acd0aa1 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -113,6 +113,21 @@ static void check_erratum_a4580(uint32_t svr) } #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 +/* + * This workaround can be implemented in PBI, or by u-boot. + */ +static void check_erratum_a007212(void) +{ + u32 __iomem *plldgdcr = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); + + if (in_be32(plldgdcr) & 0x1fe) { + /* check if PLL ratio is set by workaround */ + puts("Work-around for Erratum A007212 enabled\n"); + } +} +#endif + static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 @@ -281,6 +296,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (has_erratum_a006261()) puts("Work-around for Erratum A006261 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 + check_erratum_a007212(); +#endif + return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 0a33e8dbc1..941c20e00a 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -280,6 +280,71 @@ static void corenet_tb_init(void) } #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 +void fsl_erratum_a007212_workaround(void) +{ + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 ddr_pll_ratio; + u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); + u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28); + u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) + u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40); + u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 3) + u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60); + u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68); +#endif +#endif + /* + * Even this workaround applies to selected version of SoCs, it is + * safe to apply to all versions, with the limitation of odd ratios. + * If RCW has disabled DDR PLL, we have to apply this workaround, + * otherwise DDR will not work. + */ + ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> + FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & + FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; + /* check if RCW sets ratio to 0, required by this workaround */ + if (ddr_pll_ratio != 0) + return; + ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> + FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & + FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; + /* check if reserved bits have the desired ratio */ + if (ddr_pll_ratio == 0) { + printf("Error: Unknown DDR PLL ratio!\n"); + return; + } + ddr_pll_ratio >>= 1; + + setbits_be32(plldadcr1, 0x02000001); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) + setbits_be32(plldadcr2, 0x02000001); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 3) + setbits_be32(plldadcr3, 0x02000001); +#endif +#endif + setbits_be32(dpdovrcr4, 0xe0000000); + out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1)); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) + out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1)); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 3) + out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1)); +#endif +#endif + udelay(100); + clrbits_be32(plldadcr1, 0x02000001); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) + clrbits_be32(plldadcr2, 0x02000001); +#if (CONFIG_NUM_DDR_CONTROLLERS >= 3) + clrbits_be32(plldadcr3, 0x02000001); +#endif +#endif + clrbits_be32(dpdovrcr4, 0xe0000000); +} +#endif + void cpu_init_f (void) { extern void m8560_cpm_reset (void); @@ -349,6 +414,10 @@ void cpu_init_f (void) in_be32(&gur->dcsrcr); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 + fsl_erratum_a007212_workaround(); +#endif + } /* Implement a dummy function for those platforms w/o SERDES */ diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 488fd5ea76..35dfb0a9a9 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -107,6 +107,13 @@ void get_sys_info(sys_info_t *sys_info) mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; +#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 + if (mem_pll_rat == 0) { + mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> + FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & + FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; + } +#endif /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 * it uses 6. diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 502e7ccf25..864e74c0c7 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -679,6 +679,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A007075 #define CONFIG_SYS_FSL_ERRATUM_A006475 #define CONFIG_SYS_FSL_ERRATUM_A006384 +#define CONFIG_SYS_FSL_ERRATUM_A007212 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #ifdef CONFIG_PPC_B4860 @@ -792,6 +793,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY +#define CONFIG_SYS_FSL_ERRATUM_A007212 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_ISBC_VER 2 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 4bda0f1934..1ec30337cb 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1739,6 +1739,8 @@ typedef struct ccsr_gur { #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16 +/* use reserved bits 18~23 as scratch space to host DDR PLL ratio */ +#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000 -- cgit From d616fc58e5ac56e2297761ad2ad530eb7df559f9 Mon Sep 17 00:00:00 2001 From: Codrin Ciubotariu Date: Fri, 28 Mar 2014 18:57:29 +0200 Subject: powerpc/cpu/mpc85xx: Add MAC address for layer 2 switch T1040RDB and T1040QDS boards have an integrated l2 switch. The switch needs a MAC address for Layer 2 protocols (MSTP, LLDP, LACP, etc). Setting a MAC address on l2switchaddr will add a MAC in device-tree, under node l2switch. Signed-off-by: Codrin Ciubotariu Cc: York Sun Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/fdt.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 31e63f7159..0cc21c7f68 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -586,6 +586,33 @@ static void fdt_fixup_usb(void *fdt) #define fdt_fixup_usb(x) #endif +#if defined(CONFIG_PPC_T1040) +static void fdt_fixup_l2_switch(void *blob) +{ + uchar l2swaddr[6]; + int node; + + /* The l2switch node from device-tree has + * compatible string "vitesse-9953" */ + node = fdt_node_offset_by_compatible(blob, -1, "vitesse-9953"); + if (node == -FDT_ERR_NOTFOUND) + /* no l2switch node has been found */ + return; + + /* Get MAC address for the l2switch from "l2switchaddr"*/ + if (!eth_getenv_enetaddr("l2switchaddr", l2swaddr)) { + printf("Warning: MAC address for l2switch not found\n"); + memset(l2swaddr, 0, sizeof(l2swaddr)); + } + + /* Add MAC address to l2switch node */ + fdt_setprop(blob, node, "local-mac-address", l2swaddr, + sizeof(l2swaddr)); +} +#else +#define fdt_fixup_l2_switch(x) +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { int off; @@ -723,6 +750,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) "clock-frequency", gd->bus_clk/2, 1); fdt_fixup_usb(blob); + + fdt_fixup_l2_switch(blob); } /* -- cgit From 5aef4c86f3629b937cee159c3d44c0d0e9762a42 Mon Sep 17 00:00:00 2001 From: Tang Yuantian Date: Wed, 26 Mar 2014 16:08:05 +0800 Subject: mpc85xx: Add support for the supplement configuration unit register The supplement configuration unit (SCFG) provides chip-specific configuration and status registers for the device. It is the chip defined module for extending the device configuration unit (DCFG) module. It provides a set of CCSR registers in addition to those available in the device configuration unit. The base address for this unit is 0x0F_C000. Signed-off-by: Tang Yuantian Reviewed-by: York Sun --- arch/powerpc/include/asm/immap_85xx.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 1ec30337cb..be54920efd 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -3156,4 +3156,26 @@ struct dcsr_dcfg_regs { #define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000 u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */ }; + +#define CONFIG_SYS_MPC85xx_SCFG \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET) +#define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000 +/* The supplement configuration unit register */ +struct ccsr_scfg { + u32 dpslpcr; /* 0x000 Deep Sleep Control register */ + u32 usb1dpslpcsr;/* 0x004 USB1 Deep Sleep Control Status register */ + u32 usb2dpslpcsr;/* 0x008 USB2 Deep Sleep Control Status register */ + u32 fmclkdpslpcr;/* 0x00c FM Clock Deep Sleep Control register */ + u32 res1[4]; + u32 esgmiiselcr;/* 0x020 Ethernet Switch SGMII Select Control reg */ + u32 res2; + u32 pixclkcr; /* 0x028 Pixel Clock Control register */ + u32 res3[245]; + u32 qeioclkcr; /* 0x400 QUICC Engine IO Clock Control register */ + u32 emiiocr; /* 0x404 EMI MDIO Control Register */ + u32 sdhciovselcr;/* 0x408 SDHC IO VSEL Control register */ + u32 qmifrstcr; /* 0x40c QMAN Interface Reset Control register */ + u32 res4[60]; + u32 sparecr[8]; /* 0x500 Spare Control register(0-7) */ +}; #endif /*__IMMAP_85xx__*/ -- cgit From aade20046b7ab5bd9b2afe84ccb31f0adf0c5e1e Mon Sep 17 00:00:00 2001 From: Tang Yuantian Date: Thu, 17 Apr 2014 15:33:46 +0800 Subject: mpc85xx/t104x: Add deep sleep framework support When T104x soc wakes up from deep sleep, control is passed to the primary core that starts executing uboot. After re-initialized some IP blocks, like DDRC, kernel will take responsibility to continue to restore environment it leaves before. Signed-off-by: Tang Yuantian Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 8 ++++++++ arch/powerpc/lib/board.c | 16 ++++++++++++++++ 2 files changed, 24 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 941c20e00a..867abb6cf7 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -350,6 +350,7 @@ void cpu_init_f (void) extern void m8560_cpm_reset (void); #ifdef CONFIG_SYS_DCSRBAR_PHYS ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); #endif #if defined(CONFIG_SECURE_BOOT) struct law_entry law; @@ -414,6 +415,13 @@ void cpu_init_f (void) in_be32(&gur->dcsrcr); #endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS +#ifdef CONFIG_DEEP_SLEEP + /* disable the console if boot from deep sleep */ + if (in_be32(&gur->scrtsr[0]) & (1 << 3)) + gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; +#endif +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 fsl_erratum_a007212_workaround(); #endif diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index f86c6f3e8f..8b03d3aa07 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -343,6 +343,13 @@ void board_init_f(ulong bootflag) #ifdef CONFIG_PRAM ulong reg; #endif +#ifdef CONFIG_DEEP_SLEEP + const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + struct ccsr_scfg *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG; + u32 start_addr; + typedef void (*func_t)(void); + func_t kernel_resume; +#endif /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); @@ -360,6 +367,15 @@ void board_init_f(ulong bootflag) if ((*init_fnc_ptr) () != 0) hang(); +#ifdef CONFIG_DEEP_SLEEP + /* Jump to kernel in deep sleep case */ + if (in_be32(&gur->scrtsr[0]) & (1 << 3)) { + start_addr = in_be32(&scfg->sparecr[1]); + kernel_resume = (func_t)start_addr; + kernel_resume(); + } +#endif + #ifdef CONFIG_POST post_bootmode_init(); post_run(NULL, POST_ROM | post_bootmode_get(NULL)); -- cgit From 169ee57138ece39e126c54901e5c7b71c1321719 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Mon, 21 Apr 2014 10:46:59 +0530 Subject: powerpc/mpc85xx: Remove QE firmware copy from NAND qe_init() does not use data copied from NAND. Thise code is not tested or complied causing compilation error during NAND boot So, remove QE firmware copy from NAND to ddr. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 13 ------------- 1 file changed, 13 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 867abb6cf7..a2b79cc7cc 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -899,19 +899,6 @@ void cpu_secondary_init_r(void) #endif #ifdef CONFIG_QE -#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND - int ret; - size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; - - /* load QE firmware from NAND flash to DDR first */ - ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND, - &fw_length, (u_char *)CONFIG_SYS_QE_FW_ADDR); - - if (ret && ret == -EUCLEAN) { - printf ("NAND read for QE firmware at offset %x failed %d\n", - CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret); - } -#endif qe_init(qe_base); qe_reset(); #endif -- cgit From b26df185c383f91e15ebd07e3b247c15d00b385e Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Tue, 8 Apr 2014 19:12:05 +0530 Subject: powerpc/mpc85xx: Move LAW_EN define outside of config LAW_EN is only defined if CONFIG_SYS_CCSRBAR_DEFAULT is not equal to CONFIG_SYS_CCSRBAR_PHYS. in SPL framework CCSRBAR is not relocated hence both are same. This cause compilation error. So LAW_EN define outside of configs Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/start.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 9a7881f6c0..02f50762c7 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -26,6 +26,8 @@ #undef MSR_KERNEL #define MSR_KERNEL ( MSR_ME ) /* Machine Check */ +#define LAW_EN 0x80000000 + #if defined(CONFIG_NAND_SPL) || \ (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)) #define MINIMAL_SPL @@ -577,7 +579,6 @@ infinite_debug_loop: #ifdef CONFIG_FSL_CORENET #define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) -#define LAW_EN 0x80000000 #define LAW_SIZE_4K 0xb #define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K) #define CCSRAR_C 0x80000000 /* Commit */ -- cgit From 49efe85b35e61fb50b00ca02354dfca0d3c5c46c Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Tue, 8 Apr 2014 19:12:19 +0530 Subject: powerpc/mpc85xx: Avoid hardcoding in SPL linker script SPL linker has fix location of bootpg and reset vector with respect to text base. It is not necessary to have fixed locations. Avoid such hardcoding. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index acaa0939ab..4fad68b40c 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -66,11 +66,16 @@ SECTIONS } :text = 0xffff #else #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ - .bootpg ADDR(.text) + 0x1000 : +#ifndef BOOT_PAGE_OFFSET +#define BOOT_PAGE_OFFSET 0x1000 +#endif + .bootpg ADDR(.text) + BOOT_PAGE_OFFSET : { arch/powerpc/cpu/mpc85xx/start.o (.bootpg) } +#ifndef RESET_VECTOR_OFFSET #define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */ +#endif #elif defined(CONFIG_FSL_ELBC) #define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */ #else -- cgit From 651fcf6019eec1a65d4227082e12bc6ad4576f41 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Tue, 8 Apr 2014 19:12:31 +0530 Subject: powerpc:Add support of SPL non-relocation Current SPL code base has BSS section placed after reset_vector. This means they have to relocate to use the global variables. This put an implicit requirement of having SPL size = Memory/2. To avoid relocation: - Move bss_section within SPL range - Modify relocate_code() Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/start.S | 2 ++ arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 12 ++++++++++++ 2 files changed, 14 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 02f50762c7..0e3c86a0f8 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1652,6 +1652,7 @@ relocate_code: mr r10,r5 /* Save copy of Destination Address */ GET_GOT +#ifndef CONFIG_SPL_SKIP_RELOCATE mr r3,r5 /* Destination Address */ lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */ ori r4,r4,CONFIG_SYS_MONITOR_BASE@l @@ -1742,6 +1743,7 @@ relocate_code: mtlr r0 blr /* NEVER RETURNS! */ +#endif .globl in_ram in_ram: diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index 4fad68b40c..8453f3a3fe 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -57,6 +57,16 @@ SECTIONS . = ALIGN(8); __init_begin = .; __init_end = .; +#ifdef CONFIG_SPL_SKIP_RELOCATE + . = ALIGN(4); + __bss_start = .; + .bss : { + *(.sbss*) + *(.bss*) + } + . = ALIGN(4); + __bss_end = .; +#endif /* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */ #ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC @@ -86,6 +96,7 @@ SECTIONS } = 0xffff #endif +#ifndef CONFIG_SPL_SKIP_RELOCATE /* * Make sure that the bss segment isn't linked at 0x0, otherwise its * address won't be updated during relocation fixups. @@ -100,4 +111,5 @@ SECTIONS } . = ALIGN(4); __bss_end = .; +#endif } -- cgit From 6b3d588efee911db65f9deb319488cfe1499c835 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Tue, 8 Apr 2014 19:12:46 +0530 Subject: powerpc/mpc85xx:Disable non DDR LAWs before init_law Before parsing LAW table i.e. init_law, boot loader should disable all previous LAWs except DDR LAWs which has been created by previous pre boot loader during DDR initialization. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- arch/powerpc/cpu/mpc8xxx/law.c | 42 +++++++++++++++++++++++++++++++++--------- 1 file changed, 33 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index 55ee12573f..33d53a8cfe 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -221,6 +221,32 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id) } #endif /* not SPL */ +void disable_non_ddr_laws(void) +{ + int i; + int id; + for (i = 0; i < FSL_HW_NUM_LAWS; i++) { + u32 lawar = in_be32(LAWAR_ADDR(i)); + + if (lawar & LAW_EN) { + id = (lawar & ~LAW_EN) >> 20; + switch (id) { + case LAW_TRGT_IF_DDR_1: + case LAW_TRGT_IF_DDR_2: + case LAW_TRGT_IF_DDR_3: + case LAW_TRGT_IF_DDR_4: + case LAW_TRGT_IF_DDR_INTRLV: + case LAW_TRGT_IF_DDR_INTLV_34: + case LAW_TRGT_IF_DDR_INTLV_123: + case LAW_TRGT_IF_DDR_INTLV_1234: + continue; + default: + disable_law(i); + } + } + } +} + void init_laws(void) { int i; @@ -242,6 +268,13 @@ void init_laws(void) disable_law(0); #endif +#if !defined(CONFIG_SECURE_BOOT) + /* + * if any non DDR LAWs has been created earlier, remove them before + * LAW table is parsed. + */ + disable_non_ddr_laws(); +#endif /* * Any LAWs that were set up before we booted assume they are meant to @@ -254,15 +287,6 @@ void init_laws(void) gd->arch.used_laws |= (1 << i); } -#if (defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)) || \ - (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) - /* - * in SPL boot we've already parsed the law_table and setup those LAWs - * so don't do it again. - */ - return; -#endif - for (i = 0; i < num_law_entries; i++) { if (law_table[i].index == -1) set_next_law(law_table[i].addr, law_table[i].size, -- cgit From 0938b6094ee0389e3231db667d0263cac8bff258 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Mon, 31 Mar 2014 15:31:34 +0530 Subject: powerpc/mpc85xx:Avoid fix address of bootpg section It is not necessary for bootpg to be present at text + 512KB. With increase of u-boot size (768KB), bootpg section's address cannot be fixed. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/u-boot-nand.lds | 8 +++++++- arch/powerpc/cpu/mpc85xx/u-boot.lds | 6 +++++- 2 files changed, 12 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds index df3b0f9168..d77a6dc62d 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds @@ -4,6 +4,12 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include "config.h" /* CONFIG_BOARDDIR */ + +#ifndef CONFIG_SYS_MONITOR_LEN +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#endif + OUTPUT_ARCH(powerpc) /* Do we need any of these for elf? __DYNAMIC = 0; */ @@ -76,7 +82,7 @@ SECTIONS KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg)) } :text = 0xffff - . = ADDR(.text) + 0x80000; + . = ADDR(.text) + CONFIG_SYS_MONITOR_LEN; __bss_start = .; .bss (NOLOAD) : diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index b34d2125f7..0b9086dfd0 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -12,6 +12,10 @@ #define RESET_VECTOR_ADDRESS 0xfffffffc #endif +#ifndef CONFIG_SYS_MONITOR_LEN +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#endif + OUTPUT_ARCH(powerpc) ENTRY(_start_e500) @@ -85,7 +89,7 @@ SECTIONS { KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg)) } :text = 0xffff - . = ADDR(.text) + 0x80000; + . = ADDR(.text) + CONFIG_SYS_MONITOR_LEN; #else .bootpg RESET_VECTOR_ADDRESS - 0xffc : { -- cgit From 0c12a1592c49c4fccea1df3eac9bf769aa1bd503 Mon Sep 17 00:00:00 2001 From: vijay rai Date: Tue, 15 Apr 2014 11:34:12 +0530 Subject: powerpc/85xx: Enhance get_sys_info() to check clocking mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode. In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock (100MHz) to the following PLLs: • Platform PLL • Core PLLs • USB PLL • DDR PLL, etc The cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or DIFF_SYSCLK (differential) is selected as the clock input to the chip. get_sys_info has been enhanced to add the diff_sysclk so that the various drivers can be made aware of ths diff sysclk configuration and act accordingly. Other changes: -single_src to ddr_refclk_sel, as it is use for checking ddr reference clock -Removed the print of single_src from get_sys_info as this will be -printed whenever somebody calls get_sys_info which is not appropriate. -Add print of single_src in checkcpu as it is called only once during initialization Signed-off-by: Poonam Aggrwal Signed-off-by: Priyanka Jain Signed-off-by: Vijay Rai Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/cpu.c | 5 +++++ arch/powerpc/cpu/mpc85xx/speed.c | 21 +++++++++++++-------- arch/powerpc/include/asm/immap_85xx.h | 6 ++++++ 3 files changed, 24 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 2c8126c5f1..12e8e10d48 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -130,6 +130,11 @@ int checkcpu (void) get_sys_info(&sysinfo); +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK + if (sysinfo.diff_sysclk == 1) + puts("Single Source Clock Configuration\n"); +#endif + puts("Clock Configuration:"); for_each_cpu(i, core, nr_cores, mask) { if (!(i & 3)) diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 35dfb0a9a9..2d6c668dce 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -74,28 +74,33 @@ void get_sys_info(sys_info_t *sys_info) uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; unsigned long sysclk = CONFIG_SYS_CLK_FREQ; uint mem_pll_rat; -#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK - uint single_src; -#endif sys_info->freq_systembus = sysclk; #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK + uint ddr_refclk_sel; + unsigned int porsr1_sys_clk; + porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT + & FSL_DCFG_PORSR1_SYSCLK_MASK; + if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF) + sys_info->diff_sysclk = 1; + else + sys_info->diff_sysclk = 0; + /* * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS * are driven by separate DDR Refclock or single source * differential clock. */ - single_src = (in_be32(&gur->rcwsr[5]) >> + ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >> FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) & FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK; /* - * For single source clocking, both ddrclock and syclock + * For single source clocking, both ddrclock and sysclock * are driven by differential sysclock. */ - if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) { - printf("Single Source Clock Configuration\n"); + if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ; - } else + else #endif #ifdef CONFIG_DDR_CLK_FREQ sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index be54920efd..741b8618d1 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1583,6 +1583,12 @@ typedef struct cpc_corenet { typedef struct ccsr_gur { u32 porsr1; /* POR status 1 */ u32 porsr2; /* POR status 2 */ +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK +#define FSL_DCFG_PORSR1_SYSCLK_SHIFT 15 +#define FSL_DCFG_PORSR1_SYSCLK_MASK 0x1 +#define FSL_DCFG_PORSR1_SYSCLK_SINGLE_ENDED 0x1 +#define FSL_DCFG_PORSR1_SYSCLK_DIFF 0x0 +#endif u8 res_008[0x20-0x8]; u32 gpporcr1; /* General-purpose POR configuration */ u32 gpporcr2; /* General-purpose POR configuration 2 */ -- cgit From d1c561cd546353686b28199bf9a90810805c7ada Mon Sep 17 00:00:00 2001 From: Nikhil Badola Date: Tue, 15 Apr 2014 14:44:52 +0530 Subject: powerpc/mpc85xx: Add Differential SYSCLK config support T1040 Adds support for clock sourcing from sysclk(100MHz) for usb on T104xRDB and T1040QDS. This requires changing reference divisor and multiplication factor to derive usb clock from sysclk. Signed-off-by: Nikhil Badola Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index a2b79cc7cc..36ef23232e 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -39,6 +39,29 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK +/* + * For deriving usb clock from 100MHz sysclk, reference divisor is set + * to a value of 5, which gives an intermediate value 20(100/5). The + * multiplication factor integer is set to 24, which when multiplied to + * above intermediate value provides clock for usb ip. + */ +void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy) +{ + sys_info_t sysinfo; + + get_sys_info(&sysinfo); + if (sysinfo.diff_sysclk == 1) { + clrbits_be32(&usb_phy->pllprg[1], + CONFIG_SYS_FSL_USB_PLLPRG2_MFI); + setbits_be32(&usb_phy->pllprg[1], + CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK | + CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK | + CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN); + } +} +#endif + #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy) { @@ -815,6 +838,9 @@ skip_l2: CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | CONFIG_SYS_FSL_USB_PLLPRG2_MFI | CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); +#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK + usb_single_source_clk_configure(usb_phy); +#endif setbits_be32(&usb_phy->port1.ctrl, CONFIG_SYS_FSL_USB_CTRL_PHY_EN); setbits_be32(&usb_phy->port1.drvvbuscfg, -- cgit From b33bd8cd4b7627f64698c6f26739e0c4597bdfbc Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Mon, 21 Apr 2014 10:47:41 +0530 Subject: powerpc/mpc85xx:Update FM1 clock select and shift for B4420 B4420 is a personality of B4860. It should have same FM1_CLK_SEK and FM1_CLK_SHIFT as B4860 Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/speed.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 2d6c668dce..d516d4e4a6 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -163,8 +163,8 @@ void get_sys_info(sys_info_t *sys_info) sys_info->freq_processor[cpu] = freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; } -#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080) || \ - defined(CONFIG_PPC_T2081) +#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \ + defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define FM1_CLK_SEL 0xe0000000 #define FM1_CLK_SHIFT 29 #else -- cgit From 99509695db79668c784158964cc3843e92346926 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sat, 25 Jan 2014 07:53:47 +0100 Subject: mpc8313, bootcount: mpc8313 has no qe muram mpc831x has no muram, so muram cannot be used for bootcounter function. Signed-off-by: Heiko Schocher Signed-off-by: Kim Phillips --- arch/powerpc/cpu/mpc83xx/cpu.c | 2 +- arch/powerpc/cpu/mpc83xx/fdt.c | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index e275fcea41..e41988d5fa 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -19,7 +19,7 @@ #include #include #include -#ifdef CONFIG_BOOTCOUNT_LIMIT +#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x) #include #include #endif diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c index cce7d6b265..450a9704e5 100644 --- a/arch/powerpc/cpu/mpc83xx/fdt.c +++ b/arch/powerpc/cpu/mpc83xx/fdt.c @@ -17,7 +17,7 @@ extern void ft_qe_setup(void *blob); DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_BOOTCOUNT_LIMIT) && \ - (defined(CONFIG_QE)) + (defined(CONFIG_QE) && !defined(CONFIG_MPC831x)) #include void fdt_fixup_muram (void *blob) @@ -124,7 +124,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); -#if defined(CONFIG_BOOTCOUNT_LIMIT) +#if defined(CONFIG_BOOTCOUNT_LIMIT) && \ + (defined(CONFIG_QE) && !defined(CONFIG_MPC831x)) fdt_fixup_muram (blob); #endif } -- cgit From 994b56616bae5bb3fab7122c0aeb346afbb12523 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 31 Mar 2014 13:09:13 +0900 Subject: sh: delete an unused source file Signed-off-by: Masahiro Yamada Cc: Nobuhiro Iwamatsu Acked-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- arch/sh/cpu/sh2/cache.c | 96 ------------------------------------------------- 1 file changed, 96 deletions(-) delete mode 100644 arch/sh/cpu/sh2/cache.c (limited to 'arch') diff --git a/arch/sh/cpu/sh2/cache.c b/arch/sh/cpu/sh2/cache.c deleted file mode 100644 index 8093e98e2a..0000000000 --- a/arch/sh/cpu/sh2/cache.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * (C) Copyright 2007 - * Yoshihiro Shimoda - * - * Copyright (C) 2007, 2008 Nobobuhiro Iwamatsu - * Copyright (C) 2008 Renesas Solutions Corp. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -/* - * Jump to P2 area. - * When handling TLB or caches, we need to do it from P2 area. - */ -#define jump_to_P2() \ -do { \ - unsigned long __dummy; \ - __asm__ __volatile__( \ - "mov.l 1f, %0\n\t" \ - "or %1, %0\n\t" \ - "jmp @%0\n\t" \ - " nop\n\t" \ - ".balign 4\n" \ - "1: .long 2f\n" \ - "2:" \ - : "=&r" (__dummy) \ - : "r" (0x20000000)); \ -} while (0) - -/* - * Back to P1 area. - */ -#define back_to_P1() \ -do { \ - unsigned long __dummy; \ - __asm__ __volatile__( \ - "nop;nop;nop;nop;nop;nop;nop\n\t" \ - "mov.l 1f, %0\n\t" \ - "jmp @%0\n\t" \ - " nop\n\t" \ - ".balign 4\n" \ - "1: .long 2f\n" \ - "2:" \ - : "=&r" (__dummy)); \ -} while (0) - -#define CACHE_VALID 1 -#define CACHE_UPDATED 2 - -static inline void cache_wback_all(void) -{ - unsigned long addr, data, i, j; - - jump_to_P2(); - for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) { - for (j = 0; j < CACHE_OC_NUM_WAYS; j++) { - addr = CACHE_OC_ADDRESS_ARRAY - | (j << CACHE_OC_WAY_SHIFT) - | (i << CACHE_OC_ENTRY_SHIFT); - data = inl(addr); - if (data & CACHE_UPDATED) { - data &= ~CACHE_UPDATED; - outl(data, addr); - } - } - } - back_to_P1(); -} - - -#define CACHE_ENABLE 0 -#define CACHE_DISABLE 1 - -int cache_control(unsigned int cmd) -{ - unsigned long ccr; - - jump_to_P2(); - ccr = inl(CCR); - - if (ccr & CCR_CACHE_ENABLE) - cache_wback_all(); - - if (cmd == CACHE_DISABLE) - outl(CCR_CACHE_STOP, CCR); - else - outl(CCR_CACHE_INIT, CCR); - back_to_P1(); - - return 0; -} -- cgit From ede4d5e3872d04c75a30c5e234786b012f1c6d34 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 3 Apr 2014 13:55:54 +0900 Subject: usb: ehci: rmobile: Add support ehci host driver of rmobile SoCs The rmobile SoC has usb host controller. This supports USB controllers listed in the R8A7790, R8A7791 and R8A7740. Signed-off-by: Nobuhiro Iwamatsu Reviewed-by: Marek Vasut --- arch/arm/include/asm/arch-rmobile/ehci-rmobile.h | 147 +++++++++++++++++++++++ 1 file changed, 147 insertions(+) create mode 100644 arch/arm/include/asm/arch-rmobile/ehci-rmobile.h (limited to 'arch') diff --git a/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h b/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h new file mode 100644 index 0000000000..463654efd3 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2013,2014 Renesas Electronics Corporation + * Copyright (C) 2014 Nobuhiro Iwamatsu + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __EHCI_RMOBILE_H__ +#define __EHCI_RMOBILE_H__ + +/* Register offset */ +#define OHCI_OFFSET 0x00 +#define OHCI_SIZE 0x1000 +#define EHCI_OFFSET 0x1000 +#define EHCI_SIZE 0x1000 + +#define EHCI_USBCMD (EHCI_OFFSET + 0x0020) + +/* USBCTR */ +#define DIRPD (1 << 8) +#define PLL_RST (1 << 2) +#define PCICLK_MASK (1 << 1) +#define USBH_RST (1 << 0) + +/* CMND_STS */ +#define SERREN (1 << 8) +#define PERREN (1 << 6) +#define MASTEREN (1 << 2) +#define MEMEN (1 << 1) + +/* PCIAHB_WIN1_CTR and PCIAHB_WIN2_CTR */ +#define PCIAHB_WIN_PREFETCH ((1 << 1)|(1 << 0)) + +/* AHBPCI_WIN1_CTR */ +#define PCIWIN1_PCICMD ((1 << 3)|(1 << 1)) +#define AHB_CFG_AHBPCI 0x40000000 +#define AHB_CFG_HOST 0x80000000 + +/* AHBPCI_WIN2_CTR */ +#define PCIWIN2_PCICMD ((1 << 2)|(1 << 1)) + +/* PCI_INT_ENABLE */ +#define USBH_PMEEN (1 << 19) +#define USBH_INTBEN (1 << 17) +#define USBH_INTAEN (1 << 16) + +/* AHB_BUS_CTR */ +#define SMODE_READY_CTR (1 << 17) +#define SMODE_READ_BURST (1 << 16) +#define MMODE_HBUSREQ (1 << 7) +#define MMODE_BOUNDARY ((1 << 6)|(1 << 5)) +#define MMODE_BURST_WIDTH ((1 << 4)|(1 << 3)) +#define MMODE_SINGLE_MODE ((1 << 4)|(1 << 3)) +#define MMODE_WR_INCR (1 << 2) +#define MMODE_BYTE_BURST (1 << 1) +#define MMODE_HTRANS (1 << 0) + +/* PCI_ARBITER_CTR */ +#define PCIBUS_PARK_TIMER 0x00FF0000 +#define PCIBUS_PARK_TIMER_SET 0x00070000 +#define PCIBP_MODE (1 << 12) +#define PCIREQ7 (1 << 7) +#define PCIREQ6 (1 << 6) +#define PCIREQ5 (1 << 5) +#define PCIREQ4 (1 << 4) +#define PCIREQ3 (1 << 3) +#define PCIREQ2 (1 << 2) +#define PCIREQ1 (1 << 1) +#define PCIREQ0 (1 << 0) + +#define SMSTPCR7 0xE615014C +#define SMSTPCR703 (1 << 3) + +/* Init AHB master and slave functions of the host logic */ +#define AHB_BUS_CTR_INIT \ + (SMODE_READY_CTR | MMODE_HBUSREQ | MMODE_WR_INCR | \ + MMODE_BYTE_BURST | MMODE_HTRANS) + +#define USBCTR_WIN_SIZE_1GB 0x800 + +/* PCI Configuration Registers */ +#define PCI_CONF_OHCI_OFFSET 0x10000 +#define PCI_CONF_EHCI_OFFSET 0x10100 +struct ahb_pciconf { + u32 vid_did; + u32 cmnd_sts; + u32 rev; + u32 cache_line; + u32 basead; +}; + +/* PCI Configuration Registers for AHB-PCI Bridge Registers */ +#define PCI_CONF_AHBPCI_OFFSET 0x10000 +struct ahbconf_pci_bridge { + u32 vid_did; /* 0x00 */ + u32 cmnd_sts; + u32 revid_cc; + u32 cls_lt_ht_bist; + u32 basead; /* 0x10 */ + u32 win1_basead; + u32 win2_basead; + u32 dummy0[5]; + u32 ssvdi_ssid; /* 0x2C */ + u32 dummy1[4]; + u32 intr_line_pin; +}; + +/* AHB-PCI Bridge PCI Communication Registers */ +#define AHBPCI_OFFSET 0x10800 +struct ahbcom_pci_bridge { + u32 pciahb_win1_ctr; /* 0x00 */ + u32 pciahb_win2_ctr; + u32 pciahb_dct_ctr; + u32 dummy0; + u32 ahbpci_win1_ctr; /* 0x10 */ + u32 ahbpci_win2_ctr; + u32 dummy1; + u32 ahbpci_dct_ctr; + u32 pci_int_enable; /* 0x20 */ + u32 pci_int_status; + u32 dummy2[2]; + u32 ahb_bus_ctr; /* 0x30 */ + u32 usbctr; + u32 dummy3[2]; + u32 pci_arbiter_ctr; /* 0x40 */ + u32 dummy4; + u32 pci_unit_rev; /* 0x48 */ +}; + +struct rmobile_ehci_reg { + u32 hciversion; /* hciversion/caplength */ + u32 hcsparams; /* hcsparams */ + u32 hccparams; /* hccparams */ + u32 hcsp_portroute; /* hcsp_portroute */ + u32 usbcmd; /* usbcmd */ + u32 usbsts; /* usbsts */ + u32 usbintr; /* usbintr */ + u32 frindex; /* frindex */ + u32 ctrldssegment; /* ctrldssegment */ + u32 periodiclistbase; /* periodiclistbase */ + u32 asynclistaddr; /* asynclistaddr */ + u32 dummy[9]; + u32 configflag; /* configflag */ + u32 portsc; /* portsc */ +}; + +#endif /* __EHCI_RMOBILE_H__ */ -- cgit