From df8a24cdd30151505cf57bbee5289e91bf53bd1b Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 19 Jun 2007 16:42:31 +0200 Subject: [ppc4xx] Fix problem with NAND booting on AMCC Acadia The latest changes showed a problem with the location of the NAND-SPL image in the OCM and the init-data area (incl. cache). This patch fixes this problem. Signed-off-by: Stefan Roese --- board/amcc/acadia/memory.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'board/amcc/acadia/memory.c') diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c index 25904d3b94..9346d2c52f 100644 --- a/board/amcc/acadia/memory.c +++ b/board/amcc/acadia/memory.c @@ -31,6 +31,8 @@ #include #include +extern void board_pll_init_f(void); + /* * sdram_init - Dummy implementation for start.S, spd_sdram used on this board! */ @@ -67,6 +69,15 @@ static void cram_bcr_write(u32 wr_val) long int initdram(int board_type) { +#if defined(CONFIG_NAND_SPL) + u32 reg; + + /* don't reinit PLL when booting via I2C bootstrap option */ + mfsdr(SDR_PINSTP, reg); + if (reg != 0xf0000000) + board_pll_init_f(); +#endif + #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) int i; u32 val; -- cgit