From f544ff6656fca263ed1ebe39899b6d95da67c8b8 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 5 May 2007 08:29:01 +0200 Subject: ppc4xx: Sequoia: Remove cpu/ppc4xx/speed.c from NAND booting Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big for the 4k NAND boot image so define bus_frequency to 133MHz here which is save for the refresh counter setup. Signed-off-by: Stefan Roese --- board/amcc/sequoia/sdram.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'board/amcc/sequoia/sdram.c') diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c index f8b837ed28..d045df1872 100644 --- a/board/amcc/sequoia/sdram.c +++ b/board/amcc/sequoia/sdram.c @@ -371,6 +371,14 @@ void denali_core_search_data_eye(unsigned long memory_size) } #endif /* CONFIG_DDR_DATA_EYE */ +#if defined(CONFIG_NAND_SPL) +/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big + * for the 4k NAND boot image so define bus_frequency to 133MHz here + * which is save for the refresh counter setup. + */ +#define get_bus_freq(val) 133000000 +#endif + /************************************************************************* * * initdram -- 440EPx's DDR controller is a DENALI Core @@ -404,7 +412,7 @@ long int initdram (int board_type) mtsdram(DDR0_22, 0x00267F0B); mtsdram(DDR0_23, 0x00000000); mtsdram(DDR0_24, 0x01010002); - if (speed > 133333333) + if (speed > 133333334) mtsdram(DDR0_26, 0x5B26050C); else mtsdram(DDR0_26, 0x5B260408); -- cgit From 9d9096043e8f713d4bf1743d32e1459e6a11644b Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 1 Jun 2007 15:29:04 +0200 Subject: ppc4xx: Update Sequoia NAND booting support with ECC Signed-off-by: Stefan Roese --- board/amcc/sequoia/sdram.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'board/amcc/sequoia/sdram.c') diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c index f8b837ed28..826d192501 100644 --- a/board/amcc/sequoia/sdram.c +++ b/board/amcc/sequoia/sdram.c @@ -379,7 +379,11 @@ void denali_core_search_data_eye(unsigned long memory_size) long int initdram (int board_type) { #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) +#if !defined(CONFIG_NAND_SPL) ulong speed = get_bus_freq(0); +#else + ulong speed = 133333333; /* 133MHz is on the safe side */ +#endif mtsdram(DDR0_02, 0x00000000); -- cgit