From ab687907980fa28940a1a992d3f1c5d17cdbbf5d Mon Sep 17 00:00:00 2001 From: Graf Yang Date: Sun, 24 May 2009 02:34:34 -0400 Subject: Blackfin: bf518f-ezbrd: setup portmux for async flash The pins for async memory where parallel flash lives are not enabled by default, so make sure we mux them as needed. Signed-off-by: Graf Yang Signed-off-by: Mike Frysinger --- board/bf518f-ezbrd/bf518f-ezbrd.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'board/bf518f-ezbrd/bf518f-ezbrd.c') diff --git a/board/bf518f-ezbrd/bf518f-ezbrd.c b/board/bf518f-ezbrd/bf518f-ezbrd.c index ec5a7ed0b1..63be7cf06c 100644 --- a/board/bf518f-ezbrd/bf518f-ezbrd.c +++ b/board/bf518f-ezbrd/bf518f-ezbrd.c @@ -146,3 +146,19 @@ int misc_init_r(void) return 0; } + +int board_early_init_f(void) +{ +#if !defined(CONFIG_SYS_NO_FLASH) + /* setup BF518-EZBRD GPIO pin PG11 to AMS2. */ + bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2); + bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG11); + +# if !defined(CONFIG_BFIN_SPI) + /* setup BF518-EZBRD GPIO pin PG15 to AMS3. */ + bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_7_MASK) | PORT_x_MUX_7_FUNC_3); + bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG15); +# endif +#endif + return 0; +} -- cgit